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authorYaniv Rosner <yanivr@broadcom.com>2011-05-31 17:29:27 -0400
committerDavid S. Miller <davem@davemloft.net>2011-06-01 16:10:57 -0400
commitec146a6f019923819f5ca381980248b6d154ca1a (patch)
tree51661eb802f6ea5934eb4ab925f3394ff9b34a9c /drivers/net/bnx2x/bnx2x_link.c
parentfd36a2e69e05f42ddfe388efe14e068c0d0c6cb7 (diff)
bnx2x: Modify XGXS functions
Modify XGXS functions to follow rest of PHY scheme. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c89
1 files changed, 36 insertions, 53 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index 1816b2d5b71..43e3663ab33 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -1530,8 +1530,8 @@ int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1530 return -EINVAL; 1530 return -EINVAL;
1531} 1531}
1532 1532
1533static void bnx2x_set_aer_mmd_xgxs(struct link_params *params, 1533static void bnx2x_set_aer_mmd(struct link_params *params,
1534 struct bnx2x_phy *phy) 1534 struct bnx2x_phy *phy)
1535{ 1535{
1536 u32 ser_lane; 1536 u32 ser_lane;
1537 u16 offset, aer_val; 1537 u16 offset, aer_val;
@@ -1540,20 +1540,17 @@ static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1540 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1540 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1541 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1541 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1542 1542
1543 offset = phy->addr + ser_lane; 1543 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
1544 (phy->addr + ser_lane) : 0;
1545
1544 if (CHIP_IS_E2(bp)) 1546 if (CHIP_IS_E2(bp))
1545 aer_val = 0x3800 + offset - 1; 1547 aer_val = 0x3800 + offset - 1;
1546 else 1548 else
1547 aer_val = 0x3800 + offset; 1549 aer_val = 0x3800 + offset;
1550 DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
1548 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 1551 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
1549 MDIO_AER_BLOCK_AER_REG, aer_val); 1552 MDIO_AER_BLOCK_AER_REG, aer_val);
1550} 1553
1551static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1552 struct bnx2x_phy *phy)
1553{
1554 CL22_WR_OVER_CL45(bp, phy,
1555 MDIO_REG_BANK_AER_BLOCK,
1556 MDIO_AER_BLOCK_AER_REG, 0x3800);
1557} 1554}
1558 1555
1559/******************************************************************/ 1556/******************************************************************/
@@ -2845,9 +2842,9 @@ static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2845 } 2842 }
2846} 2843}
2847 2844
2848static void bnx2x_init_internal_phy(struct bnx2x_phy *phy, 2845static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
2849 struct link_params *params, 2846 struct link_params *params,
2850 struct link_vars *vars) 2847 struct link_vars *vars)
2851{ 2848{
2852 struct bnx2x *bp = params->bp; 2849 struct bnx2x *bp = params->bp;
2853 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || 2850 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
@@ -2894,29 +2891,12 @@ static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2894 } 2891 }
2895} 2892}
2896 2893
2897static int bnx2x_init_serdes(struct bnx2x_phy *phy, 2894static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
2898 struct link_params *params, 2895 struct link_params *params,
2899 struct link_vars *vars) 2896 struct link_vars *vars)
2900{
2901 int rc;
2902 vars->phy_flags |= PHY_SGMII_FLAG;
2903 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2904 bnx2x_set_aer_mmd_serdes(params->bp, phy);
2905 rc = bnx2x_reset_unicore(params, phy, 1);
2906 /* reset the SerDes and wait for reset bit return low */
2907 if (rc != 0)
2908 return rc;
2909 bnx2x_set_aer_mmd_serdes(params->bp, phy);
2910
2911 return rc;
2912}
2913
2914static int bnx2x_init_xgxs(struct bnx2x_phy *phy,
2915 struct link_params *params,
2916 struct link_vars *vars)
2917{ 2897{
2918 int rc; 2898 int rc;
2919 vars->phy_flags = PHY_XGXS_FLAG; 2899 vars->phy_flags |= PHY_XGXS_FLAG;
2920 if ((phy->req_line_speed && 2900 if ((phy->req_line_speed &&
2921 ((phy->req_line_speed == SPEED_100) || 2901 ((phy->req_line_speed == SPEED_100) ||
2922 (phy->req_line_speed == SPEED_10))) || 2902 (phy->req_line_speed == SPEED_10))) ||
@@ -2924,26 +2904,28 @@ static int bnx2x_init_xgxs(struct bnx2x_phy *phy,
2924 (phy->speed_cap_mask >= 2904 (phy->speed_cap_mask >=
2925 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 2905 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2926 (phy->speed_cap_mask < 2906 (phy->speed_cap_mask <
2927 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 2907 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
2928 )) 2908 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
2929 vars->phy_flags |= PHY_SGMII_FLAG; 2909 vars->phy_flags |= PHY_SGMII_FLAG;
2930 else 2910 else
2931 vars->phy_flags &= ~PHY_SGMII_FLAG; 2911 vars->phy_flags &= ~PHY_SGMII_FLAG;
2932 2912
2933 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 2913 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2934 bnx2x_set_aer_mmd_xgxs(params, phy); 2914 bnx2x_set_aer_mmd(params, phy);
2935 bnx2x_set_master_ln(params, phy); 2915 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
2916 bnx2x_set_master_ln(params, phy);
2936 2917
2937 rc = bnx2x_reset_unicore(params, phy, 0); 2918 rc = bnx2x_reset_unicore(params, phy, 0);
2938 /* reset the SerDes and wait for reset bit return low */ 2919 /* reset the SerDes and wait for reset bit return low */
2939 if (rc != 0) 2920 if (rc != 0)
2940 return rc; 2921 return rc;
2941 2922
2942 bnx2x_set_aer_mmd_xgxs(params, phy); 2923 bnx2x_set_aer_mmd(params, phy);
2943
2944 /* setting the masterLn_def again after the reset */ 2924 /* setting the masterLn_def again after the reset */
2945 bnx2x_set_master_ln(params, phy); 2925 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
2946 bnx2x_set_swap_lanes(params, phy); 2926 bnx2x_set_master_ln(params, phy);
2927 bnx2x_set_swap_lanes(params, phy);
2928 }
2947 2929
2948 return rc; 2930 return rc;
2949} 2931}
@@ -3220,7 +3202,7 @@ static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3220 0x6041); 3202 0x6041);
3221 msleep(200); 3203 msleep(200);
3222 /* set aer mmd back */ 3204 /* set aer mmd back */
3223 bnx2x_set_aer_mmd_xgxs(params, phy); 3205 bnx2x_set_aer_mmd(params, phy);
3224 3206
3225 /* and md_devad */ 3207 /* and md_devad */
3226 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad); 3208 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
@@ -3420,11 +3402,7 @@ static int bnx2x_link_initialize(struct link_params *params,
3420 * to first. 3402 * to first.
3421 */ 3403 */
3422 3404
3423 if (params->phy[INT_PHY].config_init) 3405 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
3424 params->phy[INT_PHY].config_init(
3425 &params->phy[INT_PHY],
3426 params, vars);
3427
3428 /* init ext phy and enable link state int */ 3406 /* init ext phy and enable link state int */
3429 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || 3407 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3430 (params->loopback_mode == LOOPBACK_XGXS)); 3408 (params->loopback_mode == LOOPBACK_XGXS));
@@ -3435,7 +3413,10 @@ static int bnx2x_link_initialize(struct link_params *params,
3435 struct bnx2x_phy *phy = &params->phy[INT_PHY]; 3413 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3436 if (vars->line_speed == SPEED_AUTO_NEG) 3414 if (vars->line_speed == SPEED_AUTO_NEG)
3437 bnx2x_set_parallel_detection(phy, params); 3415 bnx2x_set_parallel_detection(phy, params);
3438 bnx2x_init_internal_phy(phy, params, vars); 3416 if (params->phy[INT_PHY].config_init)
3417 params->phy[INT_PHY].config_init(phy,
3418 params,
3419 vars);
3439 } 3420 }
3440 3421
3441 /* Init external phy*/ 3422 /* Init external phy*/
@@ -3827,8 +3808,10 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3827 vars->phy_flags |= PHY_SGMII_FLAG; 3808 vars->phy_flags |= PHY_SGMII_FLAG;
3828 else 3809 else
3829 vars->phy_flags &= ~PHY_SGMII_FLAG; 3810 vars->phy_flags &= ~PHY_SGMII_FLAG;
3830 bnx2x_init_internal_phy(&params->phy[INT_PHY], 3811
3831 params, 3812 if (params->phy[INT_PHY].config_init)
3813 params->phy[INT_PHY].config_init(
3814 &params->phy[INT_PHY], params,
3832 vars); 3815 vars);
3833 } 3816 }
3834 } 3817 }
@@ -7119,7 +7102,7 @@ static struct bnx2x_phy phy_serdes = {
7119 .speed_cap_mask = 0, 7102 .speed_cap_mask = 0,
7120 .req_duplex = 0, 7103 .req_duplex = 0,
7121 .rsrv = 0, 7104 .rsrv = 0,
7122 .config_init = (config_init_t)bnx2x_init_serdes, 7105 .config_init = (config_init_t)bnx2x_xgxs_config_init,
7123 .read_status = (read_status_t)bnx2x_link_settings_status, 7106 .read_status = (read_status_t)bnx2x_link_settings_status,
7124 .link_reset = (link_reset_t)bnx2x_int_link_reset, 7107 .link_reset = (link_reset_t)bnx2x_int_link_reset,
7125 .config_loopback = (config_loopback_t)NULL, 7108 .config_loopback = (config_loopback_t)NULL,
@@ -7155,7 +7138,7 @@ static struct bnx2x_phy phy_xgxs = {
7155 .speed_cap_mask = 0, 7138 .speed_cap_mask = 0,
7156 .req_duplex = 0, 7139 .req_duplex = 0,
7157 .rsrv = 0, 7140 .rsrv = 0,
7158 .config_init = (config_init_t)bnx2x_init_xgxs, 7141 .config_init = (config_init_t)bnx2x_xgxs_config_init,
7159 .read_status = (read_status_t)bnx2x_link_settings_status, 7142 .read_status = (read_status_t)bnx2x_link_settings_status,
7160 .link_reset = (link_reset_t)bnx2x_int_link_reset, 7143 .link_reset = (link_reset_t)bnx2x_int_link_reset,
7161 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, 7144 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,