diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
---|---|---|
committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
commit | fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch) | |
tree | a57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/net/benet/be_cmds.h | |
parent | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff) |
Diffstat (limited to 'drivers/net/benet/be_cmds.h')
-rw-r--r-- | drivers/net/benet/be_cmds.h | 1551 |
1 files changed, 1551 insertions, 0 deletions
diff --git a/drivers/net/benet/be_cmds.h b/drivers/net/benet/be_cmds.h new file mode 100644 index 00000000000..8e4d48824fe --- /dev/null +++ b/drivers/net/benet/be_cmds.h | |||
@@ -0,0 +1,1551 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2005 - 2011 Emulex | ||
3 | * All rights reserved. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License version 2 | ||
7 | * as published by the Free Software Foundation. The full GNU General | ||
8 | * Public License is included in this distribution in the file called COPYING. | ||
9 | * | ||
10 | * Contact Information: | ||
11 | * linux-drivers@emulex.com | ||
12 | * | ||
13 | * Emulex | ||
14 | * 3333 Susan Street | ||
15 | * Costa Mesa, CA 92626 | ||
16 | */ | ||
17 | |||
18 | /* | ||
19 | * The driver sends configuration and managements command requests to the | ||
20 | * firmware in the BE. These requests are communicated to the processor | ||
21 | * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one | ||
22 | * WRB inside a MAILBOX. | ||
23 | * The commands are serviced by the ARM processor in the BladeEngine's MPU. | ||
24 | */ | ||
25 | |||
26 | struct be_sge { | ||
27 | u32 pa_lo; | ||
28 | u32 pa_hi; | ||
29 | u32 len; | ||
30 | }; | ||
31 | |||
32 | #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ | ||
33 | #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ | ||
34 | #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ | ||
35 | struct be_mcc_wrb { | ||
36 | u32 embedded; /* dword 0 */ | ||
37 | u32 payload_length; /* dword 1 */ | ||
38 | u32 tag0; /* dword 2 */ | ||
39 | u32 tag1; /* dword 3 */ | ||
40 | u32 rsvd; /* dword 4 */ | ||
41 | union { | ||
42 | u8 embedded_payload[236]; /* used by embedded cmds */ | ||
43 | struct be_sge sgl[19]; /* used by non-embedded cmds */ | ||
44 | } payload; | ||
45 | }; | ||
46 | |||
47 | #define CQE_FLAGS_VALID_MASK (1 << 31) | ||
48 | #define CQE_FLAGS_ASYNC_MASK (1 << 30) | ||
49 | #define CQE_FLAGS_COMPLETED_MASK (1 << 28) | ||
50 | #define CQE_FLAGS_CONSUMED_MASK (1 << 27) | ||
51 | |||
52 | /* Completion Status */ | ||
53 | enum { | ||
54 | MCC_STATUS_SUCCESS = 0, | ||
55 | MCC_STATUS_FAILED = 1, | ||
56 | MCC_STATUS_ILLEGAL_REQUEST = 2, | ||
57 | MCC_STATUS_ILLEGAL_FIELD = 3, | ||
58 | MCC_STATUS_INSUFFICIENT_BUFFER = 4, | ||
59 | MCC_STATUS_UNAUTHORIZED_REQUEST = 5, | ||
60 | MCC_STATUS_NOT_SUPPORTED = 66 | ||
61 | }; | ||
62 | |||
63 | #define CQE_STATUS_COMPL_MASK 0xFFFF | ||
64 | #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */ | ||
65 | #define CQE_STATUS_EXTD_MASK 0xFFFF | ||
66 | #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */ | ||
67 | |||
68 | struct be_mcc_compl { | ||
69 | u32 status; /* dword 0 */ | ||
70 | u32 tag0; /* dword 1 */ | ||
71 | u32 tag1; /* dword 2 */ | ||
72 | u32 flags; /* dword 3 */ | ||
73 | }; | ||
74 | |||
75 | /* When the async bit of mcc_compl is set, the last 4 bytes of | ||
76 | * mcc_compl is interpreted as follows: | ||
77 | */ | ||
78 | #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ | ||
79 | #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF | ||
80 | #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16 | ||
81 | #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF | ||
82 | #define ASYNC_EVENT_CODE_LINK_STATE 0x1 | ||
83 | #define ASYNC_EVENT_CODE_GRP_5 0x5 | ||
84 | #define ASYNC_EVENT_QOS_SPEED 0x1 | ||
85 | #define ASYNC_EVENT_COS_PRIORITY 0x2 | ||
86 | #define ASYNC_EVENT_PVID_STATE 0x3 | ||
87 | struct be_async_event_trailer { | ||
88 | u32 code; | ||
89 | }; | ||
90 | |||
91 | enum { | ||
92 | ASYNC_EVENT_LINK_DOWN = 0x0, | ||
93 | ASYNC_EVENT_LINK_UP = 0x1 | ||
94 | }; | ||
95 | |||
96 | /* When the event code of an async trailer is link-state, the mcc_compl | ||
97 | * must be interpreted as follows | ||
98 | */ | ||
99 | struct be_async_event_link_state { | ||
100 | u8 physical_port; | ||
101 | u8 port_link_status; | ||
102 | u8 port_duplex; | ||
103 | u8 port_speed; | ||
104 | u8 port_fault; | ||
105 | u8 rsvd0[7]; | ||
106 | struct be_async_event_trailer trailer; | ||
107 | } __packed; | ||
108 | |||
109 | /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED | ||
110 | * the mcc_compl must be interpreted as follows | ||
111 | */ | ||
112 | struct be_async_event_grp5_qos_link_speed { | ||
113 | u8 physical_port; | ||
114 | u8 rsvd[5]; | ||
115 | u16 qos_link_speed; | ||
116 | u32 event_tag; | ||
117 | struct be_async_event_trailer trailer; | ||
118 | } __packed; | ||
119 | |||
120 | /* When the event code of an async trailer is GRP5 and event type is | ||
121 | * CoS-Priority, the mcc_compl must be interpreted as follows | ||
122 | */ | ||
123 | struct be_async_event_grp5_cos_priority { | ||
124 | u8 physical_port; | ||
125 | u8 available_priority_bmap; | ||
126 | u8 reco_default_priority; | ||
127 | u8 valid; | ||
128 | u8 rsvd0; | ||
129 | u8 event_tag; | ||
130 | struct be_async_event_trailer trailer; | ||
131 | } __packed; | ||
132 | |||
133 | /* When the event code of an async trailer is GRP5 and event type is | ||
134 | * PVID state, the mcc_compl must be interpreted as follows | ||
135 | */ | ||
136 | struct be_async_event_grp5_pvid_state { | ||
137 | u8 enabled; | ||
138 | u8 rsvd0; | ||
139 | u16 tag; | ||
140 | u32 event_tag; | ||
141 | u32 rsvd1; | ||
142 | struct be_async_event_trailer trailer; | ||
143 | } __packed; | ||
144 | |||
145 | struct be_mcc_mailbox { | ||
146 | struct be_mcc_wrb wrb; | ||
147 | struct be_mcc_compl compl; | ||
148 | }; | ||
149 | |||
150 | #define CMD_SUBSYSTEM_COMMON 0x1 | ||
151 | #define CMD_SUBSYSTEM_ETH 0x3 | ||
152 | #define CMD_SUBSYSTEM_LOWLEVEL 0xb | ||
153 | |||
154 | #define OPCODE_COMMON_NTWK_MAC_QUERY 1 | ||
155 | #define OPCODE_COMMON_NTWK_MAC_SET 2 | ||
156 | #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 | ||
157 | #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 | ||
158 | #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 | ||
159 | #define OPCODE_COMMON_READ_FLASHROM 6 | ||
160 | #define OPCODE_COMMON_WRITE_FLASHROM 7 | ||
161 | #define OPCODE_COMMON_CQ_CREATE 12 | ||
162 | #define OPCODE_COMMON_EQ_CREATE 13 | ||
163 | #define OPCODE_COMMON_MCC_CREATE 21 | ||
164 | #define OPCODE_COMMON_SET_QOS 28 | ||
165 | #define OPCODE_COMMON_MCC_CREATE_EXT 90 | ||
166 | #define OPCODE_COMMON_SEEPROM_READ 30 | ||
167 | #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 | ||
168 | #define OPCODE_COMMON_NTWK_RX_FILTER 34 | ||
169 | #define OPCODE_COMMON_GET_FW_VERSION 35 | ||
170 | #define OPCODE_COMMON_SET_FLOW_CONTROL 36 | ||
171 | #define OPCODE_COMMON_GET_FLOW_CONTROL 37 | ||
172 | #define OPCODE_COMMON_SET_FRAME_SIZE 39 | ||
173 | #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 | ||
174 | #define OPCODE_COMMON_FIRMWARE_CONFIG 42 | ||
175 | #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 | ||
176 | #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 | ||
177 | #define OPCODE_COMMON_MCC_DESTROY 53 | ||
178 | #define OPCODE_COMMON_CQ_DESTROY 54 | ||
179 | #define OPCODE_COMMON_EQ_DESTROY 55 | ||
180 | #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 | ||
181 | #define OPCODE_COMMON_NTWK_PMAC_ADD 59 | ||
182 | #define OPCODE_COMMON_NTWK_PMAC_DEL 60 | ||
183 | #define OPCODE_COMMON_FUNCTION_RESET 61 | ||
184 | #define OPCODE_COMMON_MANAGE_FAT 68 | ||
185 | #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 | ||
186 | #define OPCODE_COMMON_GET_BEACON_STATE 70 | ||
187 | #define OPCODE_COMMON_READ_TRANSRECV_DATA 73 | ||
188 | #define OPCODE_COMMON_GET_PHY_DETAILS 102 | ||
189 | #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 | ||
190 | #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 | ||
191 | #define OPCODE_COMMON_WRITE_OBJECT 172 | ||
192 | |||
193 | #define OPCODE_ETH_RSS_CONFIG 1 | ||
194 | #define OPCODE_ETH_ACPI_CONFIG 2 | ||
195 | #define OPCODE_ETH_PROMISCUOUS 3 | ||
196 | #define OPCODE_ETH_GET_STATISTICS 4 | ||
197 | #define OPCODE_ETH_TX_CREATE 7 | ||
198 | #define OPCODE_ETH_RX_CREATE 8 | ||
199 | #define OPCODE_ETH_TX_DESTROY 9 | ||
200 | #define OPCODE_ETH_RX_DESTROY 10 | ||
201 | #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 | ||
202 | #define OPCODE_ETH_GET_PPORT_STATS 18 | ||
203 | |||
204 | #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 | ||
205 | #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 | ||
206 | #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 | ||
207 | |||
208 | struct be_cmd_req_hdr { | ||
209 | u8 opcode; /* dword 0 */ | ||
210 | u8 subsystem; /* dword 0 */ | ||
211 | u8 port_number; /* dword 0 */ | ||
212 | u8 domain; /* dword 0 */ | ||
213 | u32 timeout; /* dword 1 */ | ||
214 | u32 request_length; /* dword 2 */ | ||
215 | u8 version; /* dword 3 */ | ||
216 | u8 rsvd[3]; /* dword 3 */ | ||
217 | }; | ||
218 | |||
219 | #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ | ||
220 | #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ | ||
221 | struct be_cmd_resp_hdr { | ||
222 | u32 info; /* dword 0 */ | ||
223 | u32 status; /* dword 1 */ | ||
224 | u32 response_length; /* dword 2 */ | ||
225 | u32 actual_resp_len; /* dword 3 */ | ||
226 | }; | ||
227 | |||
228 | struct phys_addr { | ||
229 | u32 lo; | ||
230 | u32 hi; | ||
231 | }; | ||
232 | |||
233 | /************************** | ||
234 | * BE Command definitions * | ||
235 | **************************/ | ||
236 | |||
237 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
238 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
239 | struct amap_eq_context { | ||
240 | u8 cidx[13]; /* dword 0*/ | ||
241 | u8 rsvd0[3]; /* dword 0*/ | ||
242 | u8 epidx[13]; /* dword 0*/ | ||
243 | u8 valid; /* dword 0*/ | ||
244 | u8 rsvd1; /* dword 0*/ | ||
245 | u8 size; /* dword 0*/ | ||
246 | u8 pidx[13]; /* dword 1*/ | ||
247 | u8 rsvd2[3]; /* dword 1*/ | ||
248 | u8 pd[10]; /* dword 1*/ | ||
249 | u8 count[3]; /* dword 1*/ | ||
250 | u8 solevent; /* dword 1*/ | ||
251 | u8 stalled; /* dword 1*/ | ||
252 | u8 armed; /* dword 1*/ | ||
253 | u8 rsvd3[4]; /* dword 2*/ | ||
254 | u8 func[8]; /* dword 2*/ | ||
255 | u8 rsvd4; /* dword 2*/ | ||
256 | u8 delaymult[10]; /* dword 2*/ | ||
257 | u8 rsvd5[2]; /* dword 2*/ | ||
258 | u8 phase[2]; /* dword 2*/ | ||
259 | u8 nodelay; /* dword 2*/ | ||
260 | u8 rsvd6[4]; /* dword 2*/ | ||
261 | u8 rsvd7[32]; /* dword 3*/ | ||
262 | } __packed; | ||
263 | |||
264 | struct be_cmd_req_eq_create { | ||
265 | struct be_cmd_req_hdr hdr; | ||
266 | u16 num_pages; /* sword */ | ||
267 | u16 rsvd0; /* sword */ | ||
268 | u8 context[sizeof(struct amap_eq_context) / 8]; | ||
269 | struct phys_addr pages[8]; | ||
270 | } __packed; | ||
271 | |||
272 | struct be_cmd_resp_eq_create { | ||
273 | struct be_cmd_resp_hdr resp_hdr; | ||
274 | u16 eq_id; /* sword */ | ||
275 | u16 rsvd0; /* sword */ | ||
276 | } __packed; | ||
277 | |||
278 | /******************** Mac query ***************************/ | ||
279 | enum { | ||
280 | MAC_ADDRESS_TYPE_STORAGE = 0x0, | ||
281 | MAC_ADDRESS_TYPE_NETWORK = 0x1, | ||
282 | MAC_ADDRESS_TYPE_PD = 0x2, | ||
283 | MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 | ||
284 | }; | ||
285 | |||
286 | struct mac_addr { | ||
287 | u16 size_of_struct; | ||
288 | u8 addr[ETH_ALEN]; | ||
289 | } __packed; | ||
290 | |||
291 | struct be_cmd_req_mac_query { | ||
292 | struct be_cmd_req_hdr hdr; | ||
293 | u8 type; | ||
294 | u8 permanent; | ||
295 | u16 if_id; | ||
296 | } __packed; | ||
297 | |||
298 | struct be_cmd_resp_mac_query { | ||
299 | struct be_cmd_resp_hdr hdr; | ||
300 | struct mac_addr mac; | ||
301 | }; | ||
302 | |||
303 | /******************** PMac Add ***************************/ | ||
304 | struct be_cmd_req_pmac_add { | ||
305 | struct be_cmd_req_hdr hdr; | ||
306 | u32 if_id; | ||
307 | u8 mac_address[ETH_ALEN]; | ||
308 | u8 rsvd0[2]; | ||
309 | } __packed; | ||
310 | |||
311 | struct be_cmd_resp_pmac_add { | ||
312 | struct be_cmd_resp_hdr hdr; | ||
313 | u32 pmac_id; | ||
314 | }; | ||
315 | |||
316 | /******************** PMac Del ***************************/ | ||
317 | struct be_cmd_req_pmac_del { | ||
318 | struct be_cmd_req_hdr hdr; | ||
319 | u32 if_id; | ||
320 | u32 pmac_id; | ||
321 | }; | ||
322 | |||
323 | /******************** Create CQ ***************************/ | ||
324 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
325 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
326 | struct amap_cq_context_be { | ||
327 | u8 cidx[11]; /* dword 0*/ | ||
328 | u8 rsvd0; /* dword 0*/ | ||
329 | u8 coalescwm[2]; /* dword 0*/ | ||
330 | u8 nodelay; /* dword 0*/ | ||
331 | u8 epidx[11]; /* dword 0*/ | ||
332 | u8 rsvd1; /* dword 0*/ | ||
333 | u8 count[2]; /* dword 0*/ | ||
334 | u8 valid; /* dword 0*/ | ||
335 | u8 solevent; /* dword 0*/ | ||
336 | u8 eventable; /* dword 0*/ | ||
337 | u8 pidx[11]; /* dword 1*/ | ||
338 | u8 rsvd2; /* dword 1*/ | ||
339 | u8 pd[10]; /* dword 1*/ | ||
340 | u8 eqid[8]; /* dword 1*/ | ||
341 | u8 stalled; /* dword 1*/ | ||
342 | u8 armed; /* dword 1*/ | ||
343 | u8 rsvd3[4]; /* dword 2*/ | ||
344 | u8 func[8]; /* dword 2*/ | ||
345 | u8 rsvd4[20]; /* dword 2*/ | ||
346 | u8 rsvd5[32]; /* dword 3*/ | ||
347 | } __packed; | ||
348 | |||
349 | struct amap_cq_context_lancer { | ||
350 | u8 rsvd0[12]; /* dword 0*/ | ||
351 | u8 coalescwm[2]; /* dword 0*/ | ||
352 | u8 nodelay; /* dword 0*/ | ||
353 | u8 rsvd1[12]; /* dword 0*/ | ||
354 | u8 count[2]; /* dword 0*/ | ||
355 | u8 valid; /* dword 0*/ | ||
356 | u8 rsvd2; /* dword 0*/ | ||
357 | u8 eventable; /* dword 0*/ | ||
358 | u8 eqid[16]; /* dword 1*/ | ||
359 | u8 rsvd3[15]; /* dword 1*/ | ||
360 | u8 armed; /* dword 1*/ | ||
361 | u8 rsvd4[32]; /* dword 2*/ | ||
362 | u8 rsvd5[32]; /* dword 3*/ | ||
363 | } __packed; | ||
364 | |||
365 | struct be_cmd_req_cq_create { | ||
366 | struct be_cmd_req_hdr hdr; | ||
367 | u16 num_pages; | ||
368 | u8 page_size; | ||
369 | u8 rsvd0; | ||
370 | u8 context[sizeof(struct amap_cq_context_be) / 8]; | ||
371 | struct phys_addr pages[8]; | ||
372 | } __packed; | ||
373 | |||
374 | |||
375 | struct be_cmd_resp_cq_create { | ||
376 | struct be_cmd_resp_hdr hdr; | ||
377 | u16 cq_id; | ||
378 | u16 rsvd0; | ||
379 | } __packed; | ||
380 | |||
381 | struct be_cmd_req_get_fat { | ||
382 | struct be_cmd_req_hdr hdr; | ||
383 | u32 fat_operation; | ||
384 | u32 read_log_offset; | ||
385 | u32 read_log_length; | ||
386 | u32 data_buffer_size; | ||
387 | u32 data_buffer[1]; | ||
388 | } __packed; | ||
389 | |||
390 | struct be_cmd_resp_get_fat { | ||
391 | struct be_cmd_resp_hdr hdr; | ||
392 | u32 log_size; | ||
393 | u32 read_log_length; | ||
394 | u32 rsvd[2]; | ||
395 | u32 data_buffer[1]; | ||
396 | } __packed; | ||
397 | |||
398 | |||
399 | /******************** Create MCCQ ***************************/ | ||
400 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
401 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
402 | struct amap_mcc_context_be { | ||
403 | u8 con_index[14]; | ||
404 | u8 rsvd0[2]; | ||
405 | u8 ring_size[4]; | ||
406 | u8 fetch_wrb; | ||
407 | u8 fetch_r2t; | ||
408 | u8 cq_id[10]; | ||
409 | u8 prod_index[14]; | ||
410 | u8 fid[8]; | ||
411 | u8 pdid[9]; | ||
412 | u8 valid; | ||
413 | u8 rsvd1[32]; | ||
414 | u8 rsvd2[32]; | ||
415 | } __packed; | ||
416 | |||
417 | struct amap_mcc_context_lancer { | ||
418 | u8 async_cq_id[16]; | ||
419 | u8 ring_size[4]; | ||
420 | u8 rsvd0[12]; | ||
421 | u8 rsvd1[31]; | ||
422 | u8 valid; | ||
423 | u8 async_cq_valid[1]; | ||
424 | u8 rsvd2[31]; | ||
425 | u8 rsvd3[32]; | ||
426 | } __packed; | ||
427 | |||
428 | struct be_cmd_req_mcc_create { | ||
429 | struct be_cmd_req_hdr hdr; | ||
430 | u16 num_pages; | ||
431 | u16 cq_id; | ||
432 | u8 context[sizeof(struct amap_mcc_context_be) / 8]; | ||
433 | struct phys_addr pages[8]; | ||
434 | } __packed; | ||
435 | |||
436 | struct be_cmd_req_mcc_ext_create { | ||
437 | struct be_cmd_req_hdr hdr; | ||
438 | u16 num_pages; | ||
439 | u16 cq_id; | ||
440 | u32 async_event_bitmap[1]; | ||
441 | u8 context[sizeof(struct amap_mcc_context_be) / 8]; | ||
442 | struct phys_addr pages[8]; | ||
443 | } __packed; | ||
444 | |||
445 | struct be_cmd_resp_mcc_create { | ||
446 | struct be_cmd_resp_hdr hdr; | ||
447 | u16 id; | ||
448 | u16 rsvd0; | ||
449 | } __packed; | ||
450 | |||
451 | /******************** Create TxQ ***************************/ | ||
452 | #define BE_ETH_TX_RING_TYPE_STANDARD 2 | ||
453 | #define BE_ULP1_NUM 1 | ||
454 | |||
455 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
456 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
457 | struct amap_tx_context { | ||
458 | u8 if_id[16]; /* dword 0 */ | ||
459 | u8 tx_ring_size[4]; /* dword 0 */ | ||
460 | u8 rsvd1[26]; /* dword 0 */ | ||
461 | u8 pci_func_id[8]; /* dword 1 */ | ||
462 | u8 rsvd2[9]; /* dword 1 */ | ||
463 | u8 ctx_valid; /* dword 1 */ | ||
464 | u8 cq_id_send[16]; /* dword 2 */ | ||
465 | u8 rsvd3[16]; /* dword 2 */ | ||
466 | u8 rsvd4[32]; /* dword 3 */ | ||
467 | u8 rsvd5[32]; /* dword 4 */ | ||
468 | u8 rsvd6[32]; /* dword 5 */ | ||
469 | u8 rsvd7[32]; /* dword 6 */ | ||
470 | u8 rsvd8[32]; /* dword 7 */ | ||
471 | u8 rsvd9[32]; /* dword 8 */ | ||
472 | u8 rsvd10[32]; /* dword 9 */ | ||
473 | u8 rsvd11[32]; /* dword 10 */ | ||
474 | u8 rsvd12[32]; /* dword 11 */ | ||
475 | u8 rsvd13[32]; /* dword 12 */ | ||
476 | u8 rsvd14[32]; /* dword 13 */ | ||
477 | u8 rsvd15[32]; /* dword 14 */ | ||
478 | u8 rsvd16[32]; /* dword 15 */ | ||
479 | } __packed; | ||
480 | |||
481 | struct be_cmd_req_eth_tx_create { | ||
482 | struct be_cmd_req_hdr hdr; | ||
483 | u8 num_pages; | ||
484 | u8 ulp_num; | ||
485 | u8 type; | ||
486 | u8 bound_port; | ||
487 | u8 context[sizeof(struct amap_tx_context) / 8]; | ||
488 | struct phys_addr pages[8]; | ||
489 | } __packed; | ||
490 | |||
491 | struct be_cmd_resp_eth_tx_create { | ||
492 | struct be_cmd_resp_hdr hdr; | ||
493 | u16 cid; | ||
494 | u16 rsvd0; | ||
495 | } __packed; | ||
496 | |||
497 | /******************** Create RxQ ***************************/ | ||
498 | struct be_cmd_req_eth_rx_create { | ||
499 | struct be_cmd_req_hdr hdr; | ||
500 | u16 cq_id; | ||
501 | u8 frag_size; | ||
502 | u8 num_pages; | ||
503 | struct phys_addr pages[2]; | ||
504 | u32 interface_id; | ||
505 | u16 max_frame_size; | ||
506 | u16 rsvd0; | ||
507 | u32 rss_queue; | ||
508 | } __packed; | ||
509 | |||
510 | struct be_cmd_resp_eth_rx_create { | ||
511 | struct be_cmd_resp_hdr hdr; | ||
512 | u16 id; | ||
513 | u8 rss_id; | ||
514 | u8 rsvd0; | ||
515 | } __packed; | ||
516 | |||
517 | /******************** Q Destroy ***************************/ | ||
518 | /* Type of Queue to be destroyed */ | ||
519 | enum { | ||
520 | QTYPE_EQ = 1, | ||
521 | QTYPE_CQ, | ||
522 | QTYPE_TXQ, | ||
523 | QTYPE_RXQ, | ||
524 | QTYPE_MCCQ | ||
525 | }; | ||
526 | |||
527 | struct be_cmd_req_q_destroy { | ||
528 | struct be_cmd_req_hdr hdr; | ||
529 | u16 id; | ||
530 | u16 bypass_flush; /* valid only for rx q destroy */ | ||
531 | } __packed; | ||
532 | |||
533 | /************ I/f Create (it's actually I/f Config Create)**********/ | ||
534 | |||
535 | /* Capability flags for the i/f */ | ||
536 | enum be_if_flags { | ||
537 | BE_IF_FLAGS_RSS = 0x4, | ||
538 | BE_IF_FLAGS_PROMISCUOUS = 0x8, | ||
539 | BE_IF_FLAGS_BROADCAST = 0x10, | ||
540 | BE_IF_FLAGS_UNTAGGED = 0x20, | ||
541 | BE_IF_FLAGS_ULP = 0x40, | ||
542 | BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, | ||
543 | BE_IF_FLAGS_VLAN = 0x100, | ||
544 | BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, | ||
545 | BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, | ||
546 | BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, | ||
547 | BE_IF_FLAGS_MULTICAST = 0x1000 | ||
548 | }; | ||
549 | |||
550 | /* An RX interface is an object with one or more MAC addresses and | ||
551 | * filtering capabilities. */ | ||
552 | struct be_cmd_req_if_create { | ||
553 | struct be_cmd_req_hdr hdr; | ||
554 | u32 version; /* ignore currently */ | ||
555 | u32 capability_flags; | ||
556 | u32 enable_flags; | ||
557 | u8 mac_addr[ETH_ALEN]; | ||
558 | u8 rsvd0; | ||
559 | u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ | ||
560 | u32 vlan_tag; /* not used currently */ | ||
561 | } __packed; | ||
562 | |||
563 | struct be_cmd_resp_if_create { | ||
564 | struct be_cmd_resp_hdr hdr; | ||
565 | u32 interface_id; | ||
566 | u32 pmac_id; | ||
567 | }; | ||
568 | |||
569 | /****** I/f Destroy(it's actually I/f Config Destroy )**********/ | ||
570 | struct be_cmd_req_if_destroy { | ||
571 | struct be_cmd_req_hdr hdr; | ||
572 | u32 interface_id; | ||
573 | }; | ||
574 | |||
575 | /*************** HW Stats Get **********************************/ | ||
576 | struct be_port_rxf_stats_v0 { | ||
577 | u32 rx_bytes_lsd; /* dword 0*/ | ||
578 | u32 rx_bytes_msd; /* dword 1*/ | ||
579 | u32 rx_total_frames; /* dword 2*/ | ||
580 | u32 rx_unicast_frames; /* dword 3*/ | ||
581 | u32 rx_multicast_frames; /* dword 4*/ | ||
582 | u32 rx_broadcast_frames; /* dword 5*/ | ||
583 | u32 rx_crc_errors; /* dword 6*/ | ||
584 | u32 rx_alignment_symbol_errors; /* dword 7*/ | ||
585 | u32 rx_pause_frames; /* dword 8*/ | ||
586 | u32 rx_control_frames; /* dword 9*/ | ||
587 | u32 rx_in_range_errors; /* dword 10*/ | ||
588 | u32 rx_out_range_errors; /* dword 11*/ | ||
589 | u32 rx_frame_too_long; /* dword 12*/ | ||
590 | u32 rx_address_match_errors; /* dword 13*/ | ||
591 | u32 rx_vlan_mismatch; /* dword 14*/ | ||
592 | u32 rx_dropped_too_small; /* dword 15*/ | ||
593 | u32 rx_dropped_too_short; /* dword 16*/ | ||
594 | u32 rx_dropped_header_too_small; /* dword 17*/ | ||
595 | u32 rx_dropped_tcp_length; /* dword 18*/ | ||
596 | u32 rx_dropped_runt; /* dword 19*/ | ||
597 | u32 rx_64_byte_packets; /* dword 20*/ | ||
598 | u32 rx_65_127_byte_packets; /* dword 21*/ | ||
599 | u32 rx_128_256_byte_packets; /* dword 22*/ | ||
600 | u32 rx_256_511_byte_packets; /* dword 23*/ | ||
601 | u32 rx_512_1023_byte_packets; /* dword 24*/ | ||
602 | u32 rx_1024_1518_byte_packets; /* dword 25*/ | ||
603 | u32 rx_1519_2047_byte_packets; /* dword 26*/ | ||
604 | u32 rx_2048_4095_byte_packets; /* dword 27*/ | ||
605 | u32 rx_4096_8191_byte_packets; /* dword 28*/ | ||
606 | u32 rx_8192_9216_byte_packets; /* dword 29*/ | ||
607 | u32 rx_ip_checksum_errs; /* dword 30*/ | ||
608 | u32 rx_tcp_checksum_errs; /* dword 31*/ | ||
609 | u32 rx_udp_checksum_errs; /* dword 32*/ | ||
610 | u32 rx_non_rss_packets; /* dword 33*/ | ||
611 | u32 rx_ipv4_packets; /* dword 34*/ | ||
612 | u32 rx_ipv6_packets; /* dword 35*/ | ||
613 | u32 rx_ipv4_bytes_lsd; /* dword 36*/ | ||
614 | u32 rx_ipv4_bytes_msd; /* dword 37*/ | ||
615 | u32 rx_ipv6_bytes_lsd; /* dword 38*/ | ||
616 | u32 rx_ipv6_bytes_msd; /* dword 39*/ | ||
617 | u32 rx_chute1_packets; /* dword 40*/ | ||
618 | u32 rx_chute2_packets; /* dword 41*/ | ||
619 | u32 rx_chute3_packets; /* dword 42*/ | ||
620 | u32 rx_management_packets; /* dword 43*/ | ||
621 | u32 rx_switched_unicast_packets; /* dword 44*/ | ||
622 | u32 rx_switched_multicast_packets; /* dword 45*/ | ||
623 | u32 rx_switched_broadcast_packets; /* dword 46*/ | ||
624 | u32 tx_bytes_lsd; /* dword 47*/ | ||
625 | u32 tx_bytes_msd; /* dword 48*/ | ||
626 | u32 tx_unicastframes; /* dword 49*/ | ||
627 | u32 tx_multicastframes; /* dword 50*/ | ||
628 | u32 tx_broadcastframes; /* dword 51*/ | ||
629 | u32 tx_pauseframes; /* dword 52*/ | ||
630 | u32 tx_controlframes; /* dword 53*/ | ||
631 | u32 tx_64_byte_packets; /* dword 54*/ | ||
632 | u32 tx_65_127_byte_packets; /* dword 55*/ | ||
633 | u32 tx_128_256_byte_packets; /* dword 56*/ | ||
634 | u32 tx_256_511_byte_packets; /* dword 57*/ | ||
635 | u32 tx_512_1023_byte_packets; /* dword 58*/ | ||
636 | u32 tx_1024_1518_byte_packets; /* dword 59*/ | ||
637 | u32 tx_1519_2047_byte_packets; /* dword 60*/ | ||
638 | u32 tx_2048_4095_byte_packets; /* dword 61*/ | ||
639 | u32 tx_4096_8191_byte_packets; /* dword 62*/ | ||
640 | u32 tx_8192_9216_byte_packets; /* dword 63*/ | ||
641 | u32 rx_fifo_overflow; /* dword 64*/ | ||
642 | u32 rx_input_fifo_overflow; /* dword 65*/ | ||
643 | }; | ||
644 | |||
645 | struct be_rxf_stats_v0 { | ||
646 | struct be_port_rxf_stats_v0 port[2]; | ||
647 | u32 rx_drops_no_pbuf; /* dword 132*/ | ||
648 | u32 rx_drops_no_txpb; /* dword 133*/ | ||
649 | u32 rx_drops_no_erx_descr; /* dword 134*/ | ||
650 | u32 rx_drops_no_tpre_descr; /* dword 135*/ | ||
651 | u32 management_rx_port_packets; /* dword 136*/ | ||
652 | u32 management_rx_port_bytes; /* dword 137*/ | ||
653 | u32 management_rx_port_pause_frames; /* dword 138*/ | ||
654 | u32 management_rx_port_errors; /* dword 139*/ | ||
655 | u32 management_tx_port_packets; /* dword 140*/ | ||
656 | u32 management_tx_port_bytes; /* dword 141*/ | ||
657 | u32 management_tx_port_pause; /* dword 142*/ | ||
658 | u32 management_rx_port_rxfifo_overflow; /* dword 143*/ | ||
659 | u32 rx_drops_too_many_frags; /* dword 144*/ | ||
660 | u32 rx_drops_invalid_ring; /* dword 145*/ | ||
661 | u32 forwarded_packets; /* dword 146*/ | ||
662 | u32 rx_drops_mtu; /* dword 147*/ | ||
663 | u32 rsvd0[7]; | ||
664 | u32 port0_jabber_events; | ||
665 | u32 port1_jabber_events; | ||
666 | u32 rsvd1[6]; | ||
667 | }; | ||
668 | |||
669 | struct be_erx_stats_v0 { | ||
670 | u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ | ||
671 | u32 rsvd[4]; | ||
672 | }; | ||
673 | |||
674 | struct be_pmem_stats { | ||
675 | u32 eth_red_drops; | ||
676 | u32 rsvd[5]; | ||
677 | }; | ||
678 | |||
679 | struct be_hw_stats_v0 { | ||
680 | struct be_rxf_stats_v0 rxf; | ||
681 | u32 rsvd[48]; | ||
682 | struct be_erx_stats_v0 erx; | ||
683 | struct be_pmem_stats pmem; | ||
684 | }; | ||
685 | |||
686 | struct be_cmd_req_get_stats_v0 { | ||
687 | struct be_cmd_req_hdr hdr; | ||
688 | u8 rsvd[sizeof(struct be_hw_stats_v0)]; | ||
689 | }; | ||
690 | |||
691 | struct be_cmd_resp_get_stats_v0 { | ||
692 | struct be_cmd_resp_hdr hdr; | ||
693 | struct be_hw_stats_v0 hw_stats; | ||
694 | }; | ||
695 | |||
696 | #define make_64bit_val(hi_32, lo_32) (((u64)hi_32<<32) | lo_32) | ||
697 | struct lancer_cmd_pport_stats { | ||
698 | u32 tx_packets_lo; | ||
699 | u32 tx_packets_hi; | ||
700 | u32 tx_unicast_packets_lo; | ||
701 | u32 tx_unicast_packets_hi; | ||
702 | u32 tx_multicast_packets_lo; | ||
703 | u32 tx_multicast_packets_hi; | ||
704 | u32 tx_broadcast_packets_lo; | ||
705 | u32 tx_broadcast_packets_hi; | ||
706 | u32 tx_bytes_lo; | ||
707 | u32 tx_bytes_hi; | ||
708 | u32 tx_unicast_bytes_lo; | ||
709 | u32 tx_unicast_bytes_hi; | ||
710 | u32 tx_multicast_bytes_lo; | ||
711 | u32 tx_multicast_bytes_hi; | ||
712 | u32 tx_broadcast_bytes_lo; | ||
713 | u32 tx_broadcast_bytes_hi; | ||
714 | u32 tx_discards_lo; | ||
715 | u32 tx_discards_hi; | ||
716 | u32 tx_errors_lo; | ||
717 | u32 tx_errors_hi; | ||
718 | u32 tx_pause_frames_lo; | ||
719 | u32 tx_pause_frames_hi; | ||
720 | u32 tx_pause_on_frames_lo; | ||
721 | u32 tx_pause_on_frames_hi; | ||
722 | u32 tx_pause_off_frames_lo; | ||
723 | u32 tx_pause_off_frames_hi; | ||
724 | u32 tx_internal_mac_errors_lo; | ||
725 | u32 tx_internal_mac_errors_hi; | ||
726 | u32 tx_control_frames_lo; | ||
727 | u32 tx_control_frames_hi; | ||
728 | u32 tx_packets_64_bytes_lo; | ||
729 | u32 tx_packets_64_bytes_hi; | ||
730 | u32 tx_packets_65_to_127_bytes_lo; | ||
731 | u32 tx_packets_65_to_127_bytes_hi; | ||
732 | u32 tx_packets_128_to_255_bytes_lo; | ||
733 | u32 tx_packets_128_to_255_bytes_hi; | ||
734 | u32 tx_packets_256_to_511_bytes_lo; | ||
735 | u32 tx_packets_256_to_511_bytes_hi; | ||
736 | u32 tx_packets_512_to_1023_bytes_lo; | ||
737 | u32 tx_packets_512_to_1023_bytes_hi; | ||
738 | u32 tx_packets_1024_to_1518_bytes_lo; | ||
739 | u32 tx_packets_1024_to_1518_bytes_hi; | ||
740 | u32 tx_packets_1519_to_2047_bytes_lo; | ||
741 | u32 tx_packets_1519_to_2047_bytes_hi; | ||
742 | u32 tx_packets_2048_to_4095_bytes_lo; | ||
743 | u32 tx_packets_2048_to_4095_bytes_hi; | ||
744 | u32 tx_packets_4096_to_8191_bytes_lo; | ||
745 | u32 tx_packets_4096_to_8191_bytes_hi; | ||
746 | u32 tx_packets_8192_to_9216_bytes_lo; | ||
747 | u32 tx_packets_8192_to_9216_bytes_hi; | ||
748 | u32 tx_lso_packets_lo; | ||
749 | u32 tx_lso_packets_hi; | ||
750 | u32 rx_packets_lo; | ||
751 | u32 rx_packets_hi; | ||
752 | u32 rx_unicast_packets_lo; | ||
753 | u32 rx_unicast_packets_hi; | ||
754 | u32 rx_multicast_packets_lo; | ||
755 | u32 rx_multicast_packets_hi; | ||
756 | u32 rx_broadcast_packets_lo; | ||
757 | u32 rx_broadcast_packets_hi; | ||
758 | u32 rx_bytes_lo; | ||
759 | u32 rx_bytes_hi; | ||
760 | u32 rx_unicast_bytes_lo; | ||
761 | u32 rx_unicast_bytes_hi; | ||
762 | u32 rx_multicast_bytes_lo; | ||
763 | u32 rx_multicast_bytes_hi; | ||
764 | u32 rx_broadcast_bytes_lo; | ||
765 | u32 rx_broadcast_bytes_hi; | ||
766 | u32 rx_unknown_protos; | ||
767 | u32 rsvd_69; /* Word 69 is reserved */ | ||
768 | u32 rx_discards_lo; | ||
769 | u32 rx_discards_hi; | ||
770 | u32 rx_errors_lo; | ||
771 | u32 rx_errors_hi; | ||
772 | u32 rx_crc_errors_lo; | ||
773 | u32 rx_crc_errors_hi; | ||
774 | u32 rx_alignment_errors_lo; | ||
775 | u32 rx_alignment_errors_hi; | ||
776 | u32 rx_symbol_errors_lo; | ||
777 | u32 rx_symbol_errors_hi; | ||
778 | u32 rx_pause_frames_lo; | ||
779 | u32 rx_pause_frames_hi; | ||
780 | u32 rx_pause_on_frames_lo; | ||
781 | u32 rx_pause_on_frames_hi; | ||
782 | u32 rx_pause_off_frames_lo; | ||
783 | u32 rx_pause_off_frames_hi; | ||
784 | u32 rx_frames_too_long_lo; | ||
785 | u32 rx_frames_too_long_hi; | ||
786 | u32 rx_internal_mac_errors_lo; | ||
787 | u32 rx_internal_mac_errors_hi; | ||
788 | u32 rx_undersize_packets; | ||
789 | u32 rx_oversize_packets; | ||
790 | u32 rx_fragment_packets; | ||
791 | u32 rx_jabbers; | ||
792 | u32 rx_control_frames_lo; | ||
793 | u32 rx_control_frames_hi; | ||
794 | u32 rx_control_frames_unknown_opcode_lo; | ||
795 | u32 rx_control_frames_unknown_opcode_hi; | ||
796 | u32 rx_in_range_errors; | ||
797 | u32 rx_out_of_range_errors; | ||
798 | u32 rx_address_match_errors; | ||
799 | u32 rx_vlan_mismatch_errors; | ||
800 | u32 rx_dropped_too_small; | ||
801 | u32 rx_dropped_too_short; | ||
802 | u32 rx_dropped_header_too_small; | ||
803 | u32 rx_dropped_invalid_tcp_length; | ||
804 | u32 rx_dropped_runt; | ||
805 | u32 rx_ip_checksum_errors; | ||
806 | u32 rx_tcp_checksum_errors; | ||
807 | u32 rx_udp_checksum_errors; | ||
808 | u32 rx_non_rss_packets; | ||
809 | u32 rsvd_111; | ||
810 | u32 rx_ipv4_packets_lo; | ||
811 | u32 rx_ipv4_packets_hi; | ||
812 | u32 rx_ipv6_packets_lo; | ||
813 | u32 rx_ipv6_packets_hi; | ||
814 | u32 rx_ipv4_bytes_lo; | ||
815 | u32 rx_ipv4_bytes_hi; | ||
816 | u32 rx_ipv6_bytes_lo; | ||
817 | u32 rx_ipv6_bytes_hi; | ||
818 | u32 rx_nic_packets_lo; | ||
819 | u32 rx_nic_packets_hi; | ||
820 | u32 rx_tcp_packets_lo; | ||
821 | u32 rx_tcp_packets_hi; | ||
822 | u32 rx_iscsi_packets_lo; | ||
823 | u32 rx_iscsi_packets_hi; | ||
824 | u32 rx_management_packets_lo; | ||
825 | u32 rx_management_packets_hi; | ||
826 | u32 rx_switched_unicast_packets_lo; | ||
827 | u32 rx_switched_unicast_packets_hi; | ||
828 | u32 rx_switched_multicast_packets_lo; | ||
829 | u32 rx_switched_multicast_packets_hi; | ||
830 | u32 rx_switched_broadcast_packets_lo; | ||
831 | u32 rx_switched_broadcast_packets_hi; | ||
832 | u32 num_forwards_lo; | ||
833 | u32 num_forwards_hi; | ||
834 | u32 rx_fifo_overflow; | ||
835 | u32 rx_input_fifo_overflow; | ||
836 | u32 rx_drops_too_many_frags_lo; | ||
837 | u32 rx_drops_too_many_frags_hi; | ||
838 | u32 rx_drops_invalid_queue; | ||
839 | u32 rsvd_141; | ||
840 | u32 rx_drops_mtu_lo; | ||
841 | u32 rx_drops_mtu_hi; | ||
842 | u32 rx_packets_64_bytes_lo; | ||
843 | u32 rx_packets_64_bytes_hi; | ||
844 | u32 rx_packets_65_to_127_bytes_lo; | ||
845 | u32 rx_packets_65_to_127_bytes_hi; | ||
846 | u32 rx_packets_128_to_255_bytes_lo; | ||
847 | u32 rx_packets_128_to_255_bytes_hi; | ||
848 | u32 rx_packets_256_to_511_bytes_lo; | ||
849 | u32 rx_packets_256_to_511_bytes_hi; | ||
850 | u32 rx_packets_512_to_1023_bytes_lo; | ||
851 | u32 rx_packets_512_to_1023_bytes_hi; | ||
852 | u32 rx_packets_1024_to_1518_bytes_lo; | ||
853 | u32 rx_packets_1024_to_1518_bytes_hi; | ||
854 | u32 rx_packets_1519_to_2047_bytes_lo; | ||
855 | u32 rx_packets_1519_to_2047_bytes_hi; | ||
856 | u32 rx_packets_2048_to_4095_bytes_lo; | ||
857 | u32 rx_packets_2048_to_4095_bytes_hi; | ||
858 | u32 rx_packets_4096_to_8191_bytes_lo; | ||
859 | u32 rx_packets_4096_to_8191_bytes_hi; | ||
860 | u32 rx_packets_8192_to_9216_bytes_lo; | ||
861 | u32 rx_packets_8192_to_9216_bytes_hi; | ||
862 | }; | ||
863 | |||
864 | struct pport_stats_params { | ||
865 | u16 pport_num; | ||
866 | u8 rsvd; | ||
867 | u8 reset_stats; | ||
868 | }; | ||
869 | |||
870 | struct lancer_cmd_req_pport_stats { | ||
871 | struct be_cmd_req_hdr hdr; | ||
872 | union { | ||
873 | struct pport_stats_params params; | ||
874 | u8 rsvd[sizeof(struct lancer_cmd_pport_stats)]; | ||
875 | } cmd_params; | ||
876 | }; | ||
877 | |||
878 | struct lancer_cmd_resp_pport_stats { | ||
879 | struct be_cmd_resp_hdr hdr; | ||
880 | struct lancer_cmd_pport_stats pport_stats; | ||
881 | }; | ||
882 | |||
883 | static inline struct lancer_cmd_pport_stats* | ||
884 | pport_stats_from_cmd(struct be_adapter *adapter) | ||
885 | { | ||
886 | struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; | ||
887 | return &cmd->pport_stats; | ||
888 | } | ||
889 | |||
890 | struct be_cmd_req_get_cntl_addnl_attribs { | ||
891 | struct be_cmd_req_hdr hdr; | ||
892 | u8 rsvd[8]; | ||
893 | }; | ||
894 | |||
895 | struct be_cmd_resp_get_cntl_addnl_attribs { | ||
896 | struct be_cmd_resp_hdr hdr; | ||
897 | u16 ipl_file_number; | ||
898 | u8 ipl_file_version; | ||
899 | u8 rsvd0; | ||
900 | u8 on_die_temperature; /* in degrees centigrade*/ | ||
901 | u8 rsvd1[3]; | ||
902 | }; | ||
903 | |||
904 | struct be_cmd_req_vlan_config { | ||
905 | struct be_cmd_req_hdr hdr; | ||
906 | u8 interface_id; | ||
907 | u8 promiscuous; | ||
908 | u8 untagged; | ||
909 | u8 num_vlan; | ||
910 | u16 normal_vlan[64]; | ||
911 | } __packed; | ||
912 | |||
913 | /******************** Multicast MAC Config *******************/ | ||
914 | #define BE_MAX_MC 64 /* set mcast promisc if > 64 */ | ||
915 | struct macaddr { | ||
916 | u8 byte[ETH_ALEN]; | ||
917 | }; | ||
918 | |||
919 | struct be_cmd_req_mcast_mac_config { | ||
920 | struct be_cmd_req_hdr hdr; | ||
921 | u16 num_mac; | ||
922 | u8 promiscuous; | ||
923 | u8 interface_id; | ||
924 | struct macaddr mac[BE_MAX_MC]; | ||
925 | } __packed; | ||
926 | |||
927 | /******************* RX FILTER ******************************/ | ||
928 | struct be_cmd_req_rx_filter { | ||
929 | struct be_cmd_req_hdr hdr; | ||
930 | u32 global_flags_mask; | ||
931 | u32 global_flags; | ||
932 | u32 if_flags_mask; | ||
933 | u32 if_flags; | ||
934 | u32 if_id; | ||
935 | u32 multicast_num; | ||
936 | struct macaddr mac[BE_MAX_MC]; | ||
937 | }; | ||
938 | |||
939 | |||
940 | /******************** Link Status Query *******************/ | ||
941 | struct be_cmd_req_link_status { | ||
942 | struct be_cmd_req_hdr hdr; | ||
943 | u32 rsvd; | ||
944 | }; | ||
945 | |||
946 | enum { | ||
947 | PHY_LINK_DUPLEX_NONE = 0x0, | ||
948 | PHY_LINK_DUPLEX_HALF = 0x1, | ||
949 | PHY_LINK_DUPLEX_FULL = 0x2 | ||
950 | }; | ||
951 | |||
952 | enum { | ||
953 | PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ | ||
954 | PHY_LINK_SPEED_10MBPS = 0x1, | ||
955 | PHY_LINK_SPEED_100MBPS = 0x2, | ||
956 | PHY_LINK_SPEED_1GBPS = 0x3, | ||
957 | PHY_LINK_SPEED_10GBPS = 0x4 | ||
958 | }; | ||
959 | |||
960 | struct be_cmd_resp_link_status { | ||
961 | struct be_cmd_resp_hdr hdr; | ||
962 | u8 physical_port; | ||
963 | u8 mac_duplex; | ||
964 | u8 mac_speed; | ||
965 | u8 mac_fault; | ||
966 | u8 mgmt_mac_duplex; | ||
967 | u8 mgmt_mac_speed; | ||
968 | u16 link_speed; | ||
969 | u32 rsvd0; | ||
970 | } __packed; | ||
971 | |||
972 | /******************** Port Identification ***************************/ | ||
973 | /* Identifies the type of port attached to NIC */ | ||
974 | struct be_cmd_req_port_type { | ||
975 | struct be_cmd_req_hdr hdr; | ||
976 | u32 page_num; | ||
977 | u32 port; | ||
978 | }; | ||
979 | |||
980 | enum { | ||
981 | TR_PAGE_A0 = 0xa0, | ||
982 | TR_PAGE_A2 = 0xa2 | ||
983 | }; | ||
984 | |||
985 | struct be_cmd_resp_port_type { | ||
986 | struct be_cmd_resp_hdr hdr; | ||
987 | u32 page_num; | ||
988 | u32 port; | ||
989 | struct data { | ||
990 | u8 identifier; | ||
991 | u8 identifier_ext; | ||
992 | u8 connector; | ||
993 | u8 transceiver[8]; | ||
994 | u8 rsvd0[3]; | ||
995 | u8 length_km; | ||
996 | u8 length_hm; | ||
997 | u8 length_om1; | ||
998 | u8 length_om2; | ||
999 | u8 length_cu; | ||
1000 | u8 length_cu_m; | ||
1001 | u8 vendor_name[16]; | ||
1002 | u8 rsvd; | ||
1003 | u8 vendor_oui[3]; | ||
1004 | u8 vendor_pn[16]; | ||
1005 | u8 vendor_rev[4]; | ||
1006 | } data; | ||
1007 | }; | ||
1008 | |||
1009 | /******************** Get FW Version *******************/ | ||
1010 | struct be_cmd_req_get_fw_version { | ||
1011 | struct be_cmd_req_hdr hdr; | ||
1012 | u8 rsvd0[FW_VER_LEN]; | ||
1013 | u8 rsvd1[FW_VER_LEN]; | ||
1014 | } __packed; | ||
1015 | |||
1016 | struct be_cmd_resp_get_fw_version { | ||
1017 | struct be_cmd_resp_hdr hdr; | ||
1018 | u8 firmware_version_string[FW_VER_LEN]; | ||
1019 | u8 fw_on_flash_version_string[FW_VER_LEN]; | ||
1020 | } __packed; | ||
1021 | |||
1022 | /******************** Set Flow Contrl *******************/ | ||
1023 | struct be_cmd_req_set_flow_control { | ||
1024 | struct be_cmd_req_hdr hdr; | ||
1025 | u16 tx_flow_control; | ||
1026 | u16 rx_flow_control; | ||
1027 | } __packed; | ||
1028 | |||
1029 | /******************** Get Flow Contrl *******************/ | ||
1030 | struct be_cmd_req_get_flow_control { | ||
1031 | struct be_cmd_req_hdr hdr; | ||
1032 | u32 rsvd; | ||
1033 | }; | ||
1034 | |||
1035 | struct be_cmd_resp_get_flow_control { | ||
1036 | struct be_cmd_resp_hdr hdr; | ||
1037 | u16 tx_flow_control; | ||
1038 | u16 rx_flow_control; | ||
1039 | } __packed; | ||
1040 | |||
1041 | /******************** Modify EQ Delay *******************/ | ||
1042 | struct be_cmd_req_modify_eq_delay { | ||
1043 | struct be_cmd_req_hdr hdr; | ||
1044 | u32 num_eq; | ||
1045 | struct { | ||
1046 | u32 eq_id; | ||
1047 | u32 phase; | ||
1048 | u32 delay_multiplier; | ||
1049 | } delay[8]; | ||
1050 | } __packed; | ||
1051 | |||
1052 | struct be_cmd_resp_modify_eq_delay { | ||
1053 | struct be_cmd_resp_hdr hdr; | ||
1054 | u32 rsvd0; | ||
1055 | } __packed; | ||
1056 | |||
1057 | /******************** Get FW Config *******************/ | ||
1058 | #define BE_FUNCTION_CAPS_RSS 0x2 | ||
1059 | struct be_cmd_req_query_fw_cfg { | ||
1060 | struct be_cmd_req_hdr hdr; | ||
1061 | u32 rsvd[31]; | ||
1062 | }; | ||
1063 | |||
1064 | struct be_cmd_resp_query_fw_cfg { | ||
1065 | struct be_cmd_resp_hdr hdr; | ||
1066 | u32 be_config_number; | ||
1067 | u32 asic_revision; | ||
1068 | u32 phys_port; | ||
1069 | u32 function_mode; | ||
1070 | u32 rsvd[26]; | ||
1071 | u32 function_caps; | ||
1072 | }; | ||
1073 | |||
1074 | /******************** RSS Config *******************/ | ||
1075 | /* RSS types */ | ||
1076 | #define RSS_ENABLE_NONE 0x0 | ||
1077 | #define RSS_ENABLE_IPV4 0x1 | ||
1078 | #define RSS_ENABLE_TCP_IPV4 0x2 | ||
1079 | #define RSS_ENABLE_IPV6 0x4 | ||
1080 | #define RSS_ENABLE_TCP_IPV6 0x8 | ||
1081 | |||
1082 | struct be_cmd_req_rss_config { | ||
1083 | struct be_cmd_req_hdr hdr; | ||
1084 | u32 if_id; | ||
1085 | u16 enable_rss; | ||
1086 | u16 cpu_table_size_log2; | ||
1087 | u32 hash[10]; | ||
1088 | u8 cpu_table[128]; | ||
1089 | u8 flush; | ||
1090 | u8 rsvd0[3]; | ||
1091 | }; | ||
1092 | |||
1093 | /******************** Port Beacon ***************************/ | ||
1094 | |||
1095 | #define BEACON_STATE_ENABLED 0x1 | ||
1096 | #define BEACON_STATE_DISABLED 0x0 | ||
1097 | |||
1098 | struct be_cmd_req_enable_disable_beacon { | ||
1099 | struct be_cmd_req_hdr hdr; | ||
1100 | u8 port_num; | ||
1101 | u8 beacon_state; | ||
1102 | u8 beacon_duration; | ||
1103 | u8 status_duration; | ||
1104 | } __packed; | ||
1105 | |||
1106 | struct be_cmd_resp_enable_disable_beacon { | ||
1107 | struct be_cmd_resp_hdr resp_hdr; | ||
1108 | u32 rsvd0; | ||
1109 | } __packed; | ||
1110 | |||
1111 | struct be_cmd_req_get_beacon_state { | ||
1112 | struct be_cmd_req_hdr hdr; | ||
1113 | u8 port_num; | ||
1114 | u8 rsvd0; | ||
1115 | u16 rsvd1; | ||
1116 | } __packed; | ||
1117 | |||
1118 | struct be_cmd_resp_get_beacon_state { | ||
1119 | struct be_cmd_resp_hdr resp_hdr; | ||
1120 | u8 beacon_state; | ||
1121 | u8 rsvd0[3]; | ||
1122 | } __packed; | ||
1123 | |||
1124 | /****************** Firmware Flash ******************/ | ||
1125 | struct flashrom_params { | ||
1126 | u32 op_code; | ||
1127 | u32 op_type; | ||
1128 | u32 data_buf_size; | ||
1129 | u32 offset; | ||
1130 | u8 data_buf[4]; | ||
1131 | }; | ||
1132 | |||
1133 | struct be_cmd_write_flashrom { | ||
1134 | struct be_cmd_req_hdr hdr; | ||
1135 | struct flashrom_params params; | ||
1136 | }; | ||
1137 | |||
1138 | /**************** Lancer Firmware Flash ************/ | ||
1139 | struct amap_lancer_write_obj_context { | ||
1140 | u8 write_length[24]; | ||
1141 | u8 reserved1[7]; | ||
1142 | u8 eof; | ||
1143 | } __packed; | ||
1144 | |||
1145 | struct lancer_cmd_req_write_object { | ||
1146 | struct be_cmd_req_hdr hdr; | ||
1147 | u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; | ||
1148 | u32 write_offset; | ||
1149 | u8 object_name[104]; | ||
1150 | u32 descriptor_count; | ||
1151 | u32 buf_len; | ||
1152 | u32 addr_low; | ||
1153 | u32 addr_high; | ||
1154 | }; | ||
1155 | |||
1156 | struct lancer_cmd_resp_write_object { | ||
1157 | u8 opcode; | ||
1158 | u8 subsystem; | ||
1159 | u8 rsvd1[2]; | ||
1160 | u8 status; | ||
1161 | u8 additional_status; | ||
1162 | u8 rsvd2[2]; | ||
1163 | u32 resp_len; | ||
1164 | u32 actual_resp_len; | ||
1165 | u32 actual_write_len; | ||
1166 | }; | ||
1167 | |||
1168 | /************************ WOL *******************************/ | ||
1169 | struct be_cmd_req_acpi_wol_magic_config{ | ||
1170 | struct be_cmd_req_hdr hdr; | ||
1171 | u32 rsvd0[145]; | ||
1172 | u8 magic_mac[6]; | ||
1173 | u8 rsvd2[2]; | ||
1174 | } __packed; | ||
1175 | |||
1176 | /********************** LoopBack test *********************/ | ||
1177 | struct be_cmd_req_loopback_test { | ||
1178 | struct be_cmd_req_hdr hdr; | ||
1179 | u32 loopback_type; | ||
1180 | u32 num_pkts; | ||
1181 | u64 pattern; | ||
1182 | u32 src_port; | ||
1183 | u32 dest_port; | ||
1184 | u32 pkt_size; | ||
1185 | }; | ||
1186 | |||
1187 | struct be_cmd_resp_loopback_test { | ||
1188 | struct be_cmd_resp_hdr resp_hdr; | ||
1189 | u32 status; | ||
1190 | u32 num_txfer; | ||
1191 | u32 num_rx; | ||
1192 | u32 miscomp_off; | ||
1193 | u32 ticks_compl; | ||
1194 | }; | ||
1195 | |||
1196 | struct be_cmd_req_set_lmode { | ||
1197 | struct be_cmd_req_hdr hdr; | ||
1198 | u8 src_port; | ||
1199 | u8 dest_port; | ||
1200 | u8 loopback_type; | ||
1201 | u8 loopback_state; | ||
1202 | }; | ||
1203 | |||
1204 | struct be_cmd_resp_set_lmode { | ||
1205 | struct be_cmd_resp_hdr resp_hdr; | ||
1206 | u8 rsvd0[4]; | ||
1207 | }; | ||
1208 | |||
1209 | /********************** DDR DMA test *********************/ | ||
1210 | struct be_cmd_req_ddrdma_test { | ||
1211 | struct be_cmd_req_hdr hdr; | ||
1212 | u64 pattern; | ||
1213 | u32 byte_count; | ||
1214 | u32 rsvd0; | ||
1215 | u8 snd_buff[4096]; | ||
1216 | u8 rsvd1[4096]; | ||
1217 | }; | ||
1218 | |||
1219 | struct be_cmd_resp_ddrdma_test { | ||
1220 | struct be_cmd_resp_hdr hdr; | ||
1221 | u64 pattern; | ||
1222 | u32 byte_cnt; | ||
1223 | u32 snd_err; | ||
1224 | u8 rsvd0[4096]; | ||
1225 | u8 rcv_buff[4096]; | ||
1226 | }; | ||
1227 | |||
1228 | /*********************** SEEPROM Read ***********************/ | ||
1229 | |||
1230 | #define BE_READ_SEEPROM_LEN 1024 | ||
1231 | struct be_cmd_req_seeprom_read { | ||
1232 | struct be_cmd_req_hdr hdr; | ||
1233 | u8 rsvd0[BE_READ_SEEPROM_LEN]; | ||
1234 | }; | ||
1235 | |||
1236 | struct be_cmd_resp_seeprom_read { | ||
1237 | struct be_cmd_req_hdr hdr; | ||
1238 | u8 seeprom_data[BE_READ_SEEPROM_LEN]; | ||
1239 | }; | ||
1240 | |||
1241 | enum { | ||
1242 | PHY_TYPE_CX4_10GB = 0, | ||
1243 | PHY_TYPE_XFP_10GB, | ||
1244 | PHY_TYPE_SFP_1GB, | ||
1245 | PHY_TYPE_SFP_PLUS_10GB, | ||
1246 | PHY_TYPE_KR_10GB, | ||
1247 | PHY_TYPE_KX4_10GB, | ||
1248 | PHY_TYPE_BASET_10GB, | ||
1249 | PHY_TYPE_BASET_1GB, | ||
1250 | PHY_TYPE_DISABLED = 255 | ||
1251 | }; | ||
1252 | |||
1253 | struct be_cmd_req_get_phy_info { | ||
1254 | struct be_cmd_req_hdr hdr; | ||
1255 | u8 rsvd0[24]; | ||
1256 | }; | ||
1257 | struct be_cmd_resp_get_phy_info { | ||
1258 | struct be_cmd_req_hdr hdr; | ||
1259 | u16 phy_type; | ||
1260 | u16 interface_type; | ||
1261 | u32 misc_params; | ||
1262 | u32 future_use[4]; | ||
1263 | }; | ||
1264 | |||
1265 | /*********************** Set QOS ***********************/ | ||
1266 | |||
1267 | #define BE_QOS_BITS_NIC 1 | ||
1268 | |||
1269 | struct be_cmd_req_set_qos { | ||
1270 | struct be_cmd_req_hdr hdr; | ||
1271 | u32 valid_bits; | ||
1272 | u32 max_bps_nic; | ||
1273 | u32 rsvd[7]; | ||
1274 | }; | ||
1275 | |||
1276 | struct be_cmd_resp_set_qos { | ||
1277 | struct be_cmd_resp_hdr hdr; | ||
1278 | u32 rsvd; | ||
1279 | }; | ||
1280 | |||
1281 | /*********************** Controller Attributes ***********************/ | ||
1282 | struct be_cmd_req_cntl_attribs { | ||
1283 | struct be_cmd_req_hdr hdr; | ||
1284 | }; | ||
1285 | |||
1286 | struct be_cmd_resp_cntl_attribs { | ||
1287 | struct be_cmd_resp_hdr hdr; | ||
1288 | struct mgmt_controller_attrib attribs; | ||
1289 | }; | ||
1290 | |||
1291 | /*********************** Set driver function ***********************/ | ||
1292 | #define CAPABILITY_SW_TIMESTAMPS 2 | ||
1293 | #define CAPABILITY_BE3_NATIVE_ERX_API 4 | ||
1294 | |||
1295 | struct be_cmd_req_set_func_cap { | ||
1296 | struct be_cmd_req_hdr hdr; | ||
1297 | u32 valid_cap_flags; | ||
1298 | u32 cap_flags; | ||
1299 | u8 rsvd[212]; | ||
1300 | }; | ||
1301 | |||
1302 | struct be_cmd_resp_set_func_cap { | ||
1303 | struct be_cmd_resp_hdr hdr; | ||
1304 | u32 valid_cap_flags; | ||
1305 | u32 cap_flags; | ||
1306 | u8 rsvd[212]; | ||
1307 | }; | ||
1308 | |||
1309 | /*************** HW Stats Get v1 **********************************/ | ||
1310 | #define BE_TXP_SW_SZ 48 | ||
1311 | struct be_port_rxf_stats_v1 { | ||
1312 | u32 rsvd0[12]; | ||
1313 | u32 rx_crc_errors; | ||
1314 | u32 rx_alignment_symbol_errors; | ||
1315 | u32 rx_pause_frames; | ||
1316 | u32 rx_priority_pause_frames; | ||
1317 | u32 rx_control_frames; | ||
1318 | u32 rx_in_range_errors; | ||
1319 | u32 rx_out_range_errors; | ||
1320 | u32 rx_frame_too_long; | ||
1321 | u32 rx_address_match_errors; | ||
1322 | u32 rx_dropped_too_small; | ||
1323 | u32 rx_dropped_too_short; | ||
1324 | u32 rx_dropped_header_too_small; | ||
1325 | u32 rx_dropped_tcp_length; | ||
1326 | u32 rx_dropped_runt; | ||
1327 | u32 rsvd1[10]; | ||
1328 | u32 rx_ip_checksum_errs; | ||
1329 | u32 rx_tcp_checksum_errs; | ||
1330 | u32 rx_udp_checksum_errs; | ||
1331 | u32 rsvd2[7]; | ||
1332 | u32 rx_switched_unicast_packets; | ||
1333 | u32 rx_switched_multicast_packets; | ||
1334 | u32 rx_switched_broadcast_packets; | ||
1335 | u32 rsvd3[3]; | ||
1336 | u32 tx_pauseframes; | ||
1337 | u32 tx_priority_pauseframes; | ||
1338 | u32 tx_controlframes; | ||
1339 | u32 rsvd4[10]; | ||
1340 | u32 rxpp_fifo_overflow_drop; | ||
1341 | u32 rx_input_fifo_overflow_drop; | ||
1342 | u32 pmem_fifo_overflow_drop; | ||
1343 | u32 jabber_events; | ||
1344 | u32 rsvd5[3]; | ||
1345 | }; | ||
1346 | |||
1347 | |||
1348 | struct be_rxf_stats_v1 { | ||
1349 | struct be_port_rxf_stats_v1 port[4]; | ||
1350 | u32 rsvd0[2]; | ||
1351 | u32 rx_drops_no_pbuf; | ||
1352 | u32 rx_drops_no_txpb; | ||
1353 | u32 rx_drops_no_erx_descr; | ||
1354 | u32 rx_drops_no_tpre_descr; | ||
1355 | u32 rsvd1[6]; | ||
1356 | u32 rx_drops_too_many_frags; | ||
1357 | u32 rx_drops_invalid_ring; | ||
1358 | u32 forwarded_packets; | ||
1359 | u32 rx_drops_mtu; | ||
1360 | u32 rsvd2[14]; | ||
1361 | }; | ||
1362 | |||
1363 | struct be_erx_stats_v1 { | ||
1364 | u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ | ||
1365 | u32 rsvd[4]; | ||
1366 | }; | ||
1367 | |||
1368 | struct be_hw_stats_v1 { | ||
1369 | struct be_rxf_stats_v1 rxf; | ||
1370 | u32 rsvd0[BE_TXP_SW_SZ]; | ||
1371 | struct be_erx_stats_v1 erx; | ||
1372 | struct be_pmem_stats pmem; | ||
1373 | u32 rsvd1[3]; | ||
1374 | }; | ||
1375 | |||
1376 | struct be_cmd_req_get_stats_v1 { | ||
1377 | struct be_cmd_req_hdr hdr; | ||
1378 | u8 rsvd[sizeof(struct be_hw_stats_v1)]; | ||
1379 | }; | ||
1380 | |||
1381 | struct be_cmd_resp_get_stats_v1 { | ||
1382 | struct be_cmd_resp_hdr hdr; | ||
1383 | struct be_hw_stats_v1 hw_stats; | ||
1384 | }; | ||
1385 | |||
1386 | static inline void * | ||
1387 | hw_stats_from_cmd(struct be_adapter *adapter) | ||
1388 | { | ||
1389 | if (adapter->generation == BE_GEN3) { | ||
1390 | struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va; | ||
1391 | |||
1392 | return &cmd->hw_stats; | ||
1393 | } else { | ||
1394 | struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va; | ||
1395 | |||
1396 | return &cmd->hw_stats; | ||
1397 | } | ||
1398 | } | ||
1399 | |||
1400 | static inline void *be_port_rxf_stats_from_cmd(struct be_adapter *adapter) | ||
1401 | { | ||
1402 | if (adapter->generation == BE_GEN3) { | ||
1403 | struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter); | ||
1404 | struct be_rxf_stats_v1 *rxf_stats = &hw_stats->rxf; | ||
1405 | |||
1406 | return &rxf_stats->port[adapter->port_num]; | ||
1407 | } else { | ||
1408 | struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter); | ||
1409 | struct be_rxf_stats_v0 *rxf_stats = &hw_stats->rxf; | ||
1410 | |||
1411 | return &rxf_stats->port[adapter->port_num]; | ||
1412 | } | ||
1413 | } | ||
1414 | |||
1415 | static inline void *be_rxf_stats_from_cmd(struct be_adapter *adapter) | ||
1416 | { | ||
1417 | if (adapter->generation == BE_GEN3) { | ||
1418 | struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter); | ||
1419 | |||
1420 | return &hw_stats->rxf; | ||
1421 | } else { | ||
1422 | struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter); | ||
1423 | |||
1424 | return &hw_stats->rxf; | ||
1425 | } | ||
1426 | } | ||
1427 | |||
1428 | static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter) | ||
1429 | { | ||
1430 | if (adapter->generation == BE_GEN3) { | ||
1431 | struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter); | ||
1432 | |||
1433 | return &hw_stats->erx; | ||
1434 | } else { | ||
1435 | struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter); | ||
1436 | |||
1437 | return &hw_stats->erx; | ||
1438 | } | ||
1439 | } | ||
1440 | |||
1441 | static inline void *be_pmem_stats_from_cmd(struct be_adapter *adapter) | ||
1442 | { | ||
1443 | if (adapter->generation == BE_GEN3) { | ||
1444 | struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter); | ||
1445 | |||
1446 | return &hw_stats->pmem; | ||
1447 | } else { | ||
1448 | struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter); | ||
1449 | |||
1450 | return &hw_stats->pmem; | ||
1451 | } | ||
1452 | } | ||
1453 | |||
1454 | extern int be_pci_fnum_get(struct be_adapter *adapter); | ||
1455 | extern int be_cmd_POST(struct be_adapter *adapter); | ||
1456 | extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, | ||
1457 | u8 type, bool permanent, u32 if_handle); | ||
1458 | extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, | ||
1459 | u32 if_id, u32 *pmac_id, u32 domain); | ||
1460 | extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, | ||
1461 | u32 pmac_id, u32 domain); | ||
1462 | extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, | ||
1463 | u32 en_flags, u8 *mac, bool pmac_invalid, | ||
1464 | u32 *if_handle, u32 *pmac_id, u32 domain); | ||
1465 | extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle, | ||
1466 | u32 domain); | ||
1467 | extern int be_cmd_eq_create(struct be_adapter *adapter, | ||
1468 | struct be_queue_info *eq, int eq_delay); | ||
1469 | extern int be_cmd_cq_create(struct be_adapter *adapter, | ||
1470 | struct be_queue_info *cq, struct be_queue_info *eq, | ||
1471 | bool sol_evts, bool no_delay, | ||
1472 | int num_cqe_dma_coalesce); | ||
1473 | extern int be_cmd_mccq_create(struct be_adapter *adapter, | ||
1474 | struct be_queue_info *mccq, | ||
1475 | struct be_queue_info *cq); | ||
1476 | extern int be_cmd_txq_create(struct be_adapter *adapter, | ||
1477 | struct be_queue_info *txq, | ||
1478 | struct be_queue_info *cq); | ||
1479 | extern int be_cmd_rxq_create(struct be_adapter *adapter, | ||
1480 | struct be_queue_info *rxq, u16 cq_id, | ||
1481 | u16 frag_size, u16 max_frame_size, u32 if_id, | ||
1482 | u32 rss, u8 *rss_id); | ||
1483 | extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, | ||
1484 | int type); | ||
1485 | extern int be_cmd_rxq_destroy(struct be_adapter *adapter, | ||
1486 | struct be_queue_info *q); | ||
1487 | extern int be_cmd_link_status_query(struct be_adapter *adapter, | ||
1488 | bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom); | ||
1489 | extern int be_cmd_reset(struct be_adapter *adapter); | ||
1490 | extern int be_cmd_get_stats(struct be_adapter *adapter, | ||
1491 | struct be_dma_mem *nonemb_cmd); | ||
1492 | extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter, | ||
1493 | struct be_dma_mem *nonemb_cmd); | ||
1494 | extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver); | ||
1495 | |||
1496 | extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd); | ||
1497 | extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, | ||
1498 | u16 *vtag_array, u32 num, bool untagged, | ||
1499 | bool promiscuous); | ||
1500 | extern int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en); | ||
1501 | extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id, | ||
1502 | struct net_device *netdev, struct be_dma_mem *mem); | ||
1503 | extern int be_cmd_set_flow_control(struct be_adapter *adapter, | ||
1504 | u32 tx_fc, u32 rx_fc); | ||
1505 | extern int be_cmd_get_flow_control(struct be_adapter *adapter, | ||
1506 | u32 *tx_fc, u32 *rx_fc); | ||
1507 | extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, | ||
1508 | u32 *port_num, u32 *function_mode, u32 *function_caps); | ||
1509 | extern int be_cmd_reset_function(struct be_adapter *adapter); | ||
1510 | extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, | ||
1511 | u16 table_size); | ||
1512 | extern int be_process_mcc(struct be_adapter *adapter, int *status); | ||
1513 | extern int be_cmd_set_beacon_state(struct be_adapter *adapter, | ||
1514 | u8 port_num, u8 beacon, u8 status, u8 state); | ||
1515 | extern int be_cmd_get_beacon_state(struct be_adapter *adapter, | ||
1516 | u8 port_num, u32 *state); | ||
1517 | extern int be_cmd_write_flashrom(struct be_adapter *adapter, | ||
1518 | struct be_dma_mem *cmd, u32 flash_oper, | ||
1519 | u32 flash_opcode, u32 buf_size); | ||
1520 | extern int lancer_cmd_write_object(struct be_adapter *adapter, | ||
1521 | struct be_dma_mem *cmd, | ||
1522 | u32 data_size, u32 data_offset, | ||
1523 | const char *obj_name, | ||
1524 | u32 *data_written, u8 *addn_status); | ||
1525 | int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, | ||
1526 | int offset); | ||
1527 | extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, | ||
1528 | struct be_dma_mem *nonemb_cmd); | ||
1529 | extern int be_cmd_fw_init(struct be_adapter *adapter); | ||
1530 | extern int be_cmd_fw_clean(struct be_adapter *adapter); | ||
1531 | extern void be_async_mcc_enable(struct be_adapter *adapter); | ||
1532 | extern void be_async_mcc_disable(struct be_adapter *adapter); | ||
1533 | extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, | ||
1534 | u32 loopback_type, u32 pkt_size, | ||
1535 | u32 num_pkts, u64 pattern); | ||
1536 | extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, | ||
1537 | u32 byte_cnt, struct be_dma_mem *cmd); | ||
1538 | extern int be_cmd_get_seeprom_data(struct be_adapter *adapter, | ||
1539 | struct be_dma_mem *nonemb_cmd); | ||
1540 | extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, | ||
1541 | u8 loopback_type, u8 enable); | ||
1542 | extern int be_cmd_get_phy_info(struct be_adapter *adapter, | ||
1543 | struct be_dma_mem *cmd); | ||
1544 | extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain); | ||
1545 | extern void be_detect_dump_ue(struct be_adapter *adapter); | ||
1546 | extern int be_cmd_get_die_temperature(struct be_adapter *adapter); | ||
1547 | extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter); | ||
1548 | extern int be_cmd_req_native_mode(struct be_adapter *adapter); | ||
1549 | extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); | ||
1550 | extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); | ||
1551 | |||