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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/net/atlx
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/net/atlx')
-rw-r--r--drivers/net/atlx/Makefile3
-rw-r--r--drivers/net/atlx/atl1.c3675
-rw-r--r--drivers/net/atlx/atl1.h792
-rw-r--r--drivers/net/atlx/atl2.c3119
-rw-r--r--drivers/net/atlx/atl2.h525
-rw-r--r--drivers/net/atlx/atlx.c269
-rw-r--r--drivers/net/atlx/atlx.h503
7 files changed, 8886 insertions, 0 deletions
diff --git a/drivers/net/atlx/Makefile b/drivers/net/atlx/Makefile
new file mode 100644
index 00000000000..e4f6022ca55
--- /dev/null
+++ b/drivers/net/atlx/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_ATL1) += atl1.o
2obj-$(CONFIG_ATL2) += atl2.o
3
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
new file mode 100644
index 00000000000..97e6954304e
--- /dev/null
+++ b/drivers/net/atlx/atl1.c
@@ -0,0 +1,3675 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
27 * Xiong Huang <xiong.huang@atheros.com>
28 * Jie Yang <jie.yang@atheros.com>
29 * Chris Snook <csnook@redhat.com>
30 * Jay Cliburn <jcliburn@gmail.com>
31 *
32 * This version is adapted from the Attansic reference driver.
33 *
34 * TODO:
35 * Add more ethtool functions.
36 * Fix abstruse irq enable/disable condition described here:
37 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
38 *
39 * NEEDS TESTING:
40 * VLAN
41 * multicast
42 * promiscuous mode
43 * interrupt coalescing
44 * SMP torture testing
45 */
46
47#include <linux/atomic.h>
48#include <asm/byteorder.h>
49
50#include <linux/compiler.h>
51#include <linux/crc32.h>
52#include <linux/delay.h>
53#include <linux/dma-mapping.h>
54#include <linux/etherdevice.h>
55#include <linux/hardirq.h>
56#include <linux/if_ether.h>
57#include <linux/if_vlan.h>
58#include <linux/in.h>
59#include <linux/interrupt.h>
60#include <linux/ip.h>
61#include <linux/irqflags.h>
62#include <linux/irqreturn.h>
63#include <linux/jiffies.h>
64#include <linux/mii.h>
65#include <linux/module.h>
66#include <linux/moduleparam.h>
67#include <linux/net.h>
68#include <linux/netdevice.h>
69#include <linux/pci.h>
70#include <linux/pci_ids.h>
71#include <linux/pm.h>
72#include <linux/skbuff.h>
73#include <linux/slab.h>
74#include <linux/spinlock.h>
75#include <linux/string.h>
76#include <linux/tcp.h>
77#include <linux/timer.h>
78#include <linux/types.h>
79#include <linux/workqueue.h>
80
81#include <net/checksum.h>
82
83#include "atl1.h"
84
85#define ATLX_DRIVER_VERSION "2.1.3"
86MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, "
87 "Chris Snook <csnook@redhat.com>, "
88 "Jay Cliburn <jcliburn@gmail.com>");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(ATLX_DRIVER_VERSION);
91
92/* Temporary hack for merging atl1 and atl2 */
93#include "atlx.c"
94
95static const struct ethtool_ops atl1_ethtool_ops;
96
97/*
98 * This is the only thing that needs to be changed to adjust the
99 * maximum number of ports that the driver can manage.
100 */
101#define ATL1_MAX_NIC 4
102
103#define OPTION_UNSET -1
104#define OPTION_DISABLED 0
105#define OPTION_ENABLED 1
106
107#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
108
109/*
110 * Interrupt Moderate Timer in units of 2 us
111 *
112 * Valid Range: 10-65535
113 *
114 * Default Value: 100 (200us)
115 */
116static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
117static unsigned int num_int_mod_timer;
118module_param_array_named(int_mod_timer, int_mod_timer, int,
119 &num_int_mod_timer, 0);
120MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
121
122#define DEFAULT_INT_MOD_CNT 100 /* 200us */
123#define MAX_INT_MOD_CNT 65000
124#define MIN_INT_MOD_CNT 50
125
126struct atl1_option {
127 enum { enable_option, range_option, list_option } type;
128 char *name;
129 char *err;
130 int def;
131 union {
132 struct { /* range_option info */
133 int min;
134 int max;
135 } r;
136 struct { /* list_option info */
137 int nr;
138 struct atl1_opt_list {
139 int i;
140 char *str;
141 } *p;
142 } l;
143 } arg;
144};
145
146static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
147 struct pci_dev *pdev)
148{
149 if (*value == OPTION_UNSET) {
150 *value = opt->def;
151 return 0;
152 }
153
154 switch (opt->type) {
155 case enable_option:
156 switch (*value) {
157 case OPTION_ENABLED:
158 dev_info(&pdev->dev, "%s enabled\n", opt->name);
159 return 0;
160 case OPTION_DISABLED:
161 dev_info(&pdev->dev, "%s disabled\n", opt->name);
162 return 0;
163 }
164 break;
165 case range_option:
166 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
167 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
168 *value);
169 return 0;
170 }
171 break;
172 case list_option:{
173 int i;
174 struct atl1_opt_list *ent;
175
176 for (i = 0; i < opt->arg.l.nr; i++) {
177 ent = &opt->arg.l.p[i];
178 if (*value == ent->i) {
179 if (ent->str[0] != '\0')
180 dev_info(&pdev->dev, "%s\n",
181 ent->str);
182 return 0;
183 }
184 }
185 }
186 break;
187
188 default:
189 break;
190 }
191
192 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
193 opt->name, *value, opt->err);
194 *value = opt->def;
195 return -1;
196}
197
198/*
199 * atl1_check_options - Range Checking for Command Line Parameters
200 * @adapter: board private structure
201 *
202 * This routine checks all command line parameters for valid user
203 * input. If an invalid value is given, or if no user specified
204 * value exists, a default value is used. The final value is stored
205 * in a variable in the adapter structure.
206 */
207static void __devinit atl1_check_options(struct atl1_adapter *adapter)
208{
209 struct pci_dev *pdev = adapter->pdev;
210 int bd = adapter->bd_number;
211 if (bd >= ATL1_MAX_NIC) {
212 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
213 dev_notice(&pdev->dev, "using defaults for all values\n");
214 }
215 { /* Interrupt Moderate Timer */
216 struct atl1_option opt = {
217 .type = range_option,
218 .name = "Interrupt Moderator Timer",
219 .err = "using default of "
220 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
221 .def = DEFAULT_INT_MOD_CNT,
222 .arg = {.r = {.min = MIN_INT_MOD_CNT,
223 .max = MAX_INT_MOD_CNT} }
224 };
225 int val;
226 if (num_int_mod_timer > bd) {
227 val = int_mod_timer[bd];
228 atl1_validate_option(&val, &opt, pdev);
229 adapter->imt = (u16) val;
230 } else
231 adapter->imt = (u16) (opt.def);
232 }
233}
234
235/*
236 * atl1_pci_tbl - PCI Device ID Table
237 */
238static DEFINE_PCI_DEVICE_TABLE(atl1_pci_tbl) = {
239 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
240 /* required last entry */
241 {0,}
242};
243MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
244
245static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
246 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
247
248static int debug = -1;
249module_param(debug, int, 0);
250MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
251
252/*
253 * Reset the transmit and receive units; mask and clear all interrupts.
254 * hw - Struct containing variables accessed by shared code
255 * return : 0 or idle status (if error)
256 */
257static s32 atl1_reset_hw(struct atl1_hw *hw)
258{
259 struct pci_dev *pdev = hw->back->pdev;
260 struct atl1_adapter *adapter = hw->back;
261 u32 icr;
262 int i;
263
264 /*
265 * Clear Interrupt mask to stop board from generating
266 * interrupts & Clear any pending interrupt events
267 */
268 /*
269 * iowrite32(0, hw->hw_addr + REG_IMR);
270 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
271 */
272
273 /*
274 * Issue Soft Reset to the MAC. This will reset the chip's
275 * transmit, receive, DMA. It will not effect
276 * the current PCI configuration. The global reset bit is self-
277 * clearing, and should clear within a microsecond.
278 */
279 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
280 ioread32(hw->hw_addr + REG_MASTER_CTRL);
281
282 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
283 ioread16(hw->hw_addr + REG_PHY_ENABLE);
284
285 /* delay about 1ms */
286 msleep(1);
287
288 /* Wait at least 10ms for All module to be Idle */
289 for (i = 0; i < 10; i++) {
290 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
291 if (!icr)
292 break;
293 /* delay 1 ms */
294 msleep(1);
295 /* FIXME: still the right way to do this? */
296 cpu_relax();
297 }
298
299 if (icr) {
300 if (netif_msg_hw(adapter))
301 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
302 return icr;
303 }
304
305 return 0;
306}
307
308/* function about EEPROM
309 *
310 * check_eeprom_exist
311 * return 0 if eeprom exist
312 */
313static int atl1_check_eeprom_exist(struct atl1_hw *hw)
314{
315 u32 value;
316 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
317 if (value & SPI_FLASH_CTRL_EN_VPD) {
318 value &= ~SPI_FLASH_CTRL_EN_VPD;
319 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
320 }
321
322 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
323 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
324}
325
326static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
327{
328 int i;
329 u32 control;
330
331 if (offset & 3)
332 /* address do not align */
333 return false;
334
335 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
336 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
337 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
338 ioread32(hw->hw_addr + REG_VPD_CAP);
339
340 for (i = 0; i < 10; i++) {
341 msleep(2);
342 control = ioread32(hw->hw_addr + REG_VPD_CAP);
343 if (control & VPD_CAP_VPD_FLAG)
344 break;
345 }
346 if (control & VPD_CAP_VPD_FLAG) {
347 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
348 return true;
349 }
350 /* timeout */
351 return false;
352}
353
354/*
355 * Reads the value from a PHY register
356 * hw - Struct containing variables accessed by shared code
357 * reg_addr - address of the PHY register to read
358 */
359static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
360{
361 u32 val;
362 int i;
363
364 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
365 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
366 MDIO_CLK_SEL_SHIFT;
367 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
368 ioread32(hw->hw_addr + REG_MDIO_CTRL);
369
370 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
371 udelay(2);
372 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
373 if (!(val & (MDIO_START | MDIO_BUSY)))
374 break;
375 }
376 if (!(val & (MDIO_START | MDIO_BUSY))) {
377 *phy_data = (u16) val;
378 return 0;
379 }
380 return ATLX_ERR_PHY;
381}
382
383#define CUSTOM_SPI_CS_SETUP 2
384#define CUSTOM_SPI_CLK_HI 2
385#define CUSTOM_SPI_CLK_LO 2
386#define CUSTOM_SPI_CS_HOLD 2
387#define CUSTOM_SPI_CS_HI 3
388
389static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
390{
391 int i;
392 u32 value;
393
394 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
395 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
396
397 value = SPI_FLASH_CTRL_WAIT_READY |
398 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
399 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
400 SPI_FLASH_CTRL_CLK_HI_MASK) <<
401 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
402 SPI_FLASH_CTRL_CLK_LO_MASK) <<
403 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
404 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
405 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
406 SPI_FLASH_CTRL_CS_HI_MASK) <<
407 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
408 SPI_FLASH_CTRL_INS_SHIFT;
409
410 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
411
412 value |= SPI_FLASH_CTRL_START;
413 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
414 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
415
416 for (i = 0; i < 10; i++) {
417 msleep(1);
418 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
419 if (!(value & SPI_FLASH_CTRL_START))
420 break;
421 }
422
423 if (value & SPI_FLASH_CTRL_START)
424 return false;
425
426 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
427
428 return true;
429}
430
431/*
432 * get_permanent_address
433 * return 0 if get valid mac address,
434 */
435static int atl1_get_permanent_address(struct atl1_hw *hw)
436{
437 u32 addr[2];
438 u32 i, control;
439 u16 reg;
440 u8 eth_addr[ETH_ALEN];
441 bool key_valid;
442
443 if (is_valid_ether_addr(hw->perm_mac_addr))
444 return 0;
445
446 /* init */
447 addr[0] = addr[1] = 0;
448
449 if (!atl1_check_eeprom_exist(hw)) {
450 reg = 0;
451 key_valid = false;
452 /* Read out all EEPROM content */
453 i = 0;
454 while (1) {
455 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
456 if (key_valid) {
457 if (reg == REG_MAC_STA_ADDR)
458 addr[0] = control;
459 else if (reg == (REG_MAC_STA_ADDR + 4))
460 addr[1] = control;
461 key_valid = false;
462 } else if ((control & 0xff) == 0x5A) {
463 key_valid = true;
464 reg = (u16) (control >> 16);
465 } else
466 break;
467 } else
468 /* read error */
469 break;
470 i += 4;
471 }
472
473 *(u32 *) &eth_addr[2] = swab32(addr[0]);
474 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
475 if (is_valid_ether_addr(eth_addr)) {
476 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
477 return 0;
478 }
479 }
480
481 /* see if SPI FLAGS exist ? */
482 addr[0] = addr[1] = 0;
483 reg = 0;
484 key_valid = false;
485 i = 0;
486 while (1) {
487 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
488 if (key_valid) {
489 if (reg == REG_MAC_STA_ADDR)
490 addr[0] = control;
491 else if (reg == (REG_MAC_STA_ADDR + 4))
492 addr[1] = control;
493 key_valid = false;
494 } else if ((control & 0xff) == 0x5A) {
495 key_valid = true;
496 reg = (u16) (control >> 16);
497 } else
498 /* data end */
499 break;
500 } else
501 /* read error */
502 break;
503 i += 4;
504 }
505
506 *(u32 *) &eth_addr[2] = swab32(addr[0]);
507 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
508 if (is_valid_ether_addr(eth_addr)) {
509 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
510 return 0;
511 }
512
513 /*
514 * On some motherboards, the MAC address is written by the
515 * BIOS directly to the MAC register during POST, and is
516 * not stored in eeprom. If all else thus far has failed
517 * to fetch the permanent MAC address, try reading it directly.
518 */
519 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
520 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
521 *(u32 *) &eth_addr[2] = swab32(addr[0]);
522 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
523 if (is_valid_ether_addr(eth_addr)) {
524 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
525 return 0;
526 }
527
528 return 1;
529}
530
531/*
532 * Reads the adapter's MAC address from the EEPROM
533 * hw - Struct containing variables accessed by shared code
534 */
535static s32 atl1_read_mac_addr(struct atl1_hw *hw)
536{
537 u16 i;
538
539 if (atl1_get_permanent_address(hw))
540 random_ether_addr(hw->perm_mac_addr);
541
542 for (i = 0; i < ETH_ALEN; i++)
543 hw->mac_addr[i] = hw->perm_mac_addr[i];
544 return 0;
545}
546
547/*
548 * Hashes an address to determine its location in the multicast table
549 * hw - Struct containing variables accessed by shared code
550 * mc_addr - the multicast address to hash
551 *
552 * atl1_hash_mc_addr
553 * purpose
554 * set hash value for a multicast address
555 * hash calcu processing :
556 * 1. calcu 32bit CRC for multicast address
557 * 2. reverse crc with MSB to LSB
558 */
559static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
560{
561 u32 crc32, value = 0;
562 int i;
563
564 crc32 = ether_crc_le(6, mc_addr);
565 for (i = 0; i < 32; i++)
566 value |= (((crc32 >> i) & 1) << (31 - i));
567
568 return value;
569}
570
571/*
572 * Sets the bit in the multicast table corresponding to the hash value.
573 * hw - Struct containing variables accessed by shared code
574 * hash_value - Multicast address hash value
575 */
576static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
577{
578 u32 hash_bit, hash_reg;
579 u32 mta;
580
581 /*
582 * The HASH Table is a register array of 2 32-bit registers.
583 * It is treated like an array of 64 bits. We want to set
584 * bit BitArray[hash_value]. So we figure out what register
585 * the bit is in, read it, OR in the new bit, then write
586 * back the new value. The register is determined by the
587 * upper 7 bits of the hash value and the bit within that
588 * register are determined by the lower 5 bits of the value.
589 */
590 hash_reg = (hash_value >> 31) & 0x1;
591 hash_bit = (hash_value >> 26) & 0x1F;
592 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
593 mta |= (1 << hash_bit);
594 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
595}
596
597/*
598 * Writes a value to a PHY register
599 * hw - Struct containing variables accessed by shared code
600 * reg_addr - address of the PHY register to write
601 * data - data to write to the PHY
602 */
603static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
604{
605 int i;
606 u32 val;
607
608 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
609 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
610 MDIO_SUP_PREAMBLE |
611 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
612 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
613 ioread32(hw->hw_addr + REG_MDIO_CTRL);
614
615 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
616 udelay(2);
617 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
618 if (!(val & (MDIO_START | MDIO_BUSY)))
619 break;
620 }
621
622 if (!(val & (MDIO_START | MDIO_BUSY)))
623 return 0;
624
625 return ATLX_ERR_PHY;
626}
627
628/*
629 * Make L001's PHY out of Power Saving State (bug)
630 * hw - Struct containing variables accessed by shared code
631 * when power on, L001's PHY always on Power saving State
632 * (Gigabit Link forbidden)
633 */
634static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
635{
636 s32 ret;
637 ret = atl1_write_phy_reg(hw, 29, 0x0029);
638 if (ret)
639 return ret;
640 return atl1_write_phy_reg(hw, 30, 0);
641}
642
643/*
644 * Resets the PHY and make all config validate
645 * hw - Struct containing variables accessed by shared code
646 *
647 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
648 */
649static s32 atl1_phy_reset(struct atl1_hw *hw)
650{
651 struct pci_dev *pdev = hw->back->pdev;
652 struct atl1_adapter *adapter = hw->back;
653 s32 ret_val;
654 u16 phy_data;
655
656 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
657 hw->media_type == MEDIA_TYPE_1000M_FULL)
658 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
659 else {
660 switch (hw->media_type) {
661 case MEDIA_TYPE_100M_FULL:
662 phy_data =
663 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
664 MII_CR_RESET;
665 break;
666 case MEDIA_TYPE_100M_HALF:
667 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
668 break;
669 case MEDIA_TYPE_10M_FULL:
670 phy_data =
671 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
672 break;
673 default:
674 /* MEDIA_TYPE_10M_HALF: */
675 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
676 break;
677 }
678 }
679
680 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
681 if (ret_val) {
682 u32 val;
683 int i;
684 /* pcie serdes link may be down! */
685 if (netif_msg_hw(adapter))
686 dev_dbg(&pdev->dev, "pcie phy link down\n");
687
688 for (i = 0; i < 25; i++) {
689 msleep(1);
690 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
691 if (!(val & (MDIO_START | MDIO_BUSY)))
692 break;
693 }
694
695 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
696 if (netif_msg_hw(adapter))
697 dev_warn(&pdev->dev,
698 "pcie link down at least 25ms\n");
699 return ret_val;
700 }
701 }
702 return 0;
703}
704
705/*
706 * Configures PHY autoneg and flow control advertisement settings
707 * hw - Struct containing variables accessed by shared code
708 */
709static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
710{
711 s32 ret_val;
712 s16 mii_autoneg_adv_reg;
713 s16 mii_1000t_ctrl_reg;
714
715 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
716 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
717
718 /* Read the MII 1000Base-T Control Register (Address 9). */
719 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
720
721 /*
722 * First we clear all the 10/100 mb speed bits in the Auto-Neg
723 * Advertisement Register (Address 4) and the 1000 mb speed bits in
724 * the 1000Base-T Control Register (Address 9).
725 */
726 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
727 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
728
729 /*
730 * Need to parse media_type and set up
731 * the appropriate PHY registers.
732 */
733 switch (hw->media_type) {
734 case MEDIA_TYPE_AUTO_SENSOR:
735 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
736 MII_AR_10T_FD_CAPS |
737 MII_AR_100TX_HD_CAPS |
738 MII_AR_100TX_FD_CAPS);
739 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
740 break;
741
742 case MEDIA_TYPE_1000M_FULL:
743 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
744 break;
745
746 case MEDIA_TYPE_100M_FULL:
747 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
748 break;
749
750 case MEDIA_TYPE_100M_HALF:
751 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
752 break;
753
754 case MEDIA_TYPE_10M_FULL:
755 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
756 break;
757
758 default:
759 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
760 break;
761 }
762
763 /* flow control fixed to enable all */
764 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
765
766 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
767 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
768
769 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
770 if (ret_val)
771 return ret_val;
772
773 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
774 if (ret_val)
775 return ret_val;
776
777 return 0;
778}
779
780/*
781 * Configures link settings.
782 * hw - Struct containing variables accessed by shared code
783 * Assumes the hardware has previously been reset and the
784 * transmitter and receiver are not enabled.
785 */
786static s32 atl1_setup_link(struct atl1_hw *hw)
787{
788 struct pci_dev *pdev = hw->back->pdev;
789 struct atl1_adapter *adapter = hw->back;
790 s32 ret_val;
791
792 /*
793 * Options:
794 * PHY will advertise value(s) parsed from
795 * autoneg_advertised and fc
796 * no matter what autoneg is , We will not wait link result.
797 */
798 ret_val = atl1_phy_setup_autoneg_adv(hw);
799 if (ret_val) {
800 if (netif_msg_link(adapter))
801 dev_dbg(&pdev->dev,
802 "error setting up autonegotiation\n");
803 return ret_val;
804 }
805 /* SW.Reset , En-Auto-Neg if needed */
806 ret_val = atl1_phy_reset(hw);
807 if (ret_val) {
808 if (netif_msg_link(adapter))
809 dev_dbg(&pdev->dev, "error resetting phy\n");
810 return ret_val;
811 }
812 hw->phy_configured = true;
813 return ret_val;
814}
815
816static void atl1_init_flash_opcode(struct atl1_hw *hw)
817{
818 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
819 /* Atmel */
820 hw->flash_vendor = 0;
821
822 /* Init OP table */
823 iowrite8(flash_table[hw->flash_vendor].cmd_program,
824 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
825 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
826 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
827 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
828 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
829 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
830 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
831 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
832 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
833 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
834 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
835 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
836 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
837 iowrite8(flash_table[hw->flash_vendor].cmd_read,
838 hw->hw_addr + REG_SPI_FLASH_OP_READ);
839}
840
841/*
842 * Performs basic configuration of the adapter.
843 * hw - Struct containing variables accessed by shared code
844 * Assumes that the controller has previously been reset and is in a
845 * post-reset uninitialized state. Initializes multicast table,
846 * and Calls routines to setup link
847 * Leaves the transmit and receive units disabled and uninitialized.
848 */
849static s32 atl1_init_hw(struct atl1_hw *hw)
850{
851 u32 ret_val = 0;
852
853 /* Zero out the Multicast HASH table */
854 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
855 /* clear the old settings from the multicast hash table */
856 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
857
858 atl1_init_flash_opcode(hw);
859
860 if (!hw->phy_configured) {
861 /* enable GPHY LinkChange Interrrupt */
862 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
863 if (ret_val)
864 return ret_val;
865 /* make PHY out of power-saving state */
866 ret_val = atl1_phy_leave_power_saving(hw);
867 if (ret_val)
868 return ret_val;
869 /* Call a subroutine to configure the link */
870 ret_val = atl1_setup_link(hw);
871 }
872 return ret_val;
873}
874
875/*
876 * Detects the current speed and duplex settings of the hardware.
877 * hw - Struct containing variables accessed by shared code
878 * speed - Speed of the connection
879 * duplex - Duplex setting of the connection
880 */
881static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
882{
883 struct pci_dev *pdev = hw->back->pdev;
884 struct atl1_adapter *adapter = hw->back;
885 s32 ret_val;
886 u16 phy_data;
887
888 /* ; --- Read PHY Specific Status Register (17) */
889 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
890 if (ret_val)
891 return ret_val;
892
893 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
894 return ATLX_ERR_PHY_RES;
895
896 switch (phy_data & MII_ATLX_PSSR_SPEED) {
897 case MII_ATLX_PSSR_1000MBS:
898 *speed = SPEED_1000;
899 break;
900 case MII_ATLX_PSSR_100MBS:
901 *speed = SPEED_100;
902 break;
903 case MII_ATLX_PSSR_10MBS:
904 *speed = SPEED_10;
905 break;
906 default:
907 if (netif_msg_hw(adapter))
908 dev_dbg(&pdev->dev, "error getting speed\n");
909 return ATLX_ERR_PHY_SPEED;
910 break;
911 }
912 if (phy_data & MII_ATLX_PSSR_DPLX)
913 *duplex = FULL_DUPLEX;
914 else
915 *duplex = HALF_DUPLEX;
916
917 return 0;
918}
919
920static void atl1_set_mac_addr(struct atl1_hw *hw)
921{
922 u32 value;
923 /*
924 * 00-0B-6A-F6-00-DC
925 * 0: 6AF600DC 1: 000B
926 * low dword
927 */
928 value = (((u32) hw->mac_addr[2]) << 24) |
929 (((u32) hw->mac_addr[3]) << 16) |
930 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
931 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
932 /* high dword */
933 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
934 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
935}
936
937/*
938 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
939 * @adapter: board private structure to initialize
940 *
941 * atl1_sw_init initializes the Adapter private data structure.
942 * Fields are initialized based on PCI device information and
943 * OS network device settings (MTU size).
944 */
945static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
946{
947 struct atl1_hw *hw = &adapter->hw;
948 struct net_device *netdev = adapter->netdev;
949
950 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
951 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
952
953 adapter->wol = 0;
954 device_set_wakeup_enable(&adapter->pdev->dev, false);
955 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
956 adapter->ict = 50000; /* 100ms */
957 adapter->link_speed = SPEED_0; /* hardware init */
958 adapter->link_duplex = FULL_DUPLEX;
959
960 hw->phy_configured = false;
961 hw->preamble_len = 7;
962 hw->ipgt = 0x60;
963 hw->min_ifg = 0x50;
964 hw->ipgr1 = 0x40;
965 hw->ipgr2 = 0x60;
966 hw->max_retry = 0xf;
967 hw->lcol = 0x37;
968 hw->jam_ipg = 7;
969 hw->rfd_burst = 8;
970 hw->rrd_burst = 8;
971 hw->rfd_fetch_gap = 1;
972 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
973 hw->rx_jumbo_lkah = 1;
974 hw->rrd_ret_timer = 16;
975 hw->tpd_burst = 4;
976 hw->tpd_fetch_th = 16;
977 hw->txf_burst = 0x100;
978 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
979 hw->tpd_fetch_gap = 1;
980 hw->rcb_value = atl1_rcb_64;
981 hw->dma_ord = atl1_dma_ord_enh;
982 hw->dmar_block = atl1_dma_req_256;
983 hw->dmaw_block = atl1_dma_req_256;
984 hw->cmb_rrd = 4;
985 hw->cmb_tpd = 4;
986 hw->cmb_rx_timer = 1; /* about 2us */
987 hw->cmb_tx_timer = 1; /* about 2us */
988 hw->smb_timer = 100000; /* about 200ms */
989
990 spin_lock_init(&adapter->lock);
991 spin_lock_init(&adapter->mb_lock);
992
993 return 0;
994}
995
996static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
997{
998 struct atl1_adapter *adapter = netdev_priv(netdev);
999 u16 result;
1000
1001 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1002
1003 return result;
1004}
1005
1006static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1007 int val)
1008{
1009 struct atl1_adapter *adapter = netdev_priv(netdev);
1010
1011 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1012}
1013
1014/*
1015 * atl1_mii_ioctl -
1016 * @netdev:
1017 * @ifreq:
1018 * @cmd:
1019 */
1020static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1021{
1022 struct atl1_adapter *adapter = netdev_priv(netdev);
1023 unsigned long flags;
1024 int retval;
1025
1026 if (!netif_running(netdev))
1027 return -EINVAL;
1028
1029 spin_lock_irqsave(&adapter->lock, flags);
1030 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1031 spin_unlock_irqrestore(&adapter->lock, flags);
1032
1033 return retval;
1034}
1035
1036/*
1037 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1038 * @adapter: board private structure
1039 *
1040 * Return 0 on success, negative on failure
1041 */
1042static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
1043{
1044 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1045 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1046 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1047 struct atl1_ring_header *ring_header = &adapter->ring_header;
1048 struct pci_dev *pdev = adapter->pdev;
1049 int size;
1050 u8 offset = 0;
1051
1052 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1053 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1054 if (unlikely(!tpd_ring->buffer_info)) {
1055 if (netif_msg_drv(adapter))
1056 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1057 size);
1058 goto err_nomem;
1059 }
1060 rfd_ring->buffer_info =
1061 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
1062
1063 /*
1064 * real ring DMA buffer
1065 * each ring/block may need up to 8 bytes for alignment, hence the
1066 * additional 40 bytes tacked onto the end.
1067 */
1068 ring_header->size = size =
1069 sizeof(struct tx_packet_desc) * tpd_ring->count
1070 + sizeof(struct rx_free_desc) * rfd_ring->count
1071 + sizeof(struct rx_return_desc) * rrd_ring->count
1072 + sizeof(struct coals_msg_block)
1073 + sizeof(struct stats_msg_block)
1074 + 40;
1075
1076 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
1077 &ring_header->dma);
1078 if (unlikely(!ring_header->desc)) {
1079 if (netif_msg_drv(adapter))
1080 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
1081 goto err_nomem;
1082 }
1083
1084 memset(ring_header->desc, 0, ring_header->size);
1085
1086 /* init TPD ring */
1087 tpd_ring->dma = ring_header->dma;
1088 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1089 tpd_ring->dma += offset;
1090 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1091 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
1092
1093 /* init RFD ring */
1094 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1095 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1096 rfd_ring->dma += offset;
1097 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1098 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
1099
1100
1101 /* init RRD ring */
1102 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1103 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1104 rrd_ring->dma += offset;
1105 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1106 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
1107
1108
1109 /* init CMB */
1110 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1111 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1112 adapter->cmb.dma += offset;
1113 adapter->cmb.cmb = (struct coals_msg_block *)
1114 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
1115
1116 /* init SMB */
1117 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1118 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1119 adapter->smb.dma += offset;
1120 adapter->smb.smb = (struct stats_msg_block *)
1121 ((u8 *) adapter->cmb.cmb +
1122 (sizeof(struct coals_msg_block) + offset));
1123
1124 return 0;
1125
1126err_nomem:
1127 kfree(tpd_ring->buffer_info);
1128 return -ENOMEM;
1129}
1130
1131static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
1132{
1133 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1134 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1135 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1136
1137 atomic_set(&tpd_ring->next_to_use, 0);
1138 atomic_set(&tpd_ring->next_to_clean, 0);
1139
1140 rfd_ring->next_to_clean = 0;
1141 atomic_set(&rfd_ring->next_to_use, 0);
1142
1143 rrd_ring->next_to_use = 0;
1144 atomic_set(&rrd_ring->next_to_clean, 0);
1145}
1146
1147/*
1148 * atl1_clean_rx_ring - Free RFD Buffers
1149 * @adapter: board private structure
1150 */
1151static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1152{
1153 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1154 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1155 struct atl1_buffer *buffer_info;
1156 struct pci_dev *pdev = adapter->pdev;
1157 unsigned long size;
1158 unsigned int i;
1159
1160 /* Free all the Rx ring sk_buffs */
1161 for (i = 0; i < rfd_ring->count; i++) {
1162 buffer_info = &rfd_ring->buffer_info[i];
1163 if (buffer_info->dma) {
1164 pci_unmap_page(pdev, buffer_info->dma,
1165 buffer_info->length, PCI_DMA_FROMDEVICE);
1166 buffer_info->dma = 0;
1167 }
1168 if (buffer_info->skb) {
1169 dev_kfree_skb(buffer_info->skb);
1170 buffer_info->skb = NULL;
1171 }
1172 }
1173
1174 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1175 memset(rfd_ring->buffer_info, 0, size);
1176
1177 /* Zero out the descriptor ring */
1178 memset(rfd_ring->desc, 0, rfd_ring->size);
1179
1180 rfd_ring->next_to_clean = 0;
1181 atomic_set(&rfd_ring->next_to_use, 0);
1182
1183 rrd_ring->next_to_use = 0;
1184 atomic_set(&rrd_ring->next_to_clean, 0);
1185}
1186
1187/*
1188 * atl1_clean_tx_ring - Free Tx Buffers
1189 * @adapter: board private structure
1190 */
1191static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1192{
1193 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1194 struct atl1_buffer *buffer_info;
1195 struct pci_dev *pdev = adapter->pdev;
1196 unsigned long size;
1197 unsigned int i;
1198
1199 /* Free all the Tx ring sk_buffs */
1200 for (i = 0; i < tpd_ring->count; i++) {
1201 buffer_info = &tpd_ring->buffer_info[i];
1202 if (buffer_info->dma) {
1203 pci_unmap_page(pdev, buffer_info->dma,
1204 buffer_info->length, PCI_DMA_TODEVICE);
1205 buffer_info->dma = 0;
1206 }
1207 }
1208
1209 for (i = 0; i < tpd_ring->count; i++) {
1210 buffer_info = &tpd_ring->buffer_info[i];
1211 if (buffer_info->skb) {
1212 dev_kfree_skb_any(buffer_info->skb);
1213 buffer_info->skb = NULL;
1214 }
1215 }
1216
1217 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1218 memset(tpd_ring->buffer_info, 0, size);
1219
1220 /* Zero out the descriptor ring */
1221 memset(tpd_ring->desc, 0, tpd_ring->size);
1222
1223 atomic_set(&tpd_ring->next_to_use, 0);
1224 atomic_set(&tpd_ring->next_to_clean, 0);
1225}
1226
1227/*
1228 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1229 * @adapter: board private structure
1230 *
1231 * Free all transmit software resources
1232 */
1233static void atl1_free_ring_resources(struct atl1_adapter *adapter)
1234{
1235 struct pci_dev *pdev = adapter->pdev;
1236 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1237 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1238 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1239 struct atl1_ring_header *ring_header = &adapter->ring_header;
1240
1241 atl1_clean_tx_ring(adapter);
1242 atl1_clean_rx_ring(adapter);
1243
1244 kfree(tpd_ring->buffer_info);
1245 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1246 ring_header->dma);
1247
1248 tpd_ring->buffer_info = NULL;
1249 tpd_ring->desc = NULL;
1250 tpd_ring->dma = 0;
1251
1252 rfd_ring->buffer_info = NULL;
1253 rfd_ring->desc = NULL;
1254 rfd_ring->dma = 0;
1255
1256 rrd_ring->desc = NULL;
1257 rrd_ring->dma = 0;
1258
1259 adapter->cmb.dma = 0;
1260 adapter->cmb.cmb = NULL;
1261
1262 adapter->smb.dma = 0;
1263 adapter->smb.smb = NULL;
1264}
1265
1266static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
1267{
1268 u32 value;
1269 struct atl1_hw *hw = &adapter->hw;
1270 struct net_device *netdev = adapter->netdev;
1271 /* Config MAC CTRL Register */
1272 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1273 /* duplex */
1274 if (FULL_DUPLEX == adapter->link_duplex)
1275 value |= MAC_CTRL_DUPLX;
1276 /* speed */
1277 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1278 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1279 MAC_CTRL_SPEED_SHIFT);
1280 /* flow control */
1281 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1282 /* PAD & CRC */
1283 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1284 /* preamble length */
1285 value |= (((u32) adapter->hw.preamble_len
1286 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1287 /* vlan */
1288 __atlx_vlan_mode(netdev->features, &value);
1289 /* rx checksum
1290 if (adapter->rx_csum)
1291 value |= MAC_CTRL_RX_CHKSUM_EN;
1292 */
1293 /* filter mode */
1294 value |= MAC_CTRL_BC_EN;
1295 if (netdev->flags & IFF_PROMISC)
1296 value |= MAC_CTRL_PROMIS_EN;
1297 else if (netdev->flags & IFF_ALLMULTI)
1298 value |= MAC_CTRL_MC_ALL_EN;
1299 /* value |= MAC_CTRL_LOOPBACK; */
1300 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1301}
1302
1303static u32 atl1_check_link(struct atl1_adapter *adapter)
1304{
1305 struct atl1_hw *hw = &adapter->hw;
1306 struct net_device *netdev = adapter->netdev;
1307 u32 ret_val;
1308 u16 speed, duplex, phy_data;
1309 int reconfig = 0;
1310
1311 /* MII_BMSR must read twice */
1312 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1313 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1314 if (!(phy_data & BMSR_LSTATUS)) {
1315 /* link down */
1316 if (netif_carrier_ok(netdev)) {
1317 /* old link state: Up */
1318 if (netif_msg_link(adapter))
1319 dev_info(&adapter->pdev->dev, "link is down\n");
1320 adapter->link_speed = SPEED_0;
1321 netif_carrier_off(netdev);
1322 }
1323 return 0;
1324 }
1325
1326 /* Link Up */
1327 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1328 if (ret_val)
1329 return ret_val;
1330
1331 switch (hw->media_type) {
1332 case MEDIA_TYPE_1000M_FULL:
1333 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1334 reconfig = 1;
1335 break;
1336 case MEDIA_TYPE_100M_FULL:
1337 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1338 reconfig = 1;
1339 break;
1340 case MEDIA_TYPE_100M_HALF:
1341 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1342 reconfig = 1;
1343 break;
1344 case MEDIA_TYPE_10M_FULL:
1345 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1346 reconfig = 1;
1347 break;
1348 case MEDIA_TYPE_10M_HALF:
1349 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1350 reconfig = 1;
1351 break;
1352 }
1353
1354 /* link result is our setting */
1355 if (!reconfig) {
1356 if (adapter->link_speed != speed ||
1357 adapter->link_duplex != duplex) {
1358 adapter->link_speed = speed;
1359 adapter->link_duplex = duplex;
1360 atl1_setup_mac_ctrl(adapter);
1361 if (netif_msg_link(adapter))
1362 dev_info(&adapter->pdev->dev,
1363 "%s link is up %d Mbps %s\n",
1364 netdev->name, adapter->link_speed,
1365 adapter->link_duplex == FULL_DUPLEX ?
1366 "full duplex" : "half duplex");
1367 }
1368 if (!netif_carrier_ok(netdev)) {
1369 /* Link down -> Up */
1370 netif_carrier_on(netdev);
1371 }
1372 return 0;
1373 }
1374
1375 /* change original link status */
1376 if (netif_carrier_ok(netdev)) {
1377 adapter->link_speed = SPEED_0;
1378 netif_carrier_off(netdev);
1379 netif_stop_queue(netdev);
1380 }
1381
1382 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1383 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1384 switch (hw->media_type) {
1385 case MEDIA_TYPE_100M_FULL:
1386 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1387 MII_CR_RESET;
1388 break;
1389 case MEDIA_TYPE_100M_HALF:
1390 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1391 break;
1392 case MEDIA_TYPE_10M_FULL:
1393 phy_data =
1394 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1395 break;
1396 default:
1397 /* MEDIA_TYPE_10M_HALF: */
1398 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1399 break;
1400 }
1401 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1402 return 0;
1403 }
1404
1405 /* auto-neg, insert timer to re-config phy */
1406 if (!adapter->phy_timer_pending) {
1407 adapter->phy_timer_pending = true;
1408 mod_timer(&adapter->phy_config_timer,
1409 round_jiffies(jiffies + 3 * HZ));
1410 }
1411
1412 return 0;
1413}
1414
1415static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1416{
1417 u32 hi, lo, value;
1418
1419 /* RFD Flow Control */
1420 value = adapter->rfd_ring.count;
1421 hi = value / 16;
1422 if (hi < 2)
1423 hi = 2;
1424 lo = value * 7 / 8;
1425
1426 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1427 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1428 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1429
1430 /* RRD Flow Control */
1431 value = adapter->rrd_ring.count;
1432 lo = value / 16;
1433 hi = value * 7 / 8;
1434 if (lo < 2)
1435 lo = 2;
1436 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1437 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1438 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1439}
1440
1441static void set_flow_ctrl_new(struct atl1_hw *hw)
1442{
1443 u32 hi, lo, value;
1444
1445 /* RXF Flow Control */
1446 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1447 lo = value / 16;
1448 if (lo < 192)
1449 lo = 192;
1450 hi = value * 7 / 8;
1451 if (hi < lo)
1452 hi = lo + 16;
1453 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1454 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1455 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1456
1457 /* RRD Flow Control */
1458 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1459 lo = value / 8;
1460 hi = value * 7 / 8;
1461 if (lo < 2)
1462 lo = 2;
1463 if (hi < lo)
1464 hi = lo + 3;
1465 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1466 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1467 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1468}
1469
1470/*
1471 * atl1_configure - Configure Transmit&Receive Unit after Reset
1472 * @adapter: board private structure
1473 *
1474 * Configure the Tx /Rx unit of the MAC after a reset.
1475 */
1476static u32 atl1_configure(struct atl1_adapter *adapter)
1477{
1478 struct atl1_hw *hw = &adapter->hw;
1479 u32 value;
1480
1481 /* clear interrupt status */
1482 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1483
1484 /* set MAC Address */
1485 value = (((u32) hw->mac_addr[2]) << 24) |
1486 (((u32) hw->mac_addr[3]) << 16) |
1487 (((u32) hw->mac_addr[4]) << 8) |
1488 (((u32) hw->mac_addr[5]));
1489 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1490 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1491 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1492
1493 /* tx / rx ring */
1494
1495 /* HI base address */
1496 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1497 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1498 /* LO base address */
1499 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1500 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1501 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1502 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1503 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1504 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1505 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1506 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1507 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1508 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1509
1510 /* element count */
1511 value = adapter->rrd_ring.count;
1512 value <<= 16;
1513 value += adapter->rfd_ring.count;
1514 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1515 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1516 REG_DESC_TPD_RING_SIZE);
1517
1518 /* Load Ptr */
1519 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1520
1521 /* config Mailbox */
1522 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1523 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1524 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1525 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1526 ((atomic_read(&adapter->rfd_ring.next_to_use)
1527 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1528 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1529
1530 /* config IPG/IFG */
1531 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1532 << MAC_IPG_IFG_IPGT_SHIFT) |
1533 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1534 << MAC_IPG_IFG_MIFG_SHIFT) |
1535 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1536 << MAC_IPG_IFG_IPGR1_SHIFT) |
1537 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1538 << MAC_IPG_IFG_IPGR2_SHIFT);
1539 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1540
1541 /* config Half-Duplex Control */
1542 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1543 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1544 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1545 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1546 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1547 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1548 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1549 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1550
1551 /* set Interrupt Moderator Timer */
1552 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1553 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1554
1555 /* set Interrupt Clear Timer */
1556 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1557
1558 /* set max frame size hw will accept */
1559 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1560
1561 /* jumbo size & rrd retirement timer */
1562 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1563 << RXQ_JMBOSZ_TH_SHIFT) |
1564 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1565 << RXQ_JMBO_LKAH_SHIFT) |
1566 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1567 << RXQ_RRD_TIMER_SHIFT);
1568 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1569
1570 /* Flow Control */
1571 switch (hw->dev_rev) {
1572 case 0x8001:
1573 case 0x9001:
1574 case 0x9002:
1575 case 0x9003:
1576 set_flow_ctrl_old(adapter);
1577 break;
1578 default:
1579 set_flow_ctrl_new(hw);
1580 break;
1581 }
1582
1583 /* config TXQ */
1584 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1585 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1586 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1587 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1588 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1589 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1590 TXQ_CTRL_EN;
1591 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1592
1593 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1594 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1595 << TX_JUMBO_TASK_TH_SHIFT) |
1596 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1597 << TX_TPD_MIN_IPG_SHIFT);
1598 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1599
1600 /* config RXQ */
1601 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1602 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1603 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1604 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1605 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1606 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1607 RXQ_CTRL_EN;
1608 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1609
1610 /* config DMA Engine */
1611 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1612 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1613 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1614 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
1615 DMA_CTRL_DMAW_EN;
1616 value |= (u32) hw->dma_ord;
1617 if (atl1_rcb_128 == hw->rcb_value)
1618 value |= DMA_CTRL_RCB_VALUE;
1619 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1620
1621 /* config CMB / SMB */
1622 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1623 hw->cmb_tpd : adapter->tpd_ring.count;
1624 value <<= 16;
1625 value |= hw->cmb_rrd;
1626 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1627 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1628 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1629 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1630
1631 /* --- enable CMB / SMB */
1632 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1633 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1634
1635 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1636 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1637 value = 1; /* config failed */
1638 else
1639 value = 0;
1640
1641 /* clear all interrupt status */
1642 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1643 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1644 return value;
1645}
1646
1647/*
1648 * atl1_pcie_patch - Patch for PCIE module
1649 */
1650static void atl1_pcie_patch(struct atl1_adapter *adapter)
1651{
1652 u32 value;
1653
1654 /* much vendor magic here */
1655 value = 0x6500;
1656 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1657 /* pcie flow control mode change */
1658 value = ioread32(adapter->hw.hw_addr + 0x1008);
1659 value |= 0x8000;
1660 iowrite32(value, adapter->hw.hw_addr + 0x1008);
1661}
1662
1663/*
1664 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1665 * on PCI Command register is disable.
1666 * The function enable this bit.
1667 * Brackett, 2006/03/15
1668 */
1669static void atl1_via_workaround(struct atl1_adapter *adapter)
1670{
1671 unsigned long value;
1672
1673 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1674 if (value & PCI_COMMAND_INTX_DISABLE)
1675 value &= ~PCI_COMMAND_INTX_DISABLE;
1676 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1677}
1678
1679static void atl1_inc_smb(struct atl1_adapter *adapter)
1680{
1681 struct net_device *netdev = adapter->netdev;
1682 struct stats_msg_block *smb = adapter->smb.smb;
1683
1684 /* Fill out the OS statistics structure */
1685 adapter->soft_stats.rx_packets += smb->rx_ok;
1686 adapter->soft_stats.tx_packets += smb->tx_ok;
1687 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1688 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1689 adapter->soft_stats.multicast += smb->rx_mcast;
1690 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1691 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1692
1693 /* Rx Errors */
1694 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1695 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1696 smb->rx_rrd_ov + smb->rx_align_err);
1697 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1698 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1699 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1700 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1701 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1702 smb->rx_rxf_ov);
1703
1704 adapter->soft_stats.rx_pause += smb->rx_pause;
1705 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1706 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1707
1708 /* Tx Errors */
1709 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1710 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1711 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1712 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1713 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1714
1715 adapter->soft_stats.excecol += smb->tx_abort_col;
1716 adapter->soft_stats.deffer += smb->tx_defer;
1717 adapter->soft_stats.scc += smb->tx_1_col;
1718 adapter->soft_stats.mcc += smb->tx_2_col;
1719 adapter->soft_stats.latecol += smb->tx_late_col;
1720 adapter->soft_stats.tx_underun += smb->tx_underrun;
1721 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1722 adapter->soft_stats.tx_pause += smb->tx_pause;
1723
1724 netdev->stats.rx_packets = adapter->soft_stats.rx_packets;
1725 netdev->stats.tx_packets = adapter->soft_stats.tx_packets;
1726 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes;
1727 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes;
1728 netdev->stats.multicast = adapter->soft_stats.multicast;
1729 netdev->stats.collisions = adapter->soft_stats.collisions;
1730 netdev->stats.rx_errors = adapter->soft_stats.rx_errors;
1731 netdev->stats.rx_over_errors =
1732 adapter->soft_stats.rx_missed_errors;
1733 netdev->stats.rx_length_errors =
1734 adapter->soft_stats.rx_length_errors;
1735 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1736 netdev->stats.rx_frame_errors =
1737 adapter->soft_stats.rx_frame_errors;
1738 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1739 netdev->stats.rx_missed_errors =
1740 adapter->soft_stats.rx_missed_errors;
1741 netdev->stats.tx_errors = adapter->soft_stats.tx_errors;
1742 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1743 netdev->stats.tx_aborted_errors =
1744 adapter->soft_stats.tx_aborted_errors;
1745 netdev->stats.tx_window_errors =
1746 adapter->soft_stats.tx_window_errors;
1747 netdev->stats.tx_carrier_errors =
1748 adapter->soft_stats.tx_carrier_errors;
1749}
1750
1751static void atl1_update_mailbox(struct atl1_adapter *adapter)
1752{
1753 unsigned long flags;
1754 u32 tpd_next_to_use;
1755 u32 rfd_next_to_use;
1756 u32 rrd_next_to_clean;
1757 u32 value;
1758
1759 spin_lock_irqsave(&adapter->mb_lock, flags);
1760
1761 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1762 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1763 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1764
1765 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1766 MB_RFD_PROD_INDX_SHIFT) |
1767 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1768 MB_RRD_CONS_INDX_SHIFT) |
1769 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1770 MB_TPD_PROD_INDX_SHIFT);
1771 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1772
1773 spin_unlock_irqrestore(&adapter->mb_lock, flags);
1774}
1775
1776static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1777 struct rx_return_desc *rrd, u16 offset)
1778{
1779 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1780
1781 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1782 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1783 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1784 rfd_ring->next_to_clean = 0;
1785 }
1786 }
1787}
1788
1789static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1790 struct rx_return_desc *rrd)
1791{
1792 u16 num_buf;
1793
1794 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1795 adapter->rx_buffer_len;
1796 if (rrd->num_buf == num_buf)
1797 /* clean alloc flag for bad rrd */
1798 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1799}
1800
1801static void atl1_rx_checksum(struct atl1_adapter *adapter,
1802 struct rx_return_desc *rrd, struct sk_buff *skb)
1803{
1804 struct pci_dev *pdev = adapter->pdev;
1805
1806 /*
1807 * The L1 hardware contains a bug that erroneously sets the
1808 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a
1809 * fragmented IP packet is received, even though the packet
1810 * is perfectly valid and its checksum is correct. There's
1811 * no way to distinguish between one of these good packets
1812 * and a packet that actually contains a TCP/UDP checksum
1813 * error, so all we can do is allow it to be handed up to
1814 * the higher layers and let it be sorted out there.
1815 */
1816
1817 skb_checksum_none_assert(skb);
1818
1819 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1820 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1821 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1822 adapter->hw_csum_err++;
1823 if (netif_msg_rx_err(adapter))
1824 dev_printk(KERN_DEBUG, &pdev->dev,
1825 "rx checksum error\n");
1826 return;
1827 }
1828 }
1829
1830 /* not IPv4 */
1831 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1832 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1833 return;
1834
1835 /* IPv4 packet */
1836 if (likely(!(rrd->err_flg &
1837 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1838 skb->ip_summed = CHECKSUM_UNNECESSARY;
1839 adapter->hw_csum_good++;
1840 return;
1841 }
1842}
1843
1844/*
1845 * atl1_alloc_rx_buffers - Replace used receive buffers
1846 * @adapter: address of board private structure
1847 */
1848static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1849{
1850 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1851 struct pci_dev *pdev = adapter->pdev;
1852 struct page *page;
1853 unsigned long offset;
1854 struct atl1_buffer *buffer_info, *next_info;
1855 struct sk_buff *skb;
1856 u16 num_alloc = 0;
1857 u16 rfd_next_to_use, next_next;
1858 struct rx_free_desc *rfd_desc;
1859
1860 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1861 if (++next_next == rfd_ring->count)
1862 next_next = 0;
1863 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1864 next_info = &rfd_ring->buffer_info[next_next];
1865
1866 while (!buffer_info->alloced && !next_info->alloced) {
1867 if (buffer_info->skb) {
1868 buffer_info->alloced = 1;
1869 goto next;
1870 }
1871
1872 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1873
1874 skb = netdev_alloc_skb_ip_align(adapter->netdev,
1875 adapter->rx_buffer_len);
1876 if (unlikely(!skb)) {
1877 /* Better luck next round */
1878 adapter->netdev->stats.rx_dropped++;
1879 break;
1880 }
1881
1882 buffer_info->alloced = 1;
1883 buffer_info->skb = skb;
1884 buffer_info->length = (u16) adapter->rx_buffer_len;
1885 page = virt_to_page(skb->data);
1886 offset = (unsigned long)skb->data & ~PAGE_MASK;
1887 buffer_info->dma = pci_map_page(pdev, page, offset,
1888 adapter->rx_buffer_len,
1889 PCI_DMA_FROMDEVICE);
1890 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1891 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1892 rfd_desc->coalese = 0;
1893
1894next:
1895 rfd_next_to_use = next_next;
1896 if (unlikely(++next_next == rfd_ring->count))
1897 next_next = 0;
1898
1899 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1900 next_info = &rfd_ring->buffer_info[next_next];
1901 num_alloc++;
1902 }
1903
1904 if (num_alloc) {
1905 /*
1906 * Force memory writes to complete before letting h/w
1907 * know there are new descriptors to fetch. (Only
1908 * applicable for weak-ordered memory model archs,
1909 * such as IA-64).
1910 */
1911 wmb();
1912 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1913 }
1914 return num_alloc;
1915}
1916
1917static void atl1_intr_rx(struct atl1_adapter *adapter)
1918{
1919 int i, count;
1920 u16 length;
1921 u16 rrd_next_to_clean;
1922 u32 value;
1923 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1924 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1925 struct atl1_buffer *buffer_info;
1926 struct rx_return_desc *rrd;
1927 struct sk_buff *skb;
1928
1929 count = 0;
1930
1931 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
1932
1933 while (1) {
1934 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1935 i = 1;
1936 if (likely(rrd->xsz.valid)) { /* packet valid */
1937chk_rrd:
1938 /* check rrd status */
1939 if (likely(rrd->num_buf == 1))
1940 goto rrd_ok;
1941 else if (netif_msg_rx_err(adapter)) {
1942 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1943 "unexpected RRD buffer count\n");
1944 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1945 "rx_buf_len = %d\n",
1946 adapter->rx_buffer_len);
1947 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1948 "RRD num_buf = %d\n",
1949 rrd->num_buf);
1950 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1951 "RRD pkt_len = %d\n",
1952 rrd->xsz.xsum_sz.pkt_size);
1953 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1954 "RRD pkt_flg = 0x%08X\n",
1955 rrd->pkt_flg);
1956 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1957 "RRD err_flg = 0x%08X\n",
1958 rrd->err_flg);
1959 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1960 "RRD vlan_tag = 0x%08X\n",
1961 rrd->vlan_tag);
1962 }
1963
1964 /* rrd seems to be bad */
1965 if (unlikely(i-- > 0)) {
1966 /* rrd may not be DMAed completely */
1967 udelay(1);
1968 goto chk_rrd;
1969 }
1970 /* bad rrd */
1971 if (netif_msg_rx_err(adapter))
1972 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1973 "bad RRD\n");
1974 /* see if update RFD index */
1975 if (rrd->num_buf > 1)
1976 atl1_update_rfd_index(adapter, rrd);
1977
1978 /* update rrd */
1979 rrd->xsz.valid = 0;
1980 if (++rrd_next_to_clean == rrd_ring->count)
1981 rrd_next_to_clean = 0;
1982 count++;
1983 continue;
1984 } else { /* current rrd still not be updated */
1985
1986 break;
1987 }
1988rrd_ok:
1989 /* clean alloc flag for bad rrd */
1990 atl1_clean_alloc_flag(adapter, rrd, 0);
1991
1992 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
1993 if (++rfd_ring->next_to_clean == rfd_ring->count)
1994 rfd_ring->next_to_clean = 0;
1995
1996 /* update rrd next to clean */
1997 if (++rrd_next_to_clean == rrd_ring->count)
1998 rrd_next_to_clean = 0;
1999 count++;
2000
2001 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
2002 if (!(rrd->err_flg &
2003 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2004 | ERR_FLAG_LEN))) {
2005 /* packet error, don't need upstream */
2006 buffer_info->alloced = 0;
2007 rrd->xsz.valid = 0;
2008 continue;
2009 }
2010 }
2011
2012 /* Good Receive */
2013 pci_unmap_page(adapter->pdev, buffer_info->dma,
2014 buffer_info->length, PCI_DMA_FROMDEVICE);
2015 buffer_info->dma = 0;
2016 skb = buffer_info->skb;
2017 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
2018
2019 skb_put(skb, length - ETH_FCS_LEN);
2020
2021 /* Receive Checksum Offload */
2022 atl1_rx_checksum(adapter, rrd, skb);
2023 skb->protocol = eth_type_trans(skb, adapter->netdev);
2024
2025 if (rrd->pkt_flg & PACKET_FLAG_VLAN_INS) {
2026 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2027 ((rrd->vlan_tag & 7) << 13) |
2028 ((rrd->vlan_tag & 8) << 9);
2029
2030 __vlan_hwaccel_put_tag(skb, vlan_tag);
2031 }
2032 netif_rx(skb);
2033
2034 /* let protocol layer free skb */
2035 buffer_info->skb = NULL;
2036 buffer_info->alloced = 0;
2037 rrd->xsz.valid = 0;
2038 }
2039
2040 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
2041
2042 atl1_alloc_rx_buffers(adapter);
2043
2044 /* update mailbox ? */
2045 if (count) {
2046 u32 tpd_next_to_use;
2047 u32 rfd_next_to_use;
2048
2049 spin_lock(&adapter->mb_lock);
2050
2051 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2052 rfd_next_to_use =
2053 atomic_read(&adapter->rfd_ring.next_to_use);
2054 rrd_next_to_clean =
2055 atomic_read(&adapter->rrd_ring.next_to_clean);
2056 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2057 MB_RFD_PROD_INDX_SHIFT) |
2058 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2059 MB_RRD_CONS_INDX_SHIFT) |
2060 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2061 MB_TPD_PROD_INDX_SHIFT);
2062 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2063 spin_unlock(&adapter->mb_lock);
2064 }
2065}
2066
2067static void atl1_intr_tx(struct atl1_adapter *adapter)
2068{
2069 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2070 struct atl1_buffer *buffer_info;
2071 u16 sw_tpd_next_to_clean;
2072 u16 cmb_tpd_next_to_clean;
2073
2074 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2075 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
2076
2077 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2078 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2079 if (buffer_info->dma) {
2080 pci_unmap_page(adapter->pdev, buffer_info->dma,
2081 buffer_info->length, PCI_DMA_TODEVICE);
2082 buffer_info->dma = 0;
2083 }
2084
2085 if (buffer_info->skb) {
2086 dev_kfree_skb_irq(buffer_info->skb);
2087 buffer_info->skb = NULL;
2088 }
2089
2090 if (++sw_tpd_next_to_clean == tpd_ring->count)
2091 sw_tpd_next_to_clean = 0;
2092 }
2093 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2094
2095 if (netif_queue_stopped(adapter->netdev) &&
2096 netif_carrier_ok(adapter->netdev))
2097 netif_wake_queue(adapter->netdev);
2098}
2099
2100static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
2101{
2102 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2103 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
2104 return (next_to_clean > next_to_use) ?
2105 next_to_clean - next_to_use - 1 :
2106 tpd_ring->count + next_to_clean - next_to_use - 1;
2107}
2108
2109static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
2110 struct tx_packet_desc *ptpd)
2111{
2112 u8 hdr_len, ip_off;
2113 u32 real_len;
2114 int err;
2115
2116 if (skb_shinfo(skb)->gso_size) {
2117 if (skb_header_cloned(skb)) {
2118 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2119 if (unlikely(err))
2120 return -1;
2121 }
2122
2123 if (skb->protocol == htons(ETH_P_IP)) {
2124 struct iphdr *iph = ip_hdr(skb);
2125
2126 real_len = (((unsigned char *)iph - skb->data) +
2127 ntohs(iph->tot_len));
2128 if (real_len < skb->len)
2129 pskb_trim(skb, real_len);
2130 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2131 if (skb->len == hdr_len) {
2132 iph->check = 0;
2133 tcp_hdr(skb)->check =
2134 ~csum_tcpudp_magic(iph->saddr,
2135 iph->daddr, tcp_hdrlen(skb),
2136 IPPROTO_TCP, 0);
2137 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2138 TPD_IPHL_SHIFT;
2139 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2140 TPD_TCPHDRLEN_MASK) <<
2141 TPD_TCPHDRLEN_SHIFT;
2142 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2143 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2144 return 1;
2145 }
2146
2147 iph->check = 0;
2148 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2149 iph->daddr, 0, IPPROTO_TCP, 0);
2150 ip_off = (unsigned char *)iph -
2151 (unsigned char *) skb_network_header(skb);
2152 if (ip_off == 8) /* 802.3-SNAP frame */
2153 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2154 else if (ip_off != 0)
2155 return -2;
2156
2157 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2158 TPD_IPHL_SHIFT;
2159 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2160 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2161 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2162 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2163 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2164 return 3;
2165 }
2166 }
2167 return false;
2168}
2169
2170static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
2171 struct tx_packet_desc *ptpd)
2172{
2173 u8 css, cso;
2174
2175 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2176 css = skb_checksum_start_offset(skb);
2177 cso = css + (u8) skb->csum_offset;
2178 if (unlikely(css & 0x1)) {
2179 /* L1 hardware requires an even number here */
2180 if (netif_msg_tx_err(adapter))
2181 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2182 "payload offset not an even number\n");
2183 return -1;
2184 }
2185 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2186 TPD_PLOADOFFSET_SHIFT;
2187 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2188 TPD_CCSUMOFFSET_SHIFT;
2189 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
2190 return true;
2191 }
2192 return 0;
2193}
2194
2195static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
2196 struct tx_packet_desc *ptpd)
2197{
2198 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2199 struct atl1_buffer *buffer_info;
2200 u16 buf_len = skb->len;
2201 struct page *page;
2202 unsigned long offset;
2203 unsigned int nr_frags;
2204 unsigned int f;
2205 int retval;
2206 u16 next_to_use;
2207 u16 data_len;
2208 u8 hdr_len;
2209
2210 buf_len -= skb->data_len;
2211 nr_frags = skb_shinfo(skb)->nr_frags;
2212 next_to_use = atomic_read(&tpd_ring->next_to_use);
2213 buffer_info = &tpd_ring->buffer_info[next_to_use];
2214 BUG_ON(buffer_info->skb);
2215 /* put skb in last TPD */
2216 buffer_info->skb = NULL;
2217
2218 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2219 if (retval) {
2220 /* TSO */
2221 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2222 buffer_info->length = hdr_len;
2223 page = virt_to_page(skb->data);
2224 offset = (unsigned long)skb->data & ~PAGE_MASK;
2225 buffer_info->dma = pci_map_page(adapter->pdev, page,
2226 offset, hdr_len,
2227 PCI_DMA_TODEVICE);
2228
2229 if (++next_to_use == tpd_ring->count)
2230 next_to_use = 0;
2231
2232 if (buf_len > hdr_len) {
2233 int i, nseg;
2234
2235 data_len = buf_len - hdr_len;
2236 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
2237 ATL1_MAX_TX_BUF_LEN;
2238 for (i = 0; i < nseg; i++) {
2239 buffer_info =
2240 &tpd_ring->buffer_info[next_to_use];
2241 buffer_info->skb = NULL;
2242 buffer_info->length =
2243 (ATL1_MAX_TX_BUF_LEN >=
2244 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2245 data_len -= buffer_info->length;
2246 page = virt_to_page(skb->data +
2247 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
2248 offset = (unsigned long)(skb->data +
2249 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2250 ~PAGE_MASK;
2251 buffer_info->dma = pci_map_page(adapter->pdev,
2252 page, offset, buffer_info->length,
2253 PCI_DMA_TODEVICE);
2254 if (++next_to_use == tpd_ring->count)
2255 next_to_use = 0;
2256 }
2257 }
2258 } else {
2259 /* not TSO */
2260 buffer_info->length = buf_len;
2261 page = virt_to_page(skb->data);
2262 offset = (unsigned long)skb->data & ~PAGE_MASK;
2263 buffer_info->dma = pci_map_page(adapter->pdev, page,
2264 offset, buf_len, PCI_DMA_TODEVICE);
2265 if (++next_to_use == tpd_ring->count)
2266 next_to_use = 0;
2267 }
2268
2269 for (f = 0; f < nr_frags; f++) {
2270 struct skb_frag_struct *frag;
2271 u16 i, nseg;
2272
2273 frag = &skb_shinfo(skb)->frags[f];
2274 buf_len = frag->size;
2275
2276 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2277 ATL1_MAX_TX_BUF_LEN;
2278 for (i = 0; i < nseg; i++) {
2279 buffer_info = &tpd_ring->buffer_info[next_to_use];
2280 BUG_ON(buffer_info->skb);
2281
2282 buffer_info->skb = NULL;
2283 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2284 ATL1_MAX_TX_BUF_LEN : buf_len;
2285 buf_len -= buffer_info->length;
2286 buffer_info->dma = pci_map_page(adapter->pdev,
2287 frag->page,
2288 frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
2289 buffer_info->length, PCI_DMA_TODEVICE);
2290
2291 if (++next_to_use == tpd_ring->count)
2292 next_to_use = 0;
2293 }
2294 }
2295
2296 /* last tpd's buffer-info */
2297 buffer_info->skb = skb;
2298}
2299
2300static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2301 struct tx_packet_desc *ptpd)
2302{
2303 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2304 struct atl1_buffer *buffer_info;
2305 struct tx_packet_desc *tpd;
2306 u16 j;
2307 u32 val;
2308 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
2309
2310 for (j = 0; j < count; j++) {
2311 buffer_info = &tpd_ring->buffer_info[next_to_use];
2312 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2313 if (tpd != ptpd)
2314 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
2315 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2316 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT);
2317 tpd->word2 |= (cpu_to_le16(buffer_info->length) &
2318 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
2319
2320 /*
2321 * if this is the first packet in a TSO chain, set
2322 * TPD_HDRFLAG, otherwise, clear it.
2323 */
2324 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2325 TPD_SEGMENT_EN_MASK;
2326 if (val) {
2327 if (!j)
2328 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2329 else
2330 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2331 }
2332
2333 if (j == (count - 1))
2334 tpd->word3 |= 1 << TPD_EOP_SHIFT;
2335
2336 if (++next_to_use == tpd_ring->count)
2337 next_to_use = 0;
2338 }
2339 /*
2340 * Force memory writes to complete before letting h/w
2341 * know there are new descriptors to fetch. (Only
2342 * applicable for weak-ordered memory model archs,
2343 * such as IA-64).
2344 */
2345 wmb();
2346
2347 atomic_set(&tpd_ring->next_to_use, next_to_use);
2348}
2349
2350static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb,
2351 struct net_device *netdev)
2352{
2353 struct atl1_adapter *adapter = netdev_priv(netdev);
2354 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2355 int len;
2356 int tso;
2357 int count = 1;
2358 int ret_val;
2359 struct tx_packet_desc *ptpd;
2360 u16 frag_size;
2361 u16 vlan_tag;
2362 unsigned int nr_frags = 0;
2363 unsigned int mss = 0;
2364 unsigned int f;
2365 unsigned int proto_hdr_len;
2366
2367 len = skb_headlen(skb);
2368
2369 if (unlikely(skb->len <= 0)) {
2370 dev_kfree_skb_any(skb);
2371 return NETDEV_TX_OK;
2372 }
2373
2374 nr_frags = skb_shinfo(skb)->nr_frags;
2375 for (f = 0; f < nr_frags; f++) {
2376 frag_size = skb_shinfo(skb)->frags[f].size;
2377 if (frag_size)
2378 count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
2379 ATL1_MAX_TX_BUF_LEN;
2380 }
2381
2382 mss = skb_shinfo(skb)->gso_size;
2383 if (mss) {
2384 if (skb->protocol == htons(ETH_P_IP)) {
2385 proto_hdr_len = (skb_transport_offset(skb) +
2386 tcp_hdrlen(skb));
2387 if (unlikely(proto_hdr_len > len)) {
2388 dev_kfree_skb_any(skb);
2389 return NETDEV_TX_OK;
2390 }
2391 /* need additional TPD ? */
2392 if (proto_hdr_len != len)
2393 count += (len - proto_hdr_len +
2394 ATL1_MAX_TX_BUF_LEN - 1) /
2395 ATL1_MAX_TX_BUF_LEN;
2396 }
2397 }
2398
2399 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
2400 /* not enough descriptors */
2401 netif_stop_queue(netdev);
2402 if (netif_msg_tx_queued(adapter))
2403 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2404 "tx busy\n");
2405 return NETDEV_TX_BUSY;
2406 }
2407
2408 ptpd = ATL1_TPD_DESC(tpd_ring,
2409 (u16) atomic_read(&tpd_ring->next_to_use));
2410 memset(ptpd, 0, sizeof(struct tx_packet_desc));
2411
2412 if (vlan_tx_tag_present(skb)) {
2413 vlan_tag = vlan_tx_tag_get(skb);
2414 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2415 ((vlan_tag >> 9) & 0x8);
2416 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
2417 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) <<
2418 TPD_VLANTAG_SHIFT;
2419 }
2420
2421 tso = atl1_tso(adapter, skb, ptpd);
2422 if (tso < 0) {
2423 dev_kfree_skb_any(skb);
2424 return NETDEV_TX_OK;
2425 }
2426
2427 if (!tso) {
2428 ret_val = atl1_tx_csum(adapter, skb, ptpd);
2429 if (ret_val < 0) {
2430 dev_kfree_skb_any(skb);
2431 return NETDEV_TX_OK;
2432 }
2433 }
2434
2435 atl1_tx_map(adapter, skb, ptpd);
2436 atl1_tx_queue(adapter, count, ptpd);
2437 atl1_update_mailbox(adapter);
2438 mmiowb();
2439 return NETDEV_TX_OK;
2440}
2441
2442/*
2443 * atl1_intr - Interrupt Handler
2444 * @irq: interrupt number
2445 * @data: pointer to a network interface device structure
2446 * @pt_regs: CPU registers structure
2447 */
2448static irqreturn_t atl1_intr(int irq, void *data)
2449{
2450 struct atl1_adapter *adapter = netdev_priv(data);
2451 u32 status;
2452 int max_ints = 10;
2453
2454 status = adapter->cmb.cmb->int_stats;
2455 if (!status)
2456 return IRQ_NONE;
2457
2458 do {
2459 /* clear CMB interrupt status at once */
2460 adapter->cmb.cmb->int_stats = 0;
2461
2462 if (status & ISR_GPHY) /* clear phy status */
2463 atlx_clear_phy_int(adapter);
2464
2465 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2466 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2467
2468 /* check if SMB intr */
2469 if (status & ISR_SMB)
2470 atl1_inc_smb(adapter);
2471
2472 /* check if PCIE PHY Link down */
2473 if (status & ISR_PHY_LINKDOWN) {
2474 if (netif_msg_intr(adapter))
2475 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2476 "pcie phy link down %x\n", status);
2477 if (netif_running(adapter->netdev)) { /* reset MAC */
2478 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2479 schedule_work(&adapter->pcie_dma_to_rst_task);
2480 return IRQ_HANDLED;
2481 }
2482 }
2483
2484 /* check if DMA read/write error ? */
2485 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
2486 if (netif_msg_intr(adapter))
2487 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2488 "pcie DMA r/w error (status = 0x%x)\n",
2489 status);
2490 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2491 schedule_work(&adapter->pcie_dma_to_rst_task);
2492 return IRQ_HANDLED;
2493 }
2494
2495 /* link event */
2496 if (status & ISR_GPHY) {
2497 adapter->soft_stats.tx_carrier_errors++;
2498 atl1_check_for_link(adapter);
2499 }
2500
2501 /* transmit event */
2502 if (status & ISR_CMB_TX)
2503 atl1_intr_tx(adapter);
2504
2505 /* rx exception */
2506 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2507 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2508 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
2509 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2510 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2511 ISR_HOST_RRD_OV))
2512 if (netif_msg_intr(adapter))
2513 dev_printk(KERN_DEBUG,
2514 &adapter->pdev->dev,
2515 "rx exception, ISR = 0x%x\n",
2516 status);
2517 atl1_intr_rx(adapter);
2518 }
2519
2520 if (--max_ints < 0)
2521 break;
2522
2523 } while ((status = adapter->cmb.cmb->int_stats));
2524
2525 /* re-enable Interrupt */
2526 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2527 return IRQ_HANDLED;
2528}
2529
2530
2531/*
2532 * atl1_phy_config - Timer Call-back
2533 * @data: pointer to netdev cast into an unsigned long
2534 */
2535static void atl1_phy_config(unsigned long data)
2536{
2537 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2538 struct atl1_hw *hw = &adapter->hw;
2539 unsigned long flags;
2540
2541 spin_lock_irqsave(&adapter->lock, flags);
2542 adapter->phy_timer_pending = false;
2543 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2544 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2545 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
2546 spin_unlock_irqrestore(&adapter->lock, flags);
2547}
2548
2549/*
2550 * Orphaned vendor comment left intact here:
2551 * <vendor comment>
2552 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2553 * will assert. We do soft reset <0x1400=1> according
2554 * with the SPEC. BUT, it seemes that PCIE or DMA
2555 * state-machine will not be reset. DMAR_TO_INT will
2556 * assert again and again.
2557 * </vendor comment>
2558 */
2559
2560static int atl1_reset(struct atl1_adapter *adapter)
2561{
2562 int ret;
2563 ret = atl1_reset_hw(&adapter->hw);
2564 if (ret)
2565 return ret;
2566 return atl1_init_hw(&adapter->hw);
2567}
2568
2569static s32 atl1_up(struct atl1_adapter *adapter)
2570{
2571 struct net_device *netdev = adapter->netdev;
2572 int err;
2573 int irq_flags = 0;
2574
2575 /* hardware has been reset, we need to reload some things */
2576 atlx_set_multi(netdev);
2577 atl1_init_ring_ptrs(adapter);
2578 atlx_restore_vlan(adapter);
2579 err = atl1_alloc_rx_buffers(adapter);
2580 if (unlikely(!err))
2581 /* no RX BUFFER allocated */
2582 return -ENOMEM;
2583
2584 if (unlikely(atl1_configure(adapter))) {
2585 err = -EIO;
2586 goto err_up;
2587 }
2588
2589 err = pci_enable_msi(adapter->pdev);
2590 if (err) {
2591 if (netif_msg_ifup(adapter))
2592 dev_info(&adapter->pdev->dev,
2593 "Unable to enable MSI: %d\n", err);
2594 irq_flags |= IRQF_SHARED;
2595 }
2596
2597 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags,
2598 netdev->name, netdev);
2599 if (unlikely(err))
2600 goto err_up;
2601
2602 atlx_irq_enable(adapter);
2603 atl1_check_link(adapter);
2604 netif_start_queue(netdev);
2605 return 0;
2606
2607err_up:
2608 pci_disable_msi(adapter->pdev);
2609 /* free rx_buffers */
2610 atl1_clean_rx_ring(adapter);
2611 return err;
2612}
2613
2614static void atl1_down(struct atl1_adapter *adapter)
2615{
2616 struct net_device *netdev = adapter->netdev;
2617
2618 netif_stop_queue(netdev);
2619 del_timer_sync(&adapter->phy_config_timer);
2620 adapter->phy_timer_pending = false;
2621
2622 atlx_irq_disable(adapter);
2623 free_irq(adapter->pdev->irq, netdev);
2624 pci_disable_msi(adapter->pdev);
2625 atl1_reset_hw(&adapter->hw);
2626 adapter->cmb.cmb->int_stats = 0;
2627
2628 adapter->link_speed = SPEED_0;
2629 adapter->link_duplex = -1;
2630 netif_carrier_off(netdev);
2631
2632 atl1_clean_tx_ring(adapter);
2633 atl1_clean_rx_ring(adapter);
2634}
2635
2636static void atl1_tx_timeout_task(struct work_struct *work)
2637{
2638 struct atl1_adapter *adapter =
2639 container_of(work, struct atl1_adapter, tx_timeout_task);
2640 struct net_device *netdev = adapter->netdev;
2641
2642 netif_device_detach(netdev);
2643 atl1_down(adapter);
2644 atl1_up(adapter);
2645 netif_device_attach(netdev);
2646}
2647
2648/*
2649 * atl1_change_mtu - Change the Maximum Transfer Unit
2650 * @netdev: network interface device structure
2651 * @new_mtu: new value for maximum frame size
2652 *
2653 * Returns 0 on success, negative on failure
2654 */
2655static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
2656{
2657 struct atl1_adapter *adapter = netdev_priv(netdev);
2658 int old_mtu = netdev->mtu;
2659 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
2660
2661 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2662 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2663 if (netif_msg_link(adapter))
2664 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2665 return -EINVAL;
2666 }
2667
2668 adapter->hw.max_frame_size = max_frame;
2669 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2670 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2671 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2672
2673 netdev->mtu = new_mtu;
2674 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2675 atl1_down(adapter);
2676 atl1_up(adapter);
2677 }
2678
2679 return 0;
2680}
2681
2682/*
2683 * atl1_open - Called when a network interface is made active
2684 * @netdev: network interface device structure
2685 *
2686 * Returns 0 on success, negative value on failure
2687 *
2688 * The open entry point is called when a network interface is made
2689 * active by the system (IFF_UP). At this point all resources needed
2690 * for transmit and receive operations are allocated, the interrupt
2691 * handler is registered with the OS, the watchdog timer is started,
2692 * and the stack is notified that the interface is ready.
2693 */
2694static int atl1_open(struct net_device *netdev)
2695{
2696 struct atl1_adapter *adapter = netdev_priv(netdev);
2697 int err;
2698
2699 netif_carrier_off(netdev);
2700
2701 /* allocate transmit descriptors */
2702 err = atl1_setup_ring_resources(adapter);
2703 if (err)
2704 return err;
2705
2706 err = atl1_up(adapter);
2707 if (err)
2708 goto err_up;
2709
2710 return 0;
2711
2712err_up:
2713 atl1_reset(adapter);
2714 return err;
2715}
2716
2717/*
2718 * atl1_close - Disables a network interface
2719 * @netdev: network interface device structure
2720 *
2721 * Returns 0, this is not allowed to fail
2722 *
2723 * The close entry point is called when an interface is de-activated
2724 * by the OS. The hardware is still under the drivers control, but
2725 * needs to be disabled. A global MAC reset is issued to stop the
2726 * hardware, and all transmit and receive resources are freed.
2727 */
2728static int atl1_close(struct net_device *netdev)
2729{
2730 struct atl1_adapter *adapter = netdev_priv(netdev);
2731 atl1_down(adapter);
2732 atl1_free_ring_resources(adapter);
2733 return 0;
2734}
2735
2736#ifdef CONFIG_PM
2737static int atl1_suspend(struct device *dev)
2738{
2739 struct pci_dev *pdev = to_pci_dev(dev);
2740 struct net_device *netdev = pci_get_drvdata(pdev);
2741 struct atl1_adapter *adapter = netdev_priv(netdev);
2742 struct atl1_hw *hw = &adapter->hw;
2743 u32 ctrl = 0;
2744 u32 wufc = adapter->wol;
2745 u32 val;
2746 u16 speed;
2747 u16 duplex;
2748
2749 netif_device_detach(netdev);
2750 if (netif_running(netdev))
2751 atl1_down(adapter);
2752
2753 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2754 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2755 val = ctrl & BMSR_LSTATUS;
2756 if (val)
2757 wufc &= ~ATLX_WUFC_LNKC;
2758 if (!wufc)
2759 goto disable_wol;
2760
2761 if (val) {
2762 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2763 if (val) {
2764 if (netif_msg_ifdown(adapter))
2765 dev_printk(KERN_DEBUG, &pdev->dev,
2766 "error getting speed/duplex\n");
2767 goto disable_wol;
2768 }
2769
2770 ctrl = 0;
2771
2772 /* enable magic packet WOL */
2773 if (wufc & ATLX_WUFC_MAG)
2774 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
2775 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2776 ioread32(hw->hw_addr + REG_WOL_CTRL);
2777
2778 /* configure the mac */
2779 ctrl = MAC_CTRL_RX_EN;
2780 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2781 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2782 if (duplex == FULL_DUPLEX)
2783 ctrl |= MAC_CTRL_DUPLX;
2784 ctrl |= (((u32)adapter->hw.preamble_len &
2785 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2786 __atlx_vlan_mode(netdev->features, &ctrl);
2787 if (wufc & ATLX_WUFC_MAG)
2788 ctrl |= MAC_CTRL_BC_EN;
2789 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2790 ioread32(hw->hw_addr + REG_MAC_CTRL);
2791
2792 /* poke the PHY */
2793 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2794 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2795 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2796 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2797 } else {
2798 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2799 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2800 ioread32(hw->hw_addr + REG_WOL_CTRL);
2801 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2802 ioread32(hw->hw_addr + REG_MAC_CTRL);
2803 hw->phy_configured = false;
2804 }
2805
2806 return 0;
2807
2808 disable_wol:
2809 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2810 ioread32(hw->hw_addr + REG_WOL_CTRL);
2811 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2812 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2813 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2814 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2815 hw->phy_configured = false;
2816
2817 return 0;
2818}
2819
2820static int atl1_resume(struct device *dev)
2821{
2822 struct pci_dev *pdev = to_pci_dev(dev);
2823 struct net_device *netdev = pci_get_drvdata(pdev);
2824 struct atl1_adapter *adapter = netdev_priv(netdev);
2825
2826 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2827
2828 atl1_reset_hw(&adapter->hw);
2829
2830 if (netif_running(netdev)) {
2831 adapter->cmb.cmb->int_stats = 0;
2832 atl1_up(adapter);
2833 }
2834 netif_device_attach(netdev);
2835
2836 return 0;
2837}
2838
2839static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume);
2840#define ATL1_PM_OPS (&atl1_pm_ops)
2841
2842#else
2843
2844static int atl1_suspend(struct device *dev) { return 0; }
2845
2846#define ATL1_PM_OPS NULL
2847#endif
2848
2849static void atl1_shutdown(struct pci_dev *pdev)
2850{
2851 struct net_device *netdev = pci_get_drvdata(pdev);
2852 struct atl1_adapter *adapter = netdev_priv(netdev);
2853
2854 atl1_suspend(&pdev->dev);
2855 pci_wake_from_d3(pdev, adapter->wol);
2856 pci_set_power_state(pdev, PCI_D3hot);
2857}
2858
2859#ifdef CONFIG_NET_POLL_CONTROLLER
2860static void atl1_poll_controller(struct net_device *netdev)
2861{
2862 disable_irq(netdev->irq);
2863 atl1_intr(netdev->irq, netdev);
2864 enable_irq(netdev->irq);
2865}
2866#endif
2867
2868static const struct net_device_ops atl1_netdev_ops = {
2869 .ndo_open = atl1_open,
2870 .ndo_stop = atl1_close,
2871 .ndo_start_xmit = atl1_xmit_frame,
2872 .ndo_set_multicast_list = atlx_set_multi,
2873 .ndo_validate_addr = eth_validate_addr,
2874 .ndo_set_mac_address = atl1_set_mac,
2875 .ndo_change_mtu = atl1_change_mtu,
2876 .ndo_fix_features = atlx_fix_features,
2877 .ndo_set_features = atlx_set_features,
2878 .ndo_do_ioctl = atlx_ioctl,
2879 .ndo_tx_timeout = atlx_tx_timeout,
2880#ifdef CONFIG_NET_POLL_CONTROLLER
2881 .ndo_poll_controller = atl1_poll_controller,
2882#endif
2883};
2884
2885/*
2886 * atl1_probe - Device Initialization Routine
2887 * @pdev: PCI device information struct
2888 * @ent: entry in atl1_pci_tbl
2889 *
2890 * Returns 0 on success, negative on failure
2891 *
2892 * atl1_probe initializes an adapter identified by a pci_dev structure.
2893 * The OS initialization, configuring of the adapter private structure,
2894 * and a hardware reset occur.
2895 */
2896static int __devinit atl1_probe(struct pci_dev *pdev,
2897 const struct pci_device_id *ent)
2898{
2899 struct net_device *netdev;
2900 struct atl1_adapter *adapter;
2901 static int cards_found = 0;
2902 int err;
2903
2904 err = pci_enable_device(pdev);
2905 if (err)
2906 return err;
2907
2908 /*
2909 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2910 * shared register for the high 32 bits, so only a single, aligned,
2911 * 4 GB physical address range can be used at a time.
2912 *
2913 * Supporting 64-bit DMA on this hardware is more trouble than it's
2914 * worth. It is far easier to limit to 32-bit DMA than update
2915 * various kernel subsystems to support the mechanics required by a
2916 * fixed-high-32-bit system.
2917 */
2918 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2919 if (err) {
2920 dev_err(&pdev->dev, "no usable DMA configuration\n");
2921 goto err_dma;
2922 }
2923 /*
2924 * Mark all PCI regions associated with PCI device
2925 * pdev as being reserved by owner atl1_driver_name
2926 */
2927 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
2928 if (err)
2929 goto err_request_regions;
2930
2931 /*
2932 * Enables bus-mastering on the device and calls
2933 * pcibios_set_master to do the needed arch specific settings
2934 */
2935 pci_set_master(pdev);
2936
2937 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2938 if (!netdev) {
2939 err = -ENOMEM;
2940 goto err_alloc_etherdev;
2941 }
2942 SET_NETDEV_DEV(netdev, &pdev->dev);
2943
2944 pci_set_drvdata(pdev, netdev);
2945 adapter = netdev_priv(netdev);
2946 adapter->netdev = netdev;
2947 adapter->pdev = pdev;
2948 adapter->hw.back = adapter;
2949 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
2950
2951 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2952 if (!adapter->hw.hw_addr) {
2953 err = -EIO;
2954 goto err_pci_iomap;
2955 }
2956 /* get device revision number */
2957 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
2958 (REG_MASTER_CTRL + 2));
2959 if (netif_msg_probe(adapter))
2960 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
2961
2962 /* set default ring resource counts */
2963 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
2964 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
2965
2966 adapter->mii.dev = netdev;
2967 adapter->mii.mdio_read = mdio_read;
2968 adapter->mii.mdio_write = mdio_write;
2969 adapter->mii.phy_id_mask = 0x1f;
2970 adapter->mii.reg_num_mask = 0x1f;
2971
2972 netdev->netdev_ops = &atl1_netdev_ops;
2973 netdev->watchdog_timeo = 5 * HZ;
2974
2975 netdev->ethtool_ops = &atl1_ethtool_ops;
2976 adapter->bd_number = cards_found;
2977
2978 /* setup the private structure */
2979 err = atl1_sw_init(adapter);
2980 if (err)
2981 goto err_common;
2982
2983 netdev->features = NETIF_F_HW_CSUM;
2984 netdev->features |= NETIF_F_SG;
2985 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2986
2987 netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO |
2988 NETIF_F_HW_VLAN_RX;
2989
2990 /* is this valid? see atl1_setup_mac_ctrl() */
2991 netdev->features |= NETIF_F_RXCSUM;
2992
2993 /*
2994 * patch for some L1 of old version,
2995 * the final version of L1 may not need these
2996 * patches
2997 */
2998 /* atl1_pcie_patch(adapter); */
2999
3000 /* really reset GPHY core */
3001 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3002
3003 /*
3004 * reset the controller to
3005 * put the device in a known good starting state
3006 */
3007 if (atl1_reset_hw(&adapter->hw)) {
3008 err = -EIO;
3009 goto err_common;
3010 }
3011
3012 /* copy the MAC address out of the EEPROM */
3013 atl1_read_mac_addr(&adapter->hw);
3014 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3015
3016 if (!is_valid_ether_addr(netdev->dev_addr)) {
3017 err = -EIO;
3018 goto err_common;
3019 }
3020
3021 atl1_check_options(adapter);
3022
3023 /* pre-init the MAC, and setup link */
3024 err = atl1_init_hw(&adapter->hw);
3025 if (err) {
3026 err = -EIO;
3027 goto err_common;
3028 }
3029
3030 atl1_pcie_patch(adapter);
3031 /* assume we have no link for now */
3032 netif_carrier_off(netdev);
3033
3034 setup_timer(&adapter->phy_config_timer, atl1_phy_config,
3035 (unsigned long)adapter);
3036 adapter->phy_timer_pending = false;
3037
3038 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
3039
3040 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
3041
3042 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
3043
3044 err = register_netdev(netdev);
3045 if (err)
3046 goto err_common;
3047
3048 cards_found++;
3049 atl1_via_workaround(adapter);
3050 return 0;
3051
3052err_common:
3053 pci_iounmap(pdev, adapter->hw.hw_addr);
3054err_pci_iomap:
3055 free_netdev(netdev);
3056err_alloc_etherdev:
3057 pci_release_regions(pdev);
3058err_dma:
3059err_request_regions:
3060 pci_disable_device(pdev);
3061 return err;
3062}
3063
3064/*
3065 * atl1_remove - Device Removal Routine
3066 * @pdev: PCI device information struct
3067 *
3068 * atl1_remove is called by the PCI subsystem to alert the driver
3069 * that it should release a PCI device. The could be caused by a
3070 * Hot-Plug event, or because the driver is going to be removed from
3071 * memory.
3072 */
3073static void __devexit atl1_remove(struct pci_dev *pdev)
3074{
3075 struct net_device *netdev = pci_get_drvdata(pdev);
3076 struct atl1_adapter *adapter;
3077 /* Device not available. Return. */
3078 if (!netdev)
3079 return;
3080
3081 adapter = netdev_priv(netdev);
3082
3083 /*
3084 * Some atl1 boards lack persistent storage for their MAC, and get it
3085 * from the BIOS during POST. If we've been messing with the MAC
3086 * address, we need to save the permanent one.
3087 */
3088 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
3089 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3090 ETH_ALEN);
3091 atl1_set_mac_addr(&adapter->hw);
3092 }
3093
3094 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3095 unregister_netdev(netdev);
3096 pci_iounmap(pdev, adapter->hw.hw_addr);
3097 pci_release_regions(pdev);
3098 free_netdev(netdev);
3099 pci_disable_device(pdev);
3100}
3101
3102static struct pci_driver atl1_driver = {
3103 .name = ATLX_DRIVER_NAME,
3104 .id_table = atl1_pci_tbl,
3105 .probe = atl1_probe,
3106 .remove = __devexit_p(atl1_remove),
3107 .shutdown = atl1_shutdown,
3108 .driver.pm = ATL1_PM_OPS,
3109};
3110
3111/*
3112 * atl1_exit_module - Driver Exit Cleanup Routine
3113 *
3114 * atl1_exit_module is called just before the driver is removed
3115 * from memory.
3116 */
3117static void __exit atl1_exit_module(void)
3118{
3119 pci_unregister_driver(&atl1_driver);
3120}
3121
3122/*
3123 * atl1_init_module - Driver Registration Routine
3124 *
3125 * atl1_init_module is the first routine called when the driver is
3126 * loaded. All it does is register with the PCI subsystem.
3127 */
3128static int __init atl1_init_module(void)
3129{
3130 return pci_register_driver(&atl1_driver);
3131}
3132
3133module_init(atl1_init_module);
3134module_exit(atl1_exit_module);
3135
3136struct atl1_stats {
3137 char stat_string[ETH_GSTRING_LEN];
3138 int sizeof_stat;
3139 int stat_offset;
3140};
3141
3142#define ATL1_STAT(m) \
3143 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3144
3145static struct atl1_stats atl1_gstrings_stats[] = {
3146 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3147 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3148 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3149 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3150 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3151 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
3152 {"multicast", ATL1_STAT(soft_stats.multicast)},
3153 {"collisions", ATL1_STAT(soft_stats.collisions)},
3154 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3155 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3156 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3157 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3158 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3159 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3160 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3161 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3162 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3163 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3164 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3165 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3166 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3167 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3168 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3169 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3170 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3171 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3172 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3173 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3174 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3175};
3176
3177static void atl1_get_ethtool_stats(struct net_device *netdev,
3178 struct ethtool_stats *stats, u64 *data)
3179{
3180 struct atl1_adapter *adapter = netdev_priv(netdev);
3181 int i;
3182 char *p;
3183
3184 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3185 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3186 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3187 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
3188 }
3189
3190}
3191
3192static int atl1_get_sset_count(struct net_device *netdev, int sset)
3193{
3194 switch (sset) {
3195 case ETH_SS_STATS:
3196 return ARRAY_SIZE(atl1_gstrings_stats);
3197 default:
3198 return -EOPNOTSUPP;
3199 }
3200}
3201
3202static int atl1_get_settings(struct net_device *netdev,
3203 struct ethtool_cmd *ecmd)
3204{
3205 struct atl1_adapter *adapter = netdev_priv(netdev);
3206 struct atl1_hw *hw = &adapter->hw;
3207
3208 ecmd->supported = (SUPPORTED_10baseT_Half |
3209 SUPPORTED_10baseT_Full |
3210 SUPPORTED_100baseT_Half |
3211 SUPPORTED_100baseT_Full |
3212 SUPPORTED_1000baseT_Full |
3213 SUPPORTED_Autoneg | SUPPORTED_TP);
3214 ecmd->advertising = ADVERTISED_TP;
3215 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3216 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3217 ecmd->advertising |= ADVERTISED_Autoneg;
3218 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3219 ecmd->advertising |= ADVERTISED_Autoneg;
3220 ecmd->advertising |=
3221 (ADVERTISED_10baseT_Half |
3222 ADVERTISED_10baseT_Full |
3223 ADVERTISED_100baseT_Half |
3224 ADVERTISED_100baseT_Full |
3225 ADVERTISED_1000baseT_Full);
3226 } else
3227 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3228 }
3229 ecmd->port = PORT_TP;
3230 ecmd->phy_address = 0;
3231 ecmd->transceiver = XCVR_INTERNAL;
3232
3233 if (netif_carrier_ok(adapter->netdev)) {
3234 u16 link_speed, link_duplex;
3235 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3236 ethtool_cmd_speed_set(ecmd, link_speed);
3237 if (link_duplex == FULL_DUPLEX)
3238 ecmd->duplex = DUPLEX_FULL;
3239 else
3240 ecmd->duplex = DUPLEX_HALF;
3241 } else {
3242 ethtool_cmd_speed_set(ecmd, -1);
3243 ecmd->duplex = -1;
3244 }
3245 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3246 hw->media_type == MEDIA_TYPE_1000M_FULL)
3247 ecmd->autoneg = AUTONEG_ENABLE;
3248 else
3249 ecmd->autoneg = AUTONEG_DISABLE;
3250
3251 return 0;
3252}
3253
3254static int atl1_set_settings(struct net_device *netdev,
3255 struct ethtool_cmd *ecmd)
3256{
3257 struct atl1_adapter *adapter = netdev_priv(netdev);
3258 struct atl1_hw *hw = &adapter->hw;
3259 u16 phy_data;
3260 int ret_val = 0;
3261 u16 old_media_type = hw->media_type;
3262
3263 if (netif_running(adapter->netdev)) {
3264 if (netif_msg_link(adapter))
3265 dev_dbg(&adapter->pdev->dev,
3266 "ethtool shutting down adapter\n");
3267 atl1_down(adapter);
3268 }
3269
3270 if (ecmd->autoneg == AUTONEG_ENABLE)
3271 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3272 else {
3273 u32 speed = ethtool_cmd_speed(ecmd);
3274 if (speed == SPEED_1000) {
3275 if (ecmd->duplex != DUPLEX_FULL) {
3276 if (netif_msg_link(adapter))
3277 dev_warn(&adapter->pdev->dev,
3278 "1000M half is invalid\n");
3279 ret_val = -EINVAL;
3280 goto exit_sset;
3281 }
3282 hw->media_type = MEDIA_TYPE_1000M_FULL;
3283 } else if (speed == SPEED_100) {
3284 if (ecmd->duplex == DUPLEX_FULL)
3285 hw->media_type = MEDIA_TYPE_100M_FULL;
3286 else
3287 hw->media_type = MEDIA_TYPE_100M_HALF;
3288 } else {
3289 if (ecmd->duplex == DUPLEX_FULL)
3290 hw->media_type = MEDIA_TYPE_10M_FULL;
3291 else
3292 hw->media_type = MEDIA_TYPE_10M_HALF;
3293 }
3294 }
3295 switch (hw->media_type) {
3296 case MEDIA_TYPE_AUTO_SENSOR:
3297 ecmd->advertising =
3298 ADVERTISED_10baseT_Half |
3299 ADVERTISED_10baseT_Full |
3300 ADVERTISED_100baseT_Half |
3301 ADVERTISED_100baseT_Full |
3302 ADVERTISED_1000baseT_Full |
3303 ADVERTISED_Autoneg | ADVERTISED_TP;
3304 break;
3305 case MEDIA_TYPE_1000M_FULL:
3306 ecmd->advertising =
3307 ADVERTISED_1000baseT_Full |
3308 ADVERTISED_Autoneg | ADVERTISED_TP;
3309 break;
3310 default:
3311 ecmd->advertising = 0;
3312 break;
3313 }
3314 if (atl1_phy_setup_autoneg_adv(hw)) {
3315 ret_val = -EINVAL;
3316 if (netif_msg_link(adapter))
3317 dev_warn(&adapter->pdev->dev,
3318 "invalid ethtool speed/duplex setting\n");
3319 goto exit_sset;
3320 }
3321 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3322 hw->media_type == MEDIA_TYPE_1000M_FULL)
3323 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3324 else {
3325 switch (hw->media_type) {
3326 case MEDIA_TYPE_100M_FULL:
3327 phy_data =
3328 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3329 MII_CR_RESET;
3330 break;
3331 case MEDIA_TYPE_100M_HALF:
3332 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3333 break;
3334 case MEDIA_TYPE_10M_FULL:
3335 phy_data =
3336 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3337 break;
3338 default:
3339 /* MEDIA_TYPE_10M_HALF: */
3340 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3341 break;
3342 }
3343 }
3344 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3345exit_sset:
3346 if (ret_val)
3347 hw->media_type = old_media_type;
3348
3349 if (netif_running(adapter->netdev)) {
3350 if (netif_msg_link(adapter))
3351 dev_dbg(&adapter->pdev->dev,
3352 "ethtool starting adapter\n");
3353 atl1_up(adapter);
3354 } else if (!ret_val) {
3355 if (netif_msg_link(adapter))
3356 dev_dbg(&adapter->pdev->dev,
3357 "ethtool resetting adapter\n");
3358 atl1_reset(adapter);
3359 }
3360 return ret_val;
3361}
3362
3363static void atl1_get_drvinfo(struct net_device *netdev,
3364 struct ethtool_drvinfo *drvinfo)
3365{
3366 struct atl1_adapter *adapter = netdev_priv(netdev);
3367
3368 strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3369 strlcpy(drvinfo->version, ATLX_DRIVER_VERSION,
3370 sizeof(drvinfo->version));
3371 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
3372 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
3373 sizeof(drvinfo->bus_info));
3374 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3375}
3376
3377static void atl1_get_wol(struct net_device *netdev,
3378 struct ethtool_wolinfo *wol)
3379{
3380 struct atl1_adapter *adapter = netdev_priv(netdev);
3381
3382 wol->supported = WAKE_MAGIC;
3383 wol->wolopts = 0;
3384 if (adapter->wol & ATLX_WUFC_MAG)
3385 wol->wolopts |= WAKE_MAGIC;
3386}
3387
3388static int atl1_set_wol(struct net_device *netdev,
3389 struct ethtool_wolinfo *wol)
3390{
3391 struct atl1_adapter *adapter = netdev_priv(netdev);
3392
3393 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
3394 WAKE_ARP | WAKE_MAGICSECURE))
3395 return -EOPNOTSUPP;
3396 adapter->wol = 0;
3397 if (wol->wolopts & WAKE_MAGIC)
3398 adapter->wol |= ATLX_WUFC_MAG;
3399
3400 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
3401
3402 return 0;
3403}
3404
3405static u32 atl1_get_msglevel(struct net_device *netdev)
3406{
3407 struct atl1_adapter *adapter = netdev_priv(netdev);
3408 return adapter->msg_enable;
3409}
3410
3411static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3412{
3413 struct atl1_adapter *adapter = netdev_priv(netdev);
3414 adapter->msg_enable = value;
3415}
3416
3417static int atl1_get_regs_len(struct net_device *netdev)
3418{
3419 return ATL1_REG_COUNT * sizeof(u32);
3420}
3421
3422static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3423 void *p)
3424{
3425 struct atl1_adapter *adapter = netdev_priv(netdev);
3426 struct atl1_hw *hw = &adapter->hw;
3427 unsigned int i;
3428 u32 *regbuf = p;
3429
3430 for (i = 0; i < ATL1_REG_COUNT; i++) {
3431 /*
3432 * This switch statement avoids reserved regions
3433 * of register space.
3434 */
3435 switch (i) {
3436 case 6 ... 9:
3437 case 14:
3438 case 29 ... 31:
3439 case 34 ... 63:
3440 case 75 ... 127:
3441 case 136 ... 1023:
3442 case 1027 ... 1087:
3443 case 1091 ... 1151:
3444 case 1194 ... 1195:
3445 case 1200 ... 1201:
3446 case 1206 ... 1213:
3447 case 1216 ... 1279:
3448 case 1290 ... 1311:
3449 case 1323 ... 1343:
3450 case 1358 ... 1359:
3451 case 1368 ... 1375:
3452 case 1378 ... 1383:
3453 case 1388 ... 1391:
3454 case 1393 ... 1395:
3455 case 1402 ... 1403:
3456 case 1410 ... 1471:
3457 case 1522 ... 1535:
3458 /* reserved region; don't read it */
3459 regbuf[i] = 0;
3460 break;
3461 default:
3462 /* unreserved region */
3463 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3464 }
3465 }
3466}
3467
3468static void atl1_get_ringparam(struct net_device *netdev,
3469 struct ethtool_ringparam *ring)
3470{
3471 struct atl1_adapter *adapter = netdev_priv(netdev);
3472 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3473 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
3474
3475 ring->rx_max_pending = ATL1_MAX_RFD;
3476 ring->tx_max_pending = ATL1_MAX_TPD;
3477 ring->rx_mini_max_pending = 0;
3478 ring->rx_jumbo_max_pending = 0;
3479 ring->rx_pending = rxdr->count;
3480 ring->tx_pending = txdr->count;
3481 ring->rx_mini_pending = 0;
3482 ring->rx_jumbo_pending = 0;
3483}
3484
3485static int atl1_set_ringparam(struct net_device *netdev,
3486 struct ethtool_ringparam *ring)
3487{
3488 struct atl1_adapter *adapter = netdev_priv(netdev);
3489 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3490 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3491 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
3492
3493 struct atl1_tpd_ring tpd_old, tpd_new;
3494 struct atl1_rfd_ring rfd_old, rfd_new;
3495 struct atl1_rrd_ring rrd_old, rrd_new;
3496 struct atl1_ring_header rhdr_old, rhdr_new;
3497 struct atl1_smb smb;
3498 struct atl1_cmb cmb;
3499 int err;
3500
3501 tpd_old = adapter->tpd_ring;
3502 rfd_old = adapter->rfd_ring;
3503 rrd_old = adapter->rrd_ring;
3504 rhdr_old = adapter->ring_header;
3505
3506 if (netif_running(adapter->netdev))
3507 atl1_down(adapter);
3508
3509 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3510 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3511 rfdr->count;
3512 rfdr->count = (rfdr->count + 3) & ~3;
3513 rrdr->count = rfdr->count;
3514
3515 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3516 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3517 tpdr->count;
3518 tpdr->count = (tpdr->count + 3) & ~3;
3519
3520 if (netif_running(adapter->netdev)) {
3521 /* try to get new resources before deleting old */
3522 err = atl1_setup_ring_resources(adapter);
3523 if (err)
3524 goto err_setup_ring;
3525
3526 /*
3527 * save the new, restore the old in order to free it,
3528 * then restore the new back again
3529 */
3530
3531 rfd_new = adapter->rfd_ring;
3532 rrd_new = adapter->rrd_ring;
3533 tpd_new = adapter->tpd_ring;
3534 rhdr_new = adapter->ring_header;
3535 adapter->rfd_ring = rfd_old;
3536 adapter->rrd_ring = rrd_old;
3537 adapter->tpd_ring = tpd_old;
3538 adapter->ring_header = rhdr_old;
3539 /*
3540 * Save SMB and CMB, since atl1_free_ring_resources
3541 * will clear them.
3542 */
3543 smb = adapter->smb;
3544 cmb = adapter->cmb;
3545 atl1_free_ring_resources(adapter);
3546 adapter->rfd_ring = rfd_new;
3547 adapter->rrd_ring = rrd_new;
3548 adapter->tpd_ring = tpd_new;
3549 adapter->ring_header = rhdr_new;
3550 adapter->smb = smb;
3551 adapter->cmb = cmb;
3552
3553 err = atl1_up(adapter);
3554 if (err)
3555 return err;
3556 }
3557 return 0;
3558
3559err_setup_ring:
3560 adapter->rfd_ring = rfd_old;
3561 adapter->rrd_ring = rrd_old;
3562 adapter->tpd_ring = tpd_old;
3563 adapter->ring_header = rhdr_old;
3564 atl1_up(adapter);
3565 return err;
3566}
3567
3568static void atl1_get_pauseparam(struct net_device *netdev,
3569 struct ethtool_pauseparam *epause)
3570{
3571 struct atl1_adapter *adapter = netdev_priv(netdev);
3572 struct atl1_hw *hw = &adapter->hw;
3573
3574 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3575 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3576 epause->autoneg = AUTONEG_ENABLE;
3577 } else {
3578 epause->autoneg = AUTONEG_DISABLE;
3579 }
3580 epause->rx_pause = 1;
3581 epause->tx_pause = 1;
3582}
3583
3584static int atl1_set_pauseparam(struct net_device *netdev,
3585 struct ethtool_pauseparam *epause)
3586{
3587 struct atl1_adapter *adapter = netdev_priv(netdev);
3588 struct atl1_hw *hw = &adapter->hw;
3589
3590 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3591 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3592 epause->autoneg = AUTONEG_ENABLE;
3593 } else {
3594 epause->autoneg = AUTONEG_DISABLE;
3595 }
3596
3597 epause->rx_pause = 1;
3598 epause->tx_pause = 1;
3599
3600 return 0;
3601}
3602
3603static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3604 u8 *data)
3605{
3606 u8 *p = data;
3607 int i;
3608
3609 switch (stringset) {
3610 case ETH_SS_STATS:
3611 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3612 memcpy(p, atl1_gstrings_stats[i].stat_string,
3613 ETH_GSTRING_LEN);
3614 p += ETH_GSTRING_LEN;
3615 }
3616 break;
3617 }
3618}
3619
3620static int atl1_nway_reset(struct net_device *netdev)
3621{
3622 struct atl1_adapter *adapter = netdev_priv(netdev);
3623 struct atl1_hw *hw = &adapter->hw;
3624
3625 if (netif_running(netdev)) {
3626 u16 phy_data;
3627 atl1_down(adapter);
3628
3629 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3630 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3631 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3632 } else {
3633 switch (hw->media_type) {
3634 case MEDIA_TYPE_100M_FULL:
3635 phy_data = MII_CR_FULL_DUPLEX |
3636 MII_CR_SPEED_100 | MII_CR_RESET;
3637 break;
3638 case MEDIA_TYPE_100M_HALF:
3639 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3640 break;
3641 case MEDIA_TYPE_10M_FULL:
3642 phy_data = MII_CR_FULL_DUPLEX |
3643 MII_CR_SPEED_10 | MII_CR_RESET;
3644 break;
3645 default:
3646 /* MEDIA_TYPE_10M_HALF */
3647 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3648 }
3649 }
3650 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3651 atl1_up(adapter);
3652 }
3653 return 0;
3654}
3655
3656static const struct ethtool_ops atl1_ethtool_ops = {
3657 .get_settings = atl1_get_settings,
3658 .set_settings = atl1_set_settings,
3659 .get_drvinfo = atl1_get_drvinfo,
3660 .get_wol = atl1_get_wol,
3661 .set_wol = atl1_set_wol,
3662 .get_msglevel = atl1_get_msglevel,
3663 .set_msglevel = atl1_set_msglevel,
3664 .get_regs_len = atl1_get_regs_len,
3665 .get_regs = atl1_get_regs,
3666 .get_ringparam = atl1_get_ringparam,
3667 .set_ringparam = atl1_set_ringparam,
3668 .get_pauseparam = atl1_get_pauseparam,
3669 .set_pauseparam = atl1_set_pauseparam,
3670 .get_link = ethtool_op_get_link,
3671 .get_strings = atl1_get_strings,
3672 .nway_reset = atl1_nway_reset,
3673 .get_ethtool_stats = atl1_get_ethtool_stats,
3674 .get_sset_count = atl1_get_sset_count,
3675};
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
new file mode 100644
index 00000000000..109d6da8be9
--- /dev/null
+++ b/drivers/net/atlx/atl1.h
@@ -0,0 +1,792 @@
1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef ATL1_H
25#define ATL1_H
26
27#include <linux/compiler.h>
28#include <linux/ethtool.h>
29#include <linux/if_vlan.h>
30#include <linux/mii.h>
31#include <linux/module.h>
32#include <linux/skbuff.h>
33#include <linux/spinlock.h>
34#include <linux/timer.h>
35#include <linux/types.h>
36#include <linux/workqueue.h>
37
38#include "atlx.h"
39
40#define ATLX_DRIVER_NAME "atl1"
41
42MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
43
44#define atlx_adapter atl1_adapter
45#define atlx_check_for_link atl1_check_for_link
46#define atlx_check_link atl1_check_link
47#define atlx_hash_mc_addr atl1_hash_mc_addr
48#define atlx_hash_set atl1_hash_set
49#define atlx_hw atl1_hw
50#define atlx_mii_ioctl atl1_mii_ioctl
51#define atlx_read_phy_reg atl1_read_phy_reg
52#define atlx_set_mac atl1_set_mac
53#define atlx_set_mac_addr atl1_set_mac_addr
54
55struct atl1_adapter;
56struct atl1_hw;
57
58/* function prototypes needed by multiple files */
59static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
60static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
61static void atl1_set_mac_addr(struct atl1_hw *hw);
62static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
63 int cmd);
64static u32 atl1_check_link(struct atl1_adapter *adapter);
65
66/* hardware definitions specific to L1 */
67
68/* Block IDLE Status Register */
69#define IDLE_STATUS_RXMAC 0x1
70#define IDLE_STATUS_TXMAC 0x2
71#define IDLE_STATUS_RXQ 0x4
72#define IDLE_STATUS_TXQ 0x8
73#define IDLE_STATUS_DMAR 0x10
74#define IDLE_STATUS_DMAW 0x20
75#define IDLE_STATUS_SMB 0x40
76#define IDLE_STATUS_CMB 0x80
77
78/* MDIO Control Register */
79#define MDIO_WAIT_TIMES 30
80
81/* MAC Control Register */
82#define MAC_CTRL_TX_PAUSE 0x10000
83#define MAC_CTRL_SCNT 0x20000
84#define MAC_CTRL_SRST_TX 0x40000
85#define MAC_CTRL_TX_SIMURST 0x80000
86#define MAC_CTRL_SPEED_SHIFT 20
87#define MAC_CTRL_SPEED_MASK 0x300000
88#define MAC_CTRL_SPEED_1000 0x2
89#define MAC_CTRL_SPEED_10_100 0x1
90#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
91#define MAC_CTRL_TX_HUGE 0x800000
92#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
93#define MAC_CTRL_DBG 0x8000000
94
95/* Wake-On-Lan control register */
96#define WOL_CLK_SWITCH_EN 0x8000
97#define WOL_PT5_EN 0x200000
98#define WOL_PT6_EN 0x400000
99#define WOL_PT5_MATCH 0x8000000
100#define WOL_PT6_MATCH 0x10000000
101
102/* WOL Length ( 2 DWORD ) */
103#define REG_WOL_PATTERN_LEN 0x14A4
104#define WOL_PT_LEN_MASK 0x7F
105#define WOL_PT0_LEN_SHIFT 0
106#define WOL_PT1_LEN_SHIFT 8
107#define WOL_PT2_LEN_SHIFT 16
108#define WOL_PT3_LEN_SHIFT 24
109#define WOL_PT4_LEN_SHIFT 0
110#define WOL_PT5_LEN_SHIFT 8
111#define WOL_PT6_LEN_SHIFT 16
112
113/* Internal SRAM Partition Registers, low 32 bits */
114#define REG_SRAM_RFD_LEN 0x1504
115#define REG_SRAM_RRD_ADDR 0x1508
116#define REG_SRAM_RRD_LEN 0x150C
117#define REG_SRAM_TPD_ADDR 0x1510
118#define REG_SRAM_TPD_LEN 0x1514
119#define REG_SRAM_TRD_ADDR 0x1518
120#define REG_SRAM_TRD_LEN 0x151C
121#define REG_SRAM_RXF_ADDR 0x1520
122#define REG_SRAM_RXF_LEN 0x1524
123#define REG_SRAM_TXF_ADDR 0x1528
124#define REG_SRAM_TXF_LEN 0x152C
125#define REG_SRAM_TCPH_PATH_ADDR 0x1530
126#define SRAM_TCPH_ADDR_MASK 0xFFF
127#define SRAM_TCPH_ADDR_SHIFT 0
128#define SRAM_PATH_ADDR_MASK 0xFFF
129#define SRAM_PATH_ADDR_SHIFT 16
130
131/* Load Ptr Register */
132#define REG_LOAD_PTR 0x1534
133
134/* Descriptor Control registers, low 32 bits */
135#define REG_DESC_RFD_ADDR_LO 0x1544
136#define REG_DESC_RRD_ADDR_LO 0x1548
137#define REG_DESC_TPD_ADDR_LO 0x154C
138#define REG_DESC_CMB_ADDR_LO 0x1550
139#define REG_DESC_SMB_ADDR_LO 0x1554
140#define REG_DESC_RFD_RRD_RING_SIZE 0x1558
141#define DESC_RFD_RING_SIZE_MASK 0x7FF
142#define DESC_RFD_RING_SIZE_SHIFT 0
143#define DESC_RRD_RING_SIZE_MASK 0x7FF
144#define DESC_RRD_RING_SIZE_SHIFT 16
145#define REG_DESC_TPD_RING_SIZE 0x155C
146#define DESC_TPD_RING_SIZE_MASK 0x3FF
147#define DESC_TPD_RING_SIZE_SHIFT 0
148
149/* TXQ Control Register */
150#define REG_TXQ_CTRL 0x1580
151#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
152#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F
153#define TXQ_CTRL_EN 0x20
154#define TXQ_CTRL_ENH_MODE 0x40
155#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
156#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F
157#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
158#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF
159
160/* Jumbo packet Threshold for task offload */
161#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
162#define TX_JUMBO_TASK_TH_MASK 0x7FF
163#define TX_JUMBO_TASK_TH_SHIFT 0
164#define TX_TPD_MIN_IPG_MASK 0x1F
165#define TX_TPD_MIN_IPG_SHIFT 16
166
167/* RXQ Control Register */
168#define REG_RXQ_CTRL 0x15A0
169#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
170#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF
171#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
172#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF
173#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
174#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F
175#define RXQ_CTRL_CUT_THRU_EN 0x40000000
176#define RXQ_CTRL_EN 0x80000000
177
178/* Rx jumbo packet threshold and rrd retirement timer */
179#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
180#define RXQ_JMBOSZ_TH_MASK 0x7FF
181#define RXQ_JMBOSZ_TH_SHIFT 0
182#define RXQ_JMBO_LKAH_MASK 0xF
183#define RXQ_JMBO_LKAH_SHIFT 11
184#define RXQ_RRD_TIMER_MASK 0xFFFF
185#define RXQ_RRD_TIMER_SHIFT 16
186
187/* RFD flow control register */
188#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
189#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
190#define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF
191#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
192#define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF
193
194/* RRD flow control register */
195#define REG_RXQ_RRD_PAUSE_THRESH 0x15AC
196#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
197#define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF
198#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
199#define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF
200
201/* DMA Engine Control Register */
202#define REG_DMA_CTRL 0x15C0
203#define DMA_CTRL_DMAR_IN_ORDER 0x1
204#define DMA_CTRL_DMAR_ENH_ORDER 0x2
205#define DMA_CTRL_DMAR_OUT_ORDER 0x4
206#define DMA_CTRL_RCB_VALUE 0x8
207#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
208#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
209#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
210#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
211#define DMA_CTRL_DMAR_EN 0x400
212#define DMA_CTRL_DMAW_EN 0x800
213
214/* CMB/SMB Control Register */
215#define REG_CSMB_CTRL 0x15D0
216#define CSMB_CTRL_CMB_NOW 1
217#define CSMB_CTRL_SMB_NOW 2
218#define CSMB_CTRL_CMB_EN 4
219#define CSMB_CTRL_SMB_EN 8
220
221/* CMB DMA Write Threshold Register */
222#define REG_CMB_WRITE_TH 0x15D4
223#define CMB_RRD_TH_SHIFT 0
224#define CMB_RRD_TH_MASK 0x7FF
225#define CMB_TPD_TH_SHIFT 16
226#define CMB_TPD_TH_MASK 0x7FF
227
228/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
229#define REG_CMB_WRITE_TIMER 0x15D8
230#define CMB_RX_TM_SHIFT 0
231#define CMB_RX_TM_MASK 0xFFFF
232#define CMB_TX_TM_SHIFT 16
233#define CMB_TX_TM_MASK 0xFFFF
234
235/* Number of packet received since last CMB write */
236#define REG_CMB_RX_PKT_CNT 0x15DC
237
238/* Number of packet transmitted since last CMB write */
239#define REG_CMB_TX_PKT_CNT 0x15E0
240
241/* SMB auto DMA timer register */
242#define REG_SMB_TIMER 0x15E4
243
244/* Mailbox Register */
245#define REG_MAILBOX 0x15F0
246#define MB_RFD_PROD_INDX_SHIFT 0
247#define MB_RFD_PROD_INDX_MASK 0x7FF
248#define MB_RRD_CONS_INDX_SHIFT 11
249#define MB_RRD_CONS_INDX_MASK 0x7FF
250#define MB_TPD_PROD_INDX_SHIFT 22
251#define MB_TPD_PROD_INDX_MASK 0x3FF
252
253/* Interrupt Status Register */
254#define ISR_SMB 0x1
255#define ISR_TIMER 0x2
256#define ISR_MANUAL 0x4
257#define ISR_RXF_OV 0x8
258#define ISR_RFD_UNRUN 0x10
259#define ISR_RRD_OV 0x20
260#define ISR_TXF_UNRUN 0x40
261#define ISR_LINK 0x80
262#define ISR_HOST_RFD_UNRUN 0x100
263#define ISR_HOST_RRD_OV 0x200
264#define ISR_DMAR_TO_RST 0x400
265#define ISR_DMAW_TO_RST 0x800
266#define ISR_GPHY 0x1000
267#define ISR_RX_PKT 0x10000
268#define ISR_TX_PKT 0x20000
269#define ISR_TX_DMA 0x40000
270#define ISR_RX_DMA 0x80000
271#define ISR_CMB_RX 0x100000
272#define ISR_CMB_TX 0x200000
273#define ISR_MAC_RX 0x400000
274#define ISR_MAC_TX 0x800000
275#define ISR_DIS_SMB 0x20000000
276#define ISR_DIS_DMA 0x40000000
277
278/* Normal Interrupt mask */
279#define IMR_NORMAL_MASK (\
280 ISR_SMB |\
281 ISR_GPHY |\
282 ISR_PHY_LINKDOWN|\
283 ISR_DMAR_TO_RST |\
284 ISR_DMAW_TO_RST |\
285 ISR_CMB_TX |\
286 ISR_CMB_RX)
287
288/* Debug Interrupt Mask (enable all interrupt) */
289#define IMR_DEBUG_MASK (\
290 ISR_SMB |\
291 ISR_TIMER |\
292 ISR_MANUAL |\
293 ISR_RXF_OV |\
294 ISR_RFD_UNRUN |\
295 ISR_RRD_OV |\
296 ISR_TXF_UNRUN |\
297 ISR_LINK |\
298 ISR_CMB_TX |\
299 ISR_CMB_RX |\
300 ISR_RX_PKT |\
301 ISR_TX_PKT |\
302 ISR_MAC_RX |\
303 ISR_MAC_TX)
304
305#define MEDIA_TYPE_1000M_FULL 1
306#define MEDIA_TYPE_100M_FULL 2
307#define MEDIA_TYPE_100M_HALF 3
308#define MEDIA_TYPE_10M_FULL 4
309#define MEDIA_TYPE_10M_HALF 5
310
311#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */
312
313#define MAX_JUMBO_FRAME_SIZE 10240
314
315#define ATL1_EEDUMP_LEN 48
316
317/* Statistics counters collected by the MAC */
318struct stats_msg_block {
319 /* rx */
320 u32 rx_ok; /* good RX packets */
321 u32 rx_bcast; /* good RX broadcast packets */
322 u32 rx_mcast; /* good RX multicast packets */
323 u32 rx_pause; /* RX pause frames */
324 u32 rx_ctrl; /* RX control packets other than pause frames */
325 u32 rx_fcs_err; /* RX packets with bad FCS */
326 u32 rx_len_err; /* RX packets with length != actual size */
327 u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */
328 u32 rx_runt; /* RX packets < 64 bytes with good FCS */
329 u32 rx_frag; /* RX packets < 64 bytes with bad FCS */
330 u32 rx_sz_64; /* 64 byte RX packets */
331 u32 rx_sz_65_127;
332 u32 rx_sz_128_255;
333 u32 rx_sz_256_511;
334 u32 rx_sz_512_1023;
335 u32 rx_sz_1024_1518;
336 u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */
337 u32 rx_sz_ov; /* truncated RX packets > MTU */
338 u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */
339 u32 rx_rrd_ov; /* frames dropped due to RRD overflow */
340 u32 rx_align_err; /* alignment errors */
341 u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */
342 u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */
343 u32 rx_err_addr; /* packets dropped due to address filtering */
344
345 /* tx */
346 u32 tx_ok; /* good TX packets */
347 u32 tx_bcast; /* good TX broadcast packets */
348 u32 tx_mcast; /* good TX multicast packets */
349 u32 tx_pause; /* TX pause frames */
350 u32 tx_exc_defer; /* TX packets deferred excessively */
351 u32 tx_ctrl; /* TX control frames, excluding pause frames */
352 u32 tx_defer; /* TX packets deferred */
353 u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
354 u32 tx_sz_64; /* 64 byte TX packets */
355 u32 tx_sz_65_127;
356 u32 tx_sz_128_255;
357 u32 tx_sz_256_511;
358 u32 tx_sz_512_1023;
359 u32 tx_sz_1024_1518;
360 u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */
361 u32 tx_1_col; /* packets TX after a single collision */
362 u32 tx_2_col; /* packets TX after multiple collisions */
363 u32 tx_late_col; /* TX packets with late collisions */
364 u32 tx_abort_col; /* TX packets aborted w/excessive collisions */
365 u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun
366 * or TRD FIFO underrun */
367 u32 tx_rd_eop; /* reads beyond the EOP into the next frame
368 * when TRD was not written timely */
369 u32 tx_len_err; /* TX packets where length != actual size */
370 u32 tx_trunc; /* TX packets truncated due to size > MTU */
371 u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */
372 u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */
373 u32 smb_updated; /* 1: SMB Updated. This is used by software to
374 * indicate the statistics update. Software
375 * should clear this bit after retrieving the
376 * statistics information. */
377};
378
379/* Coalescing Message Block */
380struct coals_msg_block {
381 u32 int_stats; /* interrupt status */
382 u16 rrd_prod_idx; /* TRD Producer Index. */
383 u16 rfd_cons_idx; /* RFD Consumer Index. */
384 u16 update; /* Selene sets this bit every time it DMAs the
385 * CMB to host memory. Software should clear
386 * this bit when CMB info is processed. */
387 u16 tpd_cons_idx; /* TPD Consumer Index. */
388};
389
390/* RRD descriptor */
391struct rx_return_desc {
392 u8 num_buf; /* Number of RFD buffers used by the received packet */
393 u8 resved;
394 u16 buf_indx; /* RFD Index of the first buffer */
395 union {
396 u32 valid;
397 struct {
398 u16 rx_chksum;
399 u16 pkt_size;
400 } xsum_sz;
401 } xsz;
402
403 u16 pkt_flg; /* Packet flags */
404 u16 err_flg; /* Error flags */
405 u16 resved2;
406 u16 vlan_tag; /* VLAN TAG */
407};
408
409#define PACKET_FLAG_ETH_TYPE 0x0080
410#define PACKET_FLAG_VLAN_INS 0x0100
411#define PACKET_FLAG_ERR 0x0200
412#define PACKET_FLAG_IPV4 0x0400
413#define PACKET_FLAG_UDP 0x0800
414#define PACKET_FLAG_TCP 0x1000
415#define PACKET_FLAG_BCAST 0x2000
416#define PACKET_FLAG_MCAST 0x4000
417#define PACKET_FLAG_PAUSE 0x8000
418
419#define ERR_FLAG_CRC 0x0001
420#define ERR_FLAG_CODE 0x0002
421#define ERR_FLAG_DRIBBLE 0x0004
422#define ERR_FLAG_RUNT 0x0008
423#define ERR_FLAG_OV 0x0010
424#define ERR_FLAG_TRUNC 0x0020
425#define ERR_FLAG_IP_CHKSUM 0x0040
426#define ERR_FLAG_L4_CHKSUM 0x0080
427#define ERR_FLAG_LEN 0x0100
428#define ERR_FLAG_DES_ADDR 0x0200
429
430/* RFD descriptor */
431struct rx_free_desc {
432 __le64 buffer_addr; /* Address of the descriptor's data buffer */
433 __le16 buf_len; /* Size of the receive buffer in host memory */
434 u16 coalese; /* Update consumer index to host after the
435 * reception of this frame */
436 /* __packed is required */
437} __packed;
438
439/*
440 * The L1 transmit packet descriptor is comprised of four 32-bit words.
441 *
442 * 31 0
443 * +---------------------------------------+
444 * | Word 0: Buffer addr lo |
445 * +---------------------------------------+
446 * | Word 1: Buffer addr hi |
447 * +---------------------------------------+
448 * | Word 2 |
449 * +---------------------------------------+
450 * | Word 3 |
451 * +---------------------------------------+
452 *
453 * Words 0 and 1 combine to form a 64-bit buffer address.
454 *
455 * Word 2 is self explanatory in the #define block below.
456 *
457 * Word 3 has two forms, depending upon the state of bits 3 and 4.
458 * If bits 3 and 4 are both zero, then bits 14:31 are unused by the
459 * hardware. Otherwise, if either bit 3 or 4 is set, the definition
460 * of bits 14:31 vary according to the following depiction.
461 *
462 * 0 End of packet 0 End of packet
463 * 1 Coalesce 1 Coalesce
464 * 2 Insert VLAN tag 2 Insert VLAN tag
465 * 3 Custom csum enable = 0 3 Custom csum enable = 1
466 * 4 Segment enable = 1 4 Segment enable = 0
467 * 5 Generate IP checksum 5 Generate IP checksum
468 * 6 Generate TCP checksum 6 Generate TCP checksum
469 * 7 Generate UDP checksum 7 Generate UDP checksum
470 * 8 VLAN tagged 8 VLAN tagged
471 * 9 Ethernet frame type 9 Ethernet frame type
472 * 10-+ 10-+
473 * 11 | IP hdr length (10:13) 11 | IP hdr length (10:13)
474 * 12 | (num 32-bit words) 12 | (num 32-bit words)
475 * 13-+ 13-+
476 * 14-+ 14 Unused
477 * 15 | TCP hdr length (14:17) 15 Unused
478 * 16 | (num 32-bit words) 16-+
479 * 17-+ 17 |
480 * 18 Header TPD flag 18 |
481 * 19-+ 19 | Payload offset
482 * 20 | 20 | (16:23)
483 * 21 | 21 |
484 * 22 | 22 |
485 * 23 | 23-+
486 * 24 | 24-+
487 * 25 | MSS (19:31) 25 |
488 * 26 | 26 |
489 * 27 | 27 | Custom csum offset
490 * 28 | 28 | (24:31)
491 * 29 | 29 |
492 * 30 | 30 |
493 * 31-+ 31-+
494 */
495
496/* tpd word 2 */
497#define TPD_BUFLEN_MASK 0x3FFF
498#define TPD_BUFLEN_SHIFT 0
499#define TPD_DMAINT_MASK 0x0001
500#define TPD_DMAINT_SHIFT 14
501#define TPD_PKTNT_MASK 0x0001
502#define TPD_PKTINT_SHIFT 15
503#define TPD_VLANTAG_MASK 0xFFFF
504#define TPD_VLANTAG_SHIFT 16
505
506/* tpd word 3 bits 0:13 */
507#define TPD_EOP_MASK 0x0001
508#define TPD_EOP_SHIFT 0
509#define TPD_COALESCE_MASK 0x0001
510#define TPD_COALESCE_SHIFT 1
511#define TPD_INS_VL_TAG_MASK 0x0001
512#define TPD_INS_VL_TAG_SHIFT 2
513#define TPD_CUST_CSUM_EN_MASK 0x0001
514#define TPD_CUST_CSUM_EN_SHIFT 3
515#define TPD_SEGMENT_EN_MASK 0x0001
516#define TPD_SEGMENT_EN_SHIFT 4
517#define TPD_IP_CSUM_MASK 0x0001
518#define TPD_IP_CSUM_SHIFT 5
519#define TPD_TCP_CSUM_MASK 0x0001
520#define TPD_TCP_CSUM_SHIFT 6
521#define TPD_UDP_CSUM_MASK 0x0001
522#define TPD_UDP_CSUM_SHIFT 7
523#define TPD_VL_TAGGED_MASK 0x0001
524#define TPD_VL_TAGGED_SHIFT 8
525#define TPD_ETHTYPE_MASK 0x0001
526#define TPD_ETHTYPE_SHIFT 9
527#define TPD_IPHL_MASK 0x000F
528#define TPD_IPHL_SHIFT 10
529
530/* tpd word 3 bits 14:31 if segment enabled */
531#define TPD_TCPHDRLEN_MASK 0x000F
532#define TPD_TCPHDRLEN_SHIFT 14
533#define TPD_HDRFLAG_MASK 0x0001
534#define TPD_HDRFLAG_SHIFT 18
535#define TPD_MSS_MASK 0x1FFF
536#define TPD_MSS_SHIFT 19
537
538/* tpd word 3 bits 16:31 if custom csum enabled */
539#define TPD_PLOADOFFSET_MASK 0x00FF
540#define TPD_PLOADOFFSET_SHIFT 16
541#define TPD_CCSUMOFFSET_MASK 0x00FF
542#define TPD_CCSUMOFFSET_SHIFT 24
543
544struct tx_packet_desc {
545 __le64 buffer_addr;
546 __le32 word2;
547 __le32 word3;
548};
549
550/* DMA Order Settings */
551enum atl1_dma_order {
552 atl1_dma_ord_in = 1,
553 atl1_dma_ord_enh = 2,
554 atl1_dma_ord_out = 4
555};
556
557enum atl1_dma_rcb {
558 atl1_rcb_64 = 0,
559 atl1_rcb_128 = 1
560};
561
562enum atl1_dma_req_block {
563 atl1_dma_req_128 = 0,
564 atl1_dma_req_256 = 1,
565 atl1_dma_req_512 = 2,
566 atl1_dma_req_1024 = 3,
567 atl1_dma_req_2048 = 4,
568 atl1_dma_req_4096 = 5
569};
570
571#define ATL1_MAX_INTR 3
572#define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
573
574#define ATL1_DEFAULT_TPD 256
575#define ATL1_MAX_TPD 1024
576#define ATL1_MIN_TPD 64
577#define ATL1_DEFAULT_RFD 512
578#define ATL1_MIN_RFD 128
579#define ATL1_MAX_RFD 2048
580#define ATL1_REG_COUNT 1538
581
582#define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
583#define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
584#define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
585#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
586
587/*
588 * atl1_ring_header represents a single, contiguous block of DMA space
589 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
590 * message blocks (cmb, smb) described below
591 */
592struct atl1_ring_header {
593 void *desc; /* virtual address */
594 dma_addr_t dma; /* physical address*/
595 unsigned int size; /* length in bytes */
596};
597
598/*
599 * atl1_buffer is wrapper around a pointer to a socket buffer
600 * so a DMA handle can be stored along with the skb
601 */
602struct atl1_buffer {
603 struct sk_buff *skb; /* socket buffer */
604 u16 length; /* rx buffer length */
605 u16 alloced; /* 1 if skb allocated */
606 dma_addr_t dma;
607};
608
609/* transmit packet descriptor (tpd) ring */
610struct atl1_tpd_ring {
611 void *desc; /* descriptor ring virtual address */
612 dma_addr_t dma; /* descriptor ring physical address */
613 u16 size; /* descriptor ring length in bytes */
614 u16 count; /* number of descriptors in the ring */
615 u16 hw_idx; /* hardware index */
616 atomic_t next_to_clean;
617 atomic_t next_to_use;
618 struct atl1_buffer *buffer_info;
619};
620
621/* receive free descriptor (rfd) ring */
622struct atl1_rfd_ring {
623 void *desc; /* descriptor ring virtual address */
624 dma_addr_t dma; /* descriptor ring physical address */
625 u16 size; /* descriptor ring length in bytes */
626 u16 count; /* number of descriptors in the ring */
627 atomic_t next_to_use;
628 u16 next_to_clean;
629 struct atl1_buffer *buffer_info;
630};
631
632/* receive return descriptor (rrd) ring */
633struct atl1_rrd_ring {
634 void *desc; /* descriptor ring virtual address */
635 dma_addr_t dma; /* descriptor ring physical address */
636 unsigned int size; /* descriptor ring length in bytes */
637 u16 count; /* number of descriptors in the ring */
638 u16 next_to_use;
639 atomic_t next_to_clean;
640};
641
642/* coalescing message block (cmb) */
643struct atl1_cmb {
644 struct coals_msg_block *cmb;
645 dma_addr_t dma;
646};
647
648/* statistics message block (smb) */
649struct atl1_smb {
650 struct stats_msg_block *smb;
651 dma_addr_t dma;
652};
653
654/* Statistics counters */
655struct atl1_sft_stats {
656 u64 rx_packets;
657 u64 tx_packets;
658 u64 rx_bytes;
659 u64 tx_bytes;
660 u64 multicast;
661 u64 collisions;
662 u64 rx_errors;
663 u64 rx_length_errors;
664 u64 rx_crc_errors;
665 u64 rx_frame_errors;
666 u64 rx_fifo_errors;
667 u64 rx_missed_errors;
668 u64 tx_errors;
669 u64 tx_fifo_errors;
670 u64 tx_aborted_errors;
671 u64 tx_window_errors;
672 u64 tx_carrier_errors;
673 u64 tx_pause; /* TX pause frames */
674 u64 excecol; /* TX packets w/ excessive collisions */
675 u64 deffer; /* TX packets deferred */
676 u64 scc; /* packets TX after a single collision */
677 u64 mcc; /* packets TX after multiple collisions */
678 u64 latecol; /* TX packets w/ late collisions */
679 u64 tx_underun; /* TX packets aborted due to TX FIFO underrun
680 * or TRD FIFO underrun */
681 u64 tx_trunc; /* TX packets truncated due to size > MTU */
682 u64 rx_pause; /* num Pause packets received. */
683 u64 rx_rrd_ov;
684 u64 rx_trunc;
685};
686
687/* hardware structure */
688struct atl1_hw {
689 u8 __iomem *hw_addr;
690 struct atl1_adapter *back;
691 enum atl1_dma_order dma_ord;
692 enum atl1_dma_rcb rcb_value;
693 enum atl1_dma_req_block dmar_block;
694 enum atl1_dma_req_block dmaw_block;
695 u8 preamble_len;
696 u8 max_retry;
697 u8 jam_ipg; /* IPG to start JAM for collision based flow
698 * control in half-duplex mode. In units of
699 * 8-bit time */
700 u8 ipgt; /* Desired back to back inter-packet gap.
701 * The default is 96-bit time */
702 u8 min_ifg; /* Minimum number of IFG to enforce in between
703 * receive frames. Frame gap below such IFP
704 * is dropped */
705 u8 ipgr1; /* 64bit Carrier-Sense window */
706 u8 ipgr2; /* 96-bit IPG window */
707 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned
708 * burst. Each TPD is 16 bytes long */
709 u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned
710 * burst. Each RFD is 12 bytes long */
711 u8 rfd_fetch_gap;
712 u8 rrd_burst; /* Threshold number of RRDs that can be retired
713 * in a burst. Each RRD is 16 bytes long */
714 u8 tpd_fetch_th;
715 u8 tpd_fetch_gap;
716 u16 tx_jumbo_task_th;
717 u16 txf_burst; /* Number of data bytes to read in a cache-
718 * aligned burst. Each SRAM entry is 8 bytes */
719 u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN
720 * packets should add 4 bytes */
721 u16 rx_jumbo_lkah;
722 u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after
723 * every 512ns passes. */
724 u16 lcol; /* Collision Window */
725
726 u16 cmb_tpd;
727 u16 cmb_rrd;
728 u16 cmb_rx_timer;
729 u16 cmb_tx_timer;
730 u32 smb_timer;
731 u16 media_type;
732 u16 autoneg_advertised;
733
734 u16 mii_autoneg_adv_reg;
735 u16 mii_1000t_ctrl_reg;
736
737 u32 max_frame_size;
738 u32 min_frame_size;
739
740 u16 dev_rev;
741
742 /* spi flash */
743 u8 flash_vendor;
744
745 u8 mac_addr[ETH_ALEN];
746 u8 perm_mac_addr[ETH_ALEN];
747
748 bool phy_configured;
749};
750
751struct atl1_adapter {
752 struct net_device *netdev;
753 struct pci_dev *pdev;
754
755 struct atl1_sft_stats soft_stats;
756 u32 rx_buffer_len;
757 u32 wol;
758 u16 link_speed;
759 u16 link_duplex;
760 spinlock_t lock;
761 struct work_struct tx_timeout_task;
762 struct work_struct link_chg_task;
763 struct work_struct pcie_dma_to_rst_task;
764
765 struct timer_list phy_config_timer;
766 bool phy_timer_pending;
767
768 /* all descriptor rings' memory */
769 struct atl1_ring_header ring_header;
770
771 /* TX */
772 struct atl1_tpd_ring tpd_ring;
773 spinlock_t mb_lock;
774
775 /* RX */
776 struct atl1_rfd_ring rfd_ring;
777 struct atl1_rrd_ring rrd_ring;
778 u64 hw_csum_err;
779 u64 hw_csum_good;
780 u32 msg_enable;
781 u16 imt; /* interrupt moderator timer (2us resolution) */
782 u16 ict; /* interrupt clear timer (2us resolution */
783 struct mii_if_info mii; /* MII interface info */
784
785 u32 bd_number; /* board number */
786 bool pci_using_64;
787 struct atl1_hw hw;
788 struct atl1_smb smb;
789 struct atl1_cmb cmb;
790};
791
792#endif /* ATL1_H */
diff --git a/drivers/net/atlx/atl2.c b/drivers/net/atlx/atl2.c
new file mode 100644
index 00000000000..d4f7dda3972
--- /dev/null
+++ b/drivers/net/atlx/atl2.c
@@ -0,0 +1,3119 @@
1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#include <linux/atomic.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
42#include <linux/slab.h>
43#include <linux/spinlock.h>
44#include <linux/string.h>
45#include <linux/tcp.h>
46#include <linux/timer.h>
47#include <linux/types.h>
48#include <linux/workqueue.h>
49
50#include "atl2.h"
51
52#define ATL2_DRV_VERSION "2.2.3"
53
54static const char atl2_driver_name[] = "atl2";
55static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
56static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
57static const char atl2_driver_version[] = ATL2_DRV_VERSION;
58
59MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
60MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
61MODULE_LICENSE("GPL");
62MODULE_VERSION(ATL2_DRV_VERSION);
63
64/*
65 * atl2_pci_tbl - PCI Device ID Table
66 */
67static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = {
68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
69 /* required last entry */
70 {0,}
71};
72MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
73
74static void atl2_set_ethtool_ops(struct net_device *netdev);
75
76static void atl2_check_options(struct atl2_adapter *adapter);
77
78/*
79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
80 * @adapter: board private structure to initialize
81 *
82 * atl2_sw_init initializes the Adapter private data structure.
83 * Fields are initialized based on PCI device information and
84 * OS network device settings (MTU size).
85 */
86static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
87{
88 struct atl2_hw *hw = &adapter->hw;
89 struct pci_dev *pdev = adapter->pdev;
90
91 /* PCI config space info */
92 hw->vendor_id = pdev->vendor;
93 hw->device_id = pdev->device;
94 hw->subsystem_vendor_id = pdev->subsystem_vendor;
95 hw->subsystem_id = pdev->subsystem_device;
96 hw->revision_id = pdev->revision;
97
98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
99
100 adapter->wol = 0;
101 adapter->ict = 50000; /* ~100ms */
102 adapter->link_speed = SPEED_0; /* hardware init */
103 adapter->link_duplex = FULL_DUPLEX;
104
105 hw->phy_configured = false;
106 hw->preamble_len = 7;
107 hw->ipgt = 0x60;
108 hw->min_ifg = 0x50;
109 hw->ipgr1 = 0x40;
110 hw->ipgr2 = 0x60;
111 hw->retry_buf = 2;
112 hw->max_retry = 0xf;
113 hw->lcol = 0x37;
114 hw->jam_ipg = 7;
115 hw->fc_rxd_hi = 0;
116 hw->fc_rxd_lo = 0;
117 hw->max_frame_size = adapter->netdev->mtu;
118
119 spin_lock_init(&adapter->stats_lock);
120
121 set_bit(__ATL2_DOWN, &adapter->flags);
122
123 return 0;
124}
125
126/*
127 * atl2_set_multi - Multicast and Promiscuous mode set
128 * @netdev: network interface device structure
129 *
130 * The set_multi entry point is called whenever the multicast address
131 * list or the network interface flags are updated. This routine is
132 * responsible for configuring the hardware for proper multicast,
133 * promiscuous mode, and all-multi behavior.
134 */
135static void atl2_set_multi(struct net_device *netdev)
136{
137 struct atl2_adapter *adapter = netdev_priv(netdev);
138 struct atl2_hw *hw = &adapter->hw;
139 struct netdev_hw_addr *ha;
140 u32 rctl;
141 u32 hash_value;
142
143 /* Check for Promiscuous and All Multicast modes */
144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
145
146 if (netdev->flags & IFF_PROMISC) {
147 rctl |= MAC_CTRL_PROMIS_EN;
148 } else if (netdev->flags & IFF_ALLMULTI) {
149 rctl |= MAC_CTRL_MC_ALL_EN;
150 rctl &= ~MAC_CTRL_PROMIS_EN;
151 } else
152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
153
154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
155
156 /* clear the old settings from the multicast hash table */
157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
159
160 /* comoute mc addresses' hash value ,and put it into hash table */
161 netdev_for_each_mc_addr(ha, netdev) {
162 hash_value = atl2_hash_mc_addr(hw, ha->addr);
163 atl2_hash_set(hw, hash_value);
164 }
165}
166
167static void init_ring_ptrs(struct atl2_adapter *adapter)
168{
169 /* Read / Write Ptr Initialize: */
170 adapter->txd_write_ptr = 0;
171 atomic_set(&adapter->txd_read_ptr, 0);
172
173 adapter->rxd_read_ptr = 0;
174 adapter->rxd_write_ptr = 0;
175
176 atomic_set(&adapter->txs_write_ptr, 0);
177 adapter->txs_next_clear = 0;
178}
179
180/*
181 * atl2_configure - Configure Transmit&Receive Unit after Reset
182 * @adapter: board private structure
183 *
184 * Configure the Tx /Rx unit of the MAC after a reset.
185 */
186static int atl2_configure(struct atl2_adapter *adapter)
187{
188 struct atl2_hw *hw = &adapter->hw;
189 u32 value;
190
191 /* clear interrupt status */
192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
193
194 /* set MAC Address */
195 value = (((u32)hw->mac_addr[2]) << 24) |
196 (((u32)hw->mac_addr[3]) << 16) |
197 (((u32)hw->mac_addr[4]) << 8) |
198 (((u32)hw->mac_addr[5]));
199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
200 value = (((u32)hw->mac_addr[0]) << 8) |
201 (((u32)hw->mac_addr[1]));
202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
203
204 /* HI base address */
205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
207
208 /* LO base address */
209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
215
216 /* element count */
217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
220
221 /* config Internal SRAM */
222/*
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
225*/
226
227 /* config IPG/IFG */
228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
229 MAC_IPG_IFG_IPGT_SHIFT) |
230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
231 MAC_IPG_IFG_MIFG_SHIFT) |
232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
233 MAC_IPG_IFG_IPGR1_SHIFT)|
234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
235 MAC_IPG_IFG_IPGR2_SHIFT);
236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
237
238 /* config Half-Duplex Control */
239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
247
248 /* set Interrupt Moderator Timer */
249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
251
252 /* set Interrupt Clear Timer */
253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
254
255 /* set MTU */
256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
258
259 /* 1590 */
260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
261
262 /* flow control */
263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
265
266 /* Init mailbox */
267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
269
270 /* enable DMA read/write */
271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
273
274 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
275 if ((value & ISR_PHY_LINKDOWN) != 0)
276 value = 1; /* config failed */
277 else
278 value = 0;
279
280 /* clear all interrupt status */
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
283 return value;
284}
285
286/*
287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
288 * @adapter: board private structure
289 *
290 * Return 0 on success, negative on failure
291 */
292static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
293{
294 struct pci_dev *pdev = adapter->pdev;
295 int size;
296 u8 offset = 0;
297
298 /* real ring DMA buffer */
299 adapter->ring_size = size =
300 adapter->txd_ring_size * 1 + 7 + /* dword align */
301 adapter->txs_ring_size * 4 + 7 + /* dword align */
302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
303
304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
305 &adapter->ring_dma);
306 if (!adapter->ring_vir_addr)
307 return -ENOMEM;
308 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
309
310 /* Init TXD Ring */
311 adapter->txd_dma = adapter->ring_dma ;
312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
313 adapter->txd_dma += offset;
314 adapter->txd_ring = adapter->ring_vir_addr + offset;
315
316 /* Init TXS Ring */
317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
319 adapter->txs_dma += offset;
320 adapter->txs_ring = (struct tx_pkt_status *)
321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
322
323 /* Init RXD Ring */
324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
325 offset = (adapter->rxd_dma & 127) ?
326 (128 - (adapter->rxd_dma & 127)) : 0;
327 if (offset > 7)
328 offset -= 8;
329 else
330 offset += (128 - 8);
331
332 adapter->rxd_dma += offset;
333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
334 (adapter->txs_ring_size * 4 + offset));
335
336/*
337 * Read / Write Ptr Initialize:
338 * init_ring_ptrs(adapter);
339 */
340 return 0;
341}
342
343/*
344 * atl2_irq_enable - Enable default interrupt generation settings
345 * @adapter: board private structure
346 */
347static inline void atl2_irq_enable(struct atl2_adapter *adapter)
348{
349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
350 ATL2_WRITE_FLUSH(&adapter->hw);
351}
352
353/*
354 * atl2_irq_disable - Mask off interrupt generation on the NIC
355 * @adapter: board private structure
356 */
357static inline void atl2_irq_disable(struct atl2_adapter *adapter)
358{
359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
360 ATL2_WRITE_FLUSH(&adapter->hw);
361 synchronize_irq(adapter->pdev->irq);
362}
363
364static void __atl2_vlan_mode(u32 features, u32 *ctrl)
365{
366 if (features & NETIF_F_HW_VLAN_RX) {
367 /* enable VLAN tag insert/strip */
368 *ctrl |= MAC_CTRL_RMV_VLAN;
369 } else {
370 /* disable VLAN tag insert/strip */
371 *ctrl &= ~MAC_CTRL_RMV_VLAN;
372 }
373}
374
375static void atl2_vlan_mode(struct net_device *netdev, u32 features)
376{
377 struct atl2_adapter *adapter = netdev_priv(netdev);
378 u32 ctrl;
379
380 atl2_irq_disable(adapter);
381
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
383 __atl2_vlan_mode(features, &ctrl);
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
385
386 atl2_irq_enable(adapter);
387}
388
389static void atl2_restore_vlan(struct atl2_adapter *adapter)
390{
391 atl2_vlan_mode(adapter->netdev, adapter->netdev->features);
392}
393
394static u32 atl2_fix_features(struct net_device *netdev, u32 features)
395{
396 /*
397 * Since there is no support for separate rx/tx vlan accel
398 * enable/disable make sure tx flag is always in same state as rx.
399 */
400 if (features & NETIF_F_HW_VLAN_RX)
401 features |= NETIF_F_HW_VLAN_TX;
402 else
403 features &= ~NETIF_F_HW_VLAN_TX;
404
405 return features;
406}
407
408static int atl2_set_features(struct net_device *netdev, u32 features)
409{
410 u32 changed = netdev->features ^ features;
411
412 if (changed & NETIF_F_HW_VLAN_RX)
413 atl2_vlan_mode(netdev, features);
414
415 return 0;
416}
417
418static void atl2_intr_rx(struct atl2_adapter *adapter)
419{
420 struct net_device *netdev = adapter->netdev;
421 struct rx_desc *rxd;
422 struct sk_buff *skb;
423
424 do {
425 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
426 if (!rxd->status.update)
427 break; /* end of tx */
428
429 /* clear this flag at once */
430 rxd->status.update = 0;
431
432 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
433 int rx_size = (int)(rxd->status.pkt_size - 4);
434 /* alloc new buffer */
435 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
436 if (NULL == skb) {
437 printk(KERN_WARNING
438 "%s: Mem squeeze, deferring packet.\n",
439 netdev->name);
440 /*
441 * Check that some rx space is free. If not,
442 * free one and mark stats->rx_dropped++.
443 */
444 netdev->stats.rx_dropped++;
445 break;
446 }
447 memcpy(skb->data, rxd->packet, rx_size);
448 skb_put(skb, rx_size);
449 skb->protocol = eth_type_trans(skb, netdev);
450 if (rxd->status.vlan) {
451 u16 vlan_tag = (rxd->status.vtag>>4) |
452 ((rxd->status.vtag&7) << 13) |
453 ((rxd->status.vtag&8) << 9);
454
455 __vlan_hwaccel_put_tag(skb, vlan_tag);
456 }
457 netif_rx(skb);
458 netdev->stats.rx_bytes += rx_size;
459 netdev->stats.rx_packets++;
460 } else {
461 netdev->stats.rx_errors++;
462
463 if (rxd->status.ok && rxd->status.pkt_size <= 60)
464 netdev->stats.rx_length_errors++;
465 if (rxd->status.mcast)
466 netdev->stats.multicast++;
467 if (rxd->status.crc)
468 netdev->stats.rx_crc_errors++;
469 if (rxd->status.align)
470 netdev->stats.rx_frame_errors++;
471 }
472
473 /* advance write ptr */
474 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
475 adapter->rxd_write_ptr = 0;
476 } while (1);
477
478 /* update mailbox? */
479 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
480 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
481}
482
483static void atl2_intr_tx(struct atl2_adapter *adapter)
484{
485 struct net_device *netdev = adapter->netdev;
486 u32 txd_read_ptr;
487 u32 txs_write_ptr;
488 struct tx_pkt_status *txs;
489 struct tx_pkt_header *txph;
490 int free_hole = 0;
491
492 do {
493 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
494 txs = adapter->txs_ring + txs_write_ptr;
495 if (!txs->update)
496 break; /* tx stop here */
497
498 free_hole = 1;
499 txs->update = 0;
500
501 if (++txs_write_ptr == adapter->txs_ring_size)
502 txs_write_ptr = 0;
503 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
504
505 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
506 txph = (struct tx_pkt_header *)
507 (((u8 *)adapter->txd_ring) + txd_read_ptr);
508
509 if (txph->pkt_size != txs->pkt_size) {
510 struct tx_pkt_status *old_txs = txs;
511 printk(KERN_WARNING
512 "%s: txs packet size not consistent with txd"
513 " txd_:0x%08x, txs_:0x%08x!\n",
514 adapter->netdev->name,
515 *(u32 *)txph, *(u32 *)txs);
516 printk(KERN_WARNING
517 "txd read ptr: 0x%x\n",
518 txd_read_ptr);
519 txs = adapter->txs_ring + txs_write_ptr;
520 printk(KERN_WARNING
521 "txs-behind:0x%08x\n",
522 *(u32 *)txs);
523 if (txs_write_ptr < 2) {
524 txs = adapter->txs_ring +
525 (adapter->txs_ring_size +
526 txs_write_ptr - 2);
527 } else {
528 txs = adapter->txs_ring + (txs_write_ptr - 2);
529 }
530 printk(KERN_WARNING
531 "txs-before:0x%08x\n",
532 *(u32 *)txs);
533 txs = old_txs;
534 }
535
536 /* 4for TPH */
537 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
538 if (txd_read_ptr >= adapter->txd_ring_size)
539 txd_read_ptr -= adapter->txd_ring_size;
540
541 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
542
543 /* tx statistics: */
544 if (txs->ok) {
545 netdev->stats.tx_bytes += txs->pkt_size;
546 netdev->stats.tx_packets++;
547 }
548 else
549 netdev->stats.tx_errors++;
550
551 if (txs->defer)
552 netdev->stats.collisions++;
553 if (txs->abort_col)
554 netdev->stats.tx_aborted_errors++;
555 if (txs->late_col)
556 netdev->stats.tx_window_errors++;
557 if (txs->underun)
558 netdev->stats.tx_fifo_errors++;
559 } while (1);
560
561 if (free_hole) {
562 if (netif_queue_stopped(adapter->netdev) &&
563 netif_carrier_ok(adapter->netdev))
564 netif_wake_queue(adapter->netdev);
565 }
566}
567
568static void atl2_check_for_link(struct atl2_adapter *adapter)
569{
570 struct net_device *netdev = adapter->netdev;
571 u16 phy_data = 0;
572
573 spin_lock(&adapter->stats_lock);
574 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
575 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
576 spin_unlock(&adapter->stats_lock);
577
578 /* notify upper layer link down ASAP */
579 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
580 if (netif_carrier_ok(netdev)) { /* old link state: Up */
581 printk(KERN_INFO "%s: %s NIC Link is Down\n",
582 atl2_driver_name, netdev->name);
583 adapter->link_speed = SPEED_0;
584 netif_carrier_off(netdev);
585 netif_stop_queue(netdev);
586 }
587 }
588 schedule_work(&adapter->link_chg_task);
589}
590
591static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
592{
593 u16 phy_data;
594 spin_lock(&adapter->stats_lock);
595 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
596 spin_unlock(&adapter->stats_lock);
597}
598
599/*
600 * atl2_intr - Interrupt Handler
601 * @irq: interrupt number
602 * @data: pointer to a network interface device structure
603 * @pt_regs: CPU registers structure
604 */
605static irqreturn_t atl2_intr(int irq, void *data)
606{
607 struct atl2_adapter *adapter = netdev_priv(data);
608 struct atl2_hw *hw = &adapter->hw;
609 u32 status;
610
611 status = ATL2_READ_REG(hw, REG_ISR);
612 if (0 == status)
613 return IRQ_NONE;
614
615 /* link event */
616 if (status & ISR_PHY)
617 atl2_clear_phy_int(adapter);
618
619 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
620 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
621
622 /* check if PCIE PHY Link down */
623 if (status & ISR_PHY_LINKDOWN) {
624 if (netif_running(adapter->netdev)) { /* reset MAC */
625 ATL2_WRITE_REG(hw, REG_ISR, 0);
626 ATL2_WRITE_REG(hw, REG_IMR, 0);
627 ATL2_WRITE_FLUSH(hw);
628 schedule_work(&adapter->reset_task);
629 return IRQ_HANDLED;
630 }
631 }
632
633 /* check if DMA read/write error? */
634 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
635 ATL2_WRITE_REG(hw, REG_ISR, 0);
636 ATL2_WRITE_REG(hw, REG_IMR, 0);
637 ATL2_WRITE_FLUSH(hw);
638 schedule_work(&adapter->reset_task);
639 return IRQ_HANDLED;
640 }
641
642 /* link event */
643 if (status & (ISR_PHY | ISR_MANUAL)) {
644 adapter->netdev->stats.tx_carrier_errors++;
645 atl2_check_for_link(adapter);
646 }
647
648 /* transmit event */
649 if (status & ISR_TX_EVENT)
650 atl2_intr_tx(adapter);
651
652 /* rx exception */
653 if (status & ISR_RX_EVENT)
654 atl2_intr_rx(adapter);
655
656 /* re-enable Interrupt */
657 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
658 return IRQ_HANDLED;
659}
660
661static int atl2_request_irq(struct atl2_adapter *adapter)
662{
663 struct net_device *netdev = adapter->netdev;
664 int flags, err = 0;
665
666 flags = IRQF_SHARED;
667 adapter->have_msi = true;
668 err = pci_enable_msi(adapter->pdev);
669 if (err)
670 adapter->have_msi = false;
671
672 if (adapter->have_msi)
673 flags &= ~IRQF_SHARED;
674
675 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
676 netdev);
677}
678
679/*
680 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
681 * @adapter: board private structure
682 *
683 * Free all transmit software resources
684 */
685static void atl2_free_ring_resources(struct atl2_adapter *adapter)
686{
687 struct pci_dev *pdev = adapter->pdev;
688 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
689 adapter->ring_dma);
690}
691
692/*
693 * atl2_open - Called when a network interface is made active
694 * @netdev: network interface device structure
695 *
696 * Returns 0 on success, negative value on failure
697 *
698 * The open entry point is called when a network interface is made
699 * active by the system (IFF_UP). At this point all resources needed
700 * for transmit and receive operations are allocated, the interrupt
701 * handler is registered with the OS, the watchdog timer is started,
702 * and the stack is notified that the interface is ready.
703 */
704static int atl2_open(struct net_device *netdev)
705{
706 struct atl2_adapter *adapter = netdev_priv(netdev);
707 int err;
708 u32 val;
709
710 /* disallow open during test */
711 if (test_bit(__ATL2_TESTING, &adapter->flags))
712 return -EBUSY;
713
714 /* allocate transmit descriptors */
715 err = atl2_setup_ring_resources(adapter);
716 if (err)
717 return err;
718
719 err = atl2_init_hw(&adapter->hw);
720 if (err) {
721 err = -EIO;
722 goto err_init_hw;
723 }
724
725 /* hardware has been reset, we need to reload some things */
726 atl2_set_multi(netdev);
727 init_ring_ptrs(adapter);
728
729 atl2_restore_vlan(adapter);
730
731 if (atl2_configure(adapter)) {
732 err = -EIO;
733 goto err_config;
734 }
735
736 err = atl2_request_irq(adapter);
737 if (err)
738 goto err_req_irq;
739
740 clear_bit(__ATL2_DOWN, &adapter->flags);
741
742 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
743
744 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
745 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
746 val | MASTER_CTRL_MANUAL_INT);
747
748 atl2_irq_enable(adapter);
749
750 return 0;
751
752err_init_hw:
753err_req_irq:
754err_config:
755 atl2_free_ring_resources(adapter);
756 atl2_reset_hw(&adapter->hw);
757
758 return err;
759}
760
761static void atl2_down(struct atl2_adapter *adapter)
762{
763 struct net_device *netdev = adapter->netdev;
764
765 /* signal that we're down so the interrupt handler does not
766 * reschedule our watchdog timer */
767 set_bit(__ATL2_DOWN, &adapter->flags);
768
769 netif_tx_disable(netdev);
770
771 /* reset MAC to disable all RX/TX */
772 atl2_reset_hw(&adapter->hw);
773 msleep(1);
774
775 atl2_irq_disable(adapter);
776
777 del_timer_sync(&adapter->watchdog_timer);
778 del_timer_sync(&adapter->phy_config_timer);
779 clear_bit(0, &adapter->cfg_phy);
780
781 netif_carrier_off(netdev);
782 adapter->link_speed = SPEED_0;
783 adapter->link_duplex = -1;
784}
785
786static void atl2_free_irq(struct atl2_adapter *adapter)
787{
788 struct net_device *netdev = adapter->netdev;
789
790 free_irq(adapter->pdev->irq, netdev);
791
792#ifdef CONFIG_PCI_MSI
793 if (adapter->have_msi)
794 pci_disable_msi(adapter->pdev);
795#endif
796}
797
798/*
799 * atl2_close - Disables a network interface
800 * @netdev: network interface device structure
801 *
802 * Returns 0, this is not allowed to fail
803 *
804 * The close entry point is called when an interface is de-activated
805 * by the OS. The hardware is still under the drivers control, but
806 * needs to be disabled. A global MAC reset is issued to stop the
807 * hardware, and all transmit and receive resources are freed.
808 */
809static int atl2_close(struct net_device *netdev)
810{
811 struct atl2_adapter *adapter = netdev_priv(netdev);
812
813 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
814
815 atl2_down(adapter);
816 atl2_free_irq(adapter);
817 atl2_free_ring_resources(adapter);
818
819 return 0;
820}
821
822static inline int TxsFreeUnit(struct atl2_adapter *adapter)
823{
824 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
825
826 return (adapter->txs_next_clear >= txs_write_ptr) ?
827 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
828 txs_write_ptr - 1) :
829 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
830}
831
832static inline int TxdFreeBytes(struct atl2_adapter *adapter)
833{
834 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
835
836 return (adapter->txd_write_ptr >= txd_read_ptr) ?
837 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
838 txd_read_ptr - 1) :
839 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
840}
841
842static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
843 struct net_device *netdev)
844{
845 struct atl2_adapter *adapter = netdev_priv(netdev);
846 struct tx_pkt_header *txph;
847 u32 offset, copy_len;
848 int txs_unused;
849 int txbuf_unused;
850
851 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
852 dev_kfree_skb_any(skb);
853 return NETDEV_TX_OK;
854 }
855
856 if (unlikely(skb->len <= 0)) {
857 dev_kfree_skb_any(skb);
858 return NETDEV_TX_OK;
859 }
860
861 txs_unused = TxsFreeUnit(adapter);
862 txbuf_unused = TxdFreeBytes(adapter);
863
864 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
865 txs_unused < 1) {
866 /* not enough resources */
867 netif_stop_queue(netdev);
868 return NETDEV_TX_BUSY;
869 }
870
871 offset = adapter->txd_write_ptr;
872
873 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
874
875 *(u32 *)txph = 0;
876 txph->pkt_size = skb->len;
877
878 offset += 4;
879 if (offset >= adapter->txd_ring_size)
880 offset -= adapter->txd_ring_size;
881 copy_len = adapter->txd_ring_size - offset;
882 if (copy_len >= skb->len) {
883 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
884 offset += ((u32)(skb->len + 3) & ~3);
885 } else {
886 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
887 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
888 skb->len-copy_len);
889 offset = ((u32)(skb->len-copy_len + 3) & ~3);
890 }
891#ifdef NETIF_F_HW_VLAN_TX
892 if (vlan_tx_tag_present(skb)) {
893 u16 vlan_tag = vlan_tx_tag_get(skb);
894 vlan_tag = (vlan_tag << 4) |
895 (vlan_tag >> 13) |
896 ((vlan_tag >> 9) & 0x8);
897 txph->ins_vlan = 1;
898 txph->vlan = vlan_tag;
899 }
900#endif
901 if (offset >= adapter->txd_ring_size)
902 offset -= adapter->txd_ring_size;
903 adapter->txd_write_ptr = offset;
904
905 /* clear txs before send */
906 adapter->txs_ring[adapter->txs_next_clear].update = 0;
907 if (++adapter->txs_next_clear == adapter->txs_ring_size)
908 adapter->txs_next_clear = 0;
909
910 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
911 (adapter->txd_write_ptr >> 2));
912
913 mmiowb();
914 dev_kfree_skb_any(skb);
915 return NETDEV_TX_OK;
916}
917
918/*
919 * atl2_change_mtu - Change the Maximum Transfer Unit
920 * @netdev: network interface device structure
921 * @new_mtu: new value for maximum frame size
922 *
923 * Returns 0 on success, negative on failure
924 */
925static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
926{
927 struct atl2_adapter *adapter = netdev_priv(netdev);
928 struct atl2_hw *hw = &adapter->hw;
929
930 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
931 return -EINVAL;
932
933 /* set MTU */
934 if (hw->max_frame_size != new_mtu) {
935 netdev->mtu = new_mtu;
936 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
937 VLAN_SIZE + ETHERNET_FCS_SIZE);
938 }
939
940 return 0;
941}
942
943/*
944 * atl2_set_mac - Change the Ethernet Address of the NIC
945 * @netdev: network interface device structure
946 * @p: pointer to an address structure
947 *
948 * Returns 0 on success, negative on failure
949 */
950static int atl2_set_mac(struct net_device *netdev, void *p)
951{
952 struct atl2_adapter *adapter = netdev_priv(netdev);
953 struct sockaddr *addr = p;
954
955 if (!is_valid_ether_addr(addr->sa_data))
956 return -EADDRNOTAVAIL;
957
958 if (netif_running(netdev))
959 return -EBUSY;
960
961 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
962 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
963
964 atl2_set_mac_addr(&adapter->hw);
965
966 return 0;
967}
968
969/*
970 * atl2_mii_ioctl -
971 * @netdev:
972 * @ifreq:
973 * @cmd:
974 */
975static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
976{
977 struct atl2_adapter *adapter = netdev_priv(netdev);
978 struct mii_ioctl_data *data = if_mii(ifr);
979 unsigned long flags;
980
981 switch (cmd) {
982 case SIOCGMIIPHY:
983 data->phy_id = 0;
984 break;
985 case SIOCGMIIREG:
986 spin_lock_irqsave(&adapter->stats_lock, flags);
987 if (atl2_read_phy_reg(&adapter->hw,
988 data->reg_num & 0x1F, &data->val_out)) {
989 spin_unlock_irqrestore(&adapter->stats_lock, flags);
990 return -EIO;
991 }
992 spin_unlock_irqrestore(&adapter->stats_lock, flags);
993 break;
994 case SIOCSMIIREG:
995 if (data->reg_num & ~(0x1F))
996 return -EFAULT;
997 spin_lock_irqsave(&adapter->stats_lock, flags);
998 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
999 data->val_in)) {
1000 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1001 return -EIO;
1002 }
1003 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1004 break;
1005 default:
1006 return -EOPNOTSUPP;
1007 }
1008 return 0;
1009}
1010
1011/*
1012 * atl2_ioctl -
1013 * @netdev:
1014 * @ifreq:
1015 * @cmd:
1016 */
1017static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1018{
1019 switch (cmd) {
1020 case SIOCGMIIPHY:
1021 case SIOCGMIIREG:
1022 case SIOCSMIIREG:
1023 return atl2_mii_ioctl(netdev, ifr, cmd);
1024#ifdef ETHTOOL_OPS_COMPAT
1025 case SIOCETHTOOL:
1026 return ethtool_ioctl(ifr);
1027#endif
1028 default:
1029 return -EOPNOTSUPP;
1030 }
1031}
1032
1033/*
1034 * atl2_tx_timeout - Respond to a Tx Hang
1035 * @netdev: network interface device structure
1036 */
1037static void atl2_tx_timeout(struct net_device *netdev)
1038{
1039 struct atl2_adapter *adapter = netdev_priv(netdev);
1040
1041 /* Do the reset outside of interrupt context */
1042 schedule_work(&adapter->reset_task);
1043}
1044
1045/*
1046 * atl2_watchdog - Timer Call-back
1047 * @data: pointer to netdev cast into an unsigned long
1048 */
1049static void atl2_watchdog(unsigned long data)
1050{
1051 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1052
1053 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1054 u32 drop_rxd, drop_rxs;
1055 unsigned long flags;
1056
1057 spin_lock_irqsave(&adapter->stats_lock, flags);
1058 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1059 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1060 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1061
1062 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1063
1064 /* Reset the timer */
1065 mod_timer(&adapter->watchdog_timer,
1066 round_jiffies(jiffies + 4 * HZ));
1067 }
1068}
1069
1070/*
1071 * atl2_phy_config - Timer Call-back
1072 * @data: pointer to netdev cast into an unsigned long
1073 */
1074static void atl2_phy_config(unsigned long data)
1075{
1076 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1077 struct atl2_hw *hw = &adapter->hw;
1078 unsigned long flags;
1079
1080 spin_lock_irqsave(&adapter->stats_lock, flags);
1081 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1082 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1083 MII_CR_RESTART_AUTO_NEG);
1084 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1085 clear_bit(0, &adapter->cfg_phy);
1086}
1087
1088static int atl2_up(struct atl2_adapter *adapter)
1089{
1090 struct net_device *netdev = adapter->netdev;
1091 int err = 0;
1092 u32 val;
1093
1094 /* hardware has been reset, we need to reload some things */
1095
1096 err = atl2_init_hw(&adapter->hw);
1097 if (err) {
1098 err = -EIO;
1099 return err;
1100 }
1101
1102 atl2_set_multi(netdev);
1103 init_ring_ptrs(adapter);
1104
1105 atl2_restore_vlan(adapter);
1106
1107 if (atl2_configure(adapter)) {
1108 err = -EIO;
1109 goto err_up;
1110 }
1111
1112 clear_bit(__ATL2_DOWN, &adapter->flags);
1113
1114 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1115 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1116 MASTER_CTRL_MANUAL_INT);
1117
1118 atl2_irq_enable(adapter);
1119
1120err_up:
1121 return err;
1122}
1123
1124static void atl2_reinit_locked(struct atl2_adapter *adapter)
1125{
1126 WARN_ON(in_interrupt());
1127 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1128 msleep(1);
1129 atl2_down(adapter);
1130 atl2_up(adapter);
1131 clear_bit(__ATL2_RESETTING, &adapter->flags);
1132}
1133
1134static void atl2_reset_task(struct work_struct *work)
1135{
1136 struct atl2_adapter *adapter;
1137 adapter = container_of(work, struct atl2_adapter, reset_task);
1138
1139 atl2_reinit_locked(adapter);
1140}
1141
1142static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1143{
1144 u32 value;
1145 struct atl2_hw *hw = &adapter->hw;
1146 struct net_device *netdev = adapter->netdev;
1147
1148 /* Config MAC CTRL Register */
1149 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1150
1151 /* duplex */
1152 if (FULL_DUPLEX == adapter->link_duplex)
1153 value |= MAC_CTRL_DUPLX;
1154
1155 /* flow control */
1156 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1157
1158 /* PAD & CRC */
1159 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1160
1161 /* preamble length */
1162 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1163 MAC_CTRL_PRMLEN_SHIFT);
1164
1165 /* vlan */
1166 __atl2_vlan_mode(netdev->features, &value);
1167
1168 /* filter mode */
1169 value |= MAC_CTRL_BC_EN;
1170 if (netdev->flags & IFF_PROMISC)
1171 value |= MAC_CTRL_PROMIS_EN;
1172 else if (netdev->flags & IFF_ALLMULTI)
1173 value |= MAC_CTRL_MC_ALL_EN;
1174
1175 /* half retry buffer */
1176 value |= (((u32)(adapter->hw.retry_buf &
1177 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1178
1179 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1180}
1181
1182static int atl2_check_link(struct atl2_adapter *adapter)
1183{
1184 struct atl2_hw *hw = &adapter->hw;
1185 struct net_device *netdev = adapter->netdev;
1186 int ret_val;
1187 u16 speed, duplex, phy_data;
1188 int reconfig = 0;
1189
1190 /* MII_BMSR must read twise */
1191 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1192 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1193 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1194 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1195 u32 value;
1196 /* disable rx */
1197 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1198 value &= ~MAC_CTRL_RX_EN;
1199 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1200 adapter->link_speed = SPEED_0;
1201 netif_carrier_off(netdev);
1202 netif_stop_queue(netdev);
1203 }
1204 return 0;
1205 }
1206
1207 /* Link Up */
1208 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1209 if (ret_val)
1210 return ret_val;
1211 switch (hw->MediaType) {
1212 case MEDIA_TYPE_100M_FULL:
1213 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1214 reconfig = 1;
1215 break;
1216 case MEDIA_TYPE_100M_HALF:
1217 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1218 reconfig = 1;
1219 break;
1220 case MEDIA_TYPE_10M_FULL:
1221 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1222 reconfig = 1;
1223 break;
1224 case MEDIA_TYPE_10M_HALF:
1225 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1226 reconfig = 1;
1227 break;
1228 }
1229 /* link result is our setting */
1230 if (reconfig == 0) {
1231 if (adapter->link_speed != speed ||
1232 adapter->link_duplex != duplex) {
1233 adapter->link_speed = speed;
1234 adapter->link_duplex = duplex;
1235 atl2_setup_mac_ctrl(adapter);
1236 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1237 atl2_driver_name, netdev->name,
1238 adapter->link_speed,
1239 adapter->link_duplex == FULL_DUPLEX ?
1240 "Full Duplex" : "Half Duplex");
1241 }
1242
1243 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1244 netif_carrier_on(netdev);
1245 netif_wake_queue(netdev);
1246 }
1247 return 0;
1248 }
1249
1250 /* change original link status */
1251 if (netif_carrier_ok(netdev)) {
1252 u32 value;
1253 /* disable rx */
1254 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1255 value &= ~MAC_CTRL_RX_EN;
1256 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1257
1258 adapter->link_speed = SPEED_0;
1259 netif_carrier_off(netdev);
1260 netif_stop_queue(netdev);
1261 }
1262
1263 /* auto-neg, insert timer to re-config phy
1264 * (if interval smaller than 5 seconds, something strange) */
1265 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1266 if (!test_and_set_bit(0, &adapter->cfg_phy))
1267 mod_timer(&adapter->phy_config_timer,
1268 round_jiffies(jiffies + 5 * HZ));
1269 }
1270
1271 return 0;
1272}
1273
1274/*
1275 * atl2_link_chg_task - deal with link change event Out of interrupt context
1276 * @netdev: network interface device structure
1277 */
1278static void atl2_link_chg_task(struct work_struct *work)
1279{
1280 struct atl2_adapter *adapter;
1281 unsigned long flags;
1282
1283 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1284
1285 spin_lock_irqsave(&adapter->stats_lock, flags);
1286 atl2_check_link(adapter);
1287 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1288}
1289
1290static void atl2_setup_pcicmd(struct pci_dev *pdev)
1291{
1292 u16 cmd;
1293
1294 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1295
1296 if (cmd & PCI_COMMAND_INTX_DISABLE)
1297 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1298 if (cmd & PCI_COMMAND_IO)
1299 cmd &= ~PCI_COMMAND_IO;
1300 if (0 == (cmd & PCI_COMMAND_MEMORY))
1301 cmd |= PCI_COMMAND_MEMORY;
1302 if (0 == (cmd & PCI_COMMAND_MASTER))
1303 cmd |= PCI_COMMAND_MASTER;
1304 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1305
1306 /*
1307 * some motherboards BIOS(PXE/EFI) driver may set PME
1308 * while they transfer control to OS (Windows/Linux)
1309 * so we should clear this bit before NIC work normally
1310 */
1311 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1312}
1313
1314#ifdef CONFIG_NET_POLL_CONTROLLER
1315static void atl2_poll_controller(struct net_device *netdev)
1316{
1317 disable_irq(netdev->irq);
1318 atl2_intr(netdev->irq, netdev);
1319 enable_irq(netdev->irq);
1320}
1321#endif
1322
1323
1324static const struct net_device_ops atl2_netdev_ops = {
1325 .ndo_open = atl2_open,
1326 .ndo_stop = atl2_close,
1327 .ndo_start_xmit = atl2_xmit_frame,
1328 .ndo_set_multicast_list = atl2_set_multi,
1329 .ndo_validate_addr = eth_validate_addr,
1330 .ndo_set_mac_address = atl2_set_mac,
1331 .ndo_change_mtu = atl2_change_mtu,
1332 .ndo_fix_features = atl2_fix_features,
1333 .ndo_set_features = atl2_set_features,
1334 .ndo_do_ioctl = atl2_ioctl,
1335 .ndo_tx_timeout = atl2_tx_timeout,
1336#ifdef CONFIG_NET_POLL_CONTROLLER
1337 .ndo_poll_controller = atl2_poll_controller,
1338#endif
1339};
1340
1341/*
1342 * atl2_probe - Device Initialization Routine
1343 * @pdev: PCI device information struct
1344 * @ent: entry in atl2_pci_tbl
1345 *
1346 * Returns 0 on success, negative on failure
1347 *
1348 * atl2_probe initializes an adapter identified by a pci_dev structure.
1349 * The OS initialization, configuring of the adapter private structure,
1350 * and a hardware reset occur.
1351 */
1352static int __devinit atl2_probe(struct pci_dev *pdev,
1353 const struct pci_device_id *ent)
1354{
1355 struct net_device *netdev;
1356 struct atl2_adapter *adapter;
1357 static int cards_found;
1358 unsigned long mmio_start;
1359 int mmio_len;
1360 int err;
1361
1362 cards_found = 0;
1363
1364 err = pci_enable_device(pdev);
1365 if (err)
1366 return err;
1367
1368 /*
1369 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1370 * until the kernel has the proper infrastructure to support 64-bit DMA
1371 * on these devices.
1372 */
1373 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1374 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1375 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1376 goto err_dma;
1377 }
1378
1379 /* Mark all PCI regions associated with PCI device
1380 * pdev as being reserved by owner atl2_driver_name */
1381 err = pci_request_regions(pdev, atl2_driver_name);
1382 if (err)
1383 goto err_pci_reg;
1384
1385 /* Enables bus-mastering on the device and calls
1386 * pcibios_set_master to do the needed arch specific settings */
1387 pci_set_master(pdev);
1388
1389 err = -ENOMEM;
1390 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1391 if (!netdev)
1392 goto err_alloc_etherdev;
1393
1394 SET_NETDEV_DEV(netdev, &pdev->dev);
1395
1396 pci_set_drvdata(pdev, netdev);
1397 adapter = netdev_priv(netdev);
1398 adapter->netdev = netdev;
1399 adapter->pdev = pdev;
1400 adapter->hw.back = adapter;
1401
1402 mmio_start = pci_resource_start(pdev, 0x0);
1403 mmio_len = pci_resource_len(pdev, 0x0);
1404
1405 adapter->hw.mem_rang = (u32)mmio_len;
1406 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1407 if (!adapter->hw.hw_addr) {
1408 err = -EIO;
1409 goto err_ioremap;
1410 }
1411
1412 atl2_setup_pcicmd(pdev);
1413
1414 netdev->netdev_ops = &atl2_netdev_ops;
1415 atl2_set_ethtool_ops(netdev);
1416 netdev->watchdog_timeo = 5 * HZ;
1417 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1418
1419 netdev->mem_start = mmio_start;
1420 netdev->mem_end = mmio_start + mmio_len;
1421 adapter->bd_number = cards_found;
1422 adapter->pci_using_64 = false;
1423
1424 /* setup the private structure */
1425 err = atl2_sw_init(adapter);
1426 if (err)
1427 goto err_sw_init;
1428
1429 err = -EIO;
1430
1431 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_RX;
1432 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1433
1434 /* Init PHY as early as possible due to power saving issue */
1435 atl2_phy_init(&adapter->hw);
1436
1437 /* reset the controller to
1438 * put the device in a known good starting state */
1439
1440 if (atl2_reset_hw(&adapter->hw)) {
1441 err = -EIO;
1442 goto err_reset;
1443 }
1444
1445 /* copy the MAC address out of the EEPROM */
1446 atl2_read_mac_addr(&adapter->hw);
1447 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1448/* FIXME: do we still need this? */
1449#ifdef ETHTOOL_GPERMADDR
1450 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1451
1452 if (!is_valid_ether_addr(netdev->perm_addr)) {
1453#else
1454 if (!is_valid_ether_addr(netdev->dev_addr)) {
1455#endif
1456 err = -EIO;
1457 goto err_eeprom;
1458 }
1459
1460 atl2_check_options(adapter);
1461
1462 init_timer(&adapter->watchdog_timer);
1463 adapter->watchdog_timer.function = atl2_watchdog;
1464 adapter->watchdog_timer.data = (unsigned long) adapter;
1465
1466 init_timer(&adapter->phy_config_timer);
1467 adapter->phy_config_timer.function = atl2_phy_config;
1468 adapter->phy_config_timer.data = (unsigned long) adapter;
1469
1470 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1471 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1472
1473 strcpy(netdev->name, "eth%d"); /* ?? */
1474 err = register_netdev(netdev);
1475 if (err)
1476 goto err_register;
1477
1478 /* assume we have no link for now */
1479 netif_carrier_off(netdev);
1480 netif_stop_queue(netdev);
1481
1482 cards_found++;
1483
1484 return 0;
1485
1486err_reset:
1487err_register:
1488err_sw_init:
1489err_eeprom:
1490 iounmap(adapter->hw.hw_addr);
1491err_ioremap:
1492 free_netdev(netdev);
1493err_alloc_etherdev:
1494 pci_release_regions(pdev);
1495err_pci_reg:
1496err_dma:
1497 pci_disable_device(pdev);
1498 return err;
1499}
1500
1501/*
1502 * atl2_remove - Device Removal Routine
1503 * @pdev: PCI device information struct
1504 *
1505 * atl2_remove is called by the PCI subsystem to alert the driver
1506 * that it should release a PCI device. The could be caused by a
1507 * Hot-Plug event, or because the driver is going to be removed from
1508 * memory.
1509 */
1510/* FIXME: write the original MAC address back in case it was changed from a
1511 * BIOS-set value, as in atl1 -- CHS */
1512static void __devexit atl2_remove(struct pci_dev *pdev)
1513{
1514 struct net_device *netdev = pci_get_drvdata(pdev);
1515 struct atl2_adapter *adapter = netdev_priv(netdev);
1516
1517 /* flush_scheduled work may reschedule our watchdog task, so
1518 * explicitly disable watchdog tasks from being rescheduled */
1519 set_bit(__ATL2_DOWN, &adapter->flags);
1520
1521 del_timer_sync(&adapter->watchdog_timer);
1522 del_timer_sync(&adapter->phy_config_timer);
1523 cancel_work_sync(&adapter->reset_task);
1524 cancel_work_sync(&adapter->link_chg_task);
1525
1526 unregister_netdev(netdev);
1527
1528 atl2_force_ps(&adapter->hw);
1529
1530 iounmap(adapter->hw.hw_addr);
1531 pci_release_regions(pdev);
1532
1533 free_netdev(netdev);
1534
1535 pci_disable_device(pdev);
1536}
1537
1538static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1539{
1540 struct net_device *netdev = pci_get_drvdata(pdev);
1541 struct atl2_adapter *adapter = netdev_priv(netdev);
1542 struct atl2_hw *hw = &adapter->hw;
1543 u16 speed, duplex;
1544 u32 ctrl = 0;
1545 u32 wufc = adapter->wol;
1546
1547#ifdef CONFIG_PM
1548 int retval = 0;
1549#endif
1550
1551 netif_device_detach(netdev);
1552
1553 if (netif_running(netdev)) {
1554 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1555 atl2_down(adapter);
1556 }
1557
1558#ifdef CONFIG_PM
1559 retval = pci_save_state(pdev);
1560 if (retval)
1561 return retval;
1562#endif
1563
1564 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1565 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1566 if (ctrl & BMSR_LSTATUS)
1567 wufc &= ~ATLX_WUFC_LNKC;
1568
1569 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1570 u32 ret_val;
1571 /* get current link speed & duplex */
1572 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1573 if (ret_val) {
1574 printk(KERN_DEBUG
1575 "%s: get speed&duplex error while suspend\n",
1576 atl2_driver_name);
1577 goto wol_dis;
1578 }
1579
1580 ctrl = 0;
1581
1582 /* turn on magic packet wol */
1583 if (wufc & ATLX_WUFC_MAG)
1584 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1585
1586 /* ignore Link Chg event when Link is up */
1587 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1588
1589 /* Config MAC CTRL Register */
1590 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1591 if (FULL_DUPLEX == adapter->link_duplex)
1592 ctrl |= MAC_CTRL_DUPLX;
1593 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1594 ctrl |= (((u32)adapter->hw.preamble_len &
1595 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1596 ctrl |= (((u32)(adapter->hw.retry_buf &
1597 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1598 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1599 if (wufc & ATLX_WUFC_MAG) {
1600 /* magic packet maybe Broadcast&multicast&Unicast */
1601 ctrl |= MAC_CTRL_BC_EN;
1602 }
1603
1604 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1605
1606 /* pcie patch */
1607 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1608 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1609 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1610 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1611 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1612 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1613
1614 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1615 goto suspend_exit;
1616 }
1617
1618 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1619 /* link is down, so only LINK CHG WOL event enable */
1620 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1621 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1622 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1623
1624 /* pcie patch */
1625 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1626 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1627 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1628 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1629 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1630 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1631
1632 hw->phy_configured = false; /* re-init PHY when resume */
1633
1634 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1635
1636 goto suspend_exit;
1637 }
1638
1639wol_dis:
1640 /* WOL disabled */
1641 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1642
1643 /* pcie patch */
1644 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1645 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1646 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1647 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1648 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1649 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1650
1651 atl2_force_ps(hw);
1652 hw->phy_configured = false; /* re-init PHY when resume */
1653
1654 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1655
1656suspend_exit:
1657 if (netif_running(netdev))
1658 atl2_free_irq(adapter);
1659
1660 pci_disable_device(pdev);
1661
1662 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1663
1664 return 0;
1665}
1666
1667#ifdef CONFIG_PM
1668static int atl2_resume(struct pci_dev *pdev)
1669{
1670 struct net_device *netdev = pci_get_drvdata(pdev);
1671 struct atl2_adapter *adapter = netdev_priv(netdev);
1672 u32 err;
1673
1674 pci_set_power_state(pdev, PCI_D0);
1675 pci_restore_state(pdev);
1676
1677 err = pci_enable_device(pdev);
1678 if (err) {
1679 printk(KERN_ERR
1680 "atl2: Cannot enable PCI device from suspend\n");
1681 return err;
1682 }
1683
1684 pci_set_master(pdev);
1685
1686 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1687
1688 pci_enable_wake(pdev, PCI_D3hot, 0);
1689 pci_enable_wake(pdev, PCI_D3cold, 0);
1690
1691 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1692
1693 if (netif_running(netdev)) {
1694 err = atl2_request_irq(adapter);
1695 if (err)
1696 return err;
1697 }
1698
1699 atl2_reset_hw(&adapter->hw);
1700
1701 if (netif_running(netdev))
1702 atl2_up(adapter);
1703
1704 netif_device_attach(netdev);
1705
1706 return 0;
1707}
1708#endif
1709
1710static void atl2_shutdown(struct pci_dev *pdev)
1711{
1712 atl2_suspend(pdev, PMSG_SUSPEND);
1713}
1714
1715static struct pci_driver atl2_driver = {
1716 .name = atl2_driver_name,
1717 .id_table = atl2_pci_tbl,
1718 .probe = atl2_probe,
1719 .remove = __devexit_p(atl2_remove),
1720 /* Power Management Hooks */
1721 .suspend = atl2_suspend,
1722#ifdef CONFIG_PM
1723 .resume = atl2_resume,
1724#endif
1725 .shutdown = atl2_shutdown,
1726};
1727
1728/*
1729 * atl2_init_module - Driver Registration Routine
1730 *
1731 * atl2_init_module is the first routine called when the driver is
1732 * loaded. All it does is register with the PCI subsystem.
1733 */
1734static int __init atl2_init_module(void)
1735{
1736 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1737 atl2_driver_version);
1738 printk(KERN_INFO "%s\n", atl2_copyright);
1739 return pci_register_driver(&atl2_driver);
1740}
1741module_init(atl2_init_module);
1742
1743/*
1744 * atl2_exit_module - Driver Exit Cleanup Routine
1745 *
1746 * atl2_exit_module is called just before the driver is removed
1747 * from memory.
1748 */
1749static void __exit atl2_exit_module(void)
1750{
1751 pci_unregister_driver(&atl2_driver);
1752}
1753module_exit(atl2_exit_module);
1754
1755static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1756{
1757 struct atl2_adapter *adapter = hw->back;
1758 pci_read_config_word(adapter->pdev, reg, value);
1759}
1760
1761static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1762{
1763 struct atl2_adapter *adapter = hw->back;
1764 pci_write_config_word(adapter->pdev, reg, *value);
1765}
1766
1767static int atl2_get_settings(struct net_device *netdev,
1768 struct ethtool_cmd *ecmd)
1769{
1770 struct atl2_adapter *adapter = netdev_priv(netdev);
1771 struct atl2_hw *hw = &adapter->hw;
1772
1773 ecmd->supported = (SUPPORTED_10baseT_Half |
1774 SUPPORTED_10baseT_Full |
1775 SUPPORTED_100baseT_Half |
1776 SUPPORTED_100baseT_Full |
1777 SUPPORTED_Autoneg |
1778 SUPPORTED_TP);
1779 ecmd->advertising = ADVERTISED_TP;
1780
1781 ecmd->advertising |= ADVERTISED_Autoneg;
1782 ecmd->advertising |= hw->autoneg_advertised;
1783
1784 ecmd->port = PORT_TP;
1785 ecmd->phy_address = 0;
1786 ecmd->transceiver = XCVR_INTERNAL;
1787
1788 if (adapter->link_speed != SPEED_0) {
1789 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
1790 if (adapter->link_duplex == FULL_DUPLEX)
1791 ecmd->duplex = DUPLEX_FULL;
1792 else
1793 ecmd->duplex = DUPLEX_HALF;
1794 } else {
1795 ethtool_cmd_speed_set(ecmd, -1);
1796 ecmd->duplex = -1;
1797 }
1798
1799 ecmd->autoneg = AUTONEG_ENABLE;
1800 return 0;
1801}
1802
1803static int atl2_set_settings(struct net_device *netdev,
1804 struct ethtool_cmd *ecmd)
1805{
1806 struct atl2_adapter *adapter = netdev_priv(netdev);
1807 struct atl2_hw *hw = &adapter->hw;
1808
1809 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1810 msleep(1);
1811
1812 if (ecmd->autoneg == AUTONEG_ENABLE) {
1813#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1814 ADVERTISE_10_FULL | \
1815 ADVERTISE_100_HALF| \
1816 ADVERTISE_100_FULL)
1817
1818 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1819 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1820 hw->autoneg_advertised = MY_ADV_MASK;
1821 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1822 ADVERTISE_100_FULL) {
1823 hw->MediaType = MEDIA_TYPE_100M_FULL;
1824 hw->autoneg_advertised = ADVERTISE_100_FULL;
1825 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1826 ADVERTISE_100_HALF) {
1827 hw->MediaType = MEDIA_TYPE_100M_HALF;
1828 hw->autoneg_advertised = ADVERTISE_100_HALF;
1829 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1830 ADVERTISE_10_FULL) {
1831 hw->MediaType = MEDIA_TYPE_10M_FULL;
1832 hw->autoneg_advertised = ADVERTISE_10_FULL;
1833 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1834 ADVERTISE_10_HALF) {
1835 hw->MediaType = MEDIA_TYPE_10M_HALF;
1836 hw->autoneg_advertised = ADVERTISE_10_HALF;
1837 } else {
1838 clear_bit(__ATL2_RESETTING, &adapter->flags);
1839 return -EINVAL;
1840 }
1841 ecmd->advertising = hw->autoneg_advertised |
1842 ADVERTISED_TP | ADVERTISED_Autoneg;
1843 } else {
1844 clear_bit(__ATL2_RESETTING, &adapter->flags);
1845 return -EINVAL;
1846 }
1847
1848 /* reset the link */
1849 if (netif_running(adapter->netdev)) {
1850 atl2_down(adapter);
1851 atl2_up(adapter);
1852 } else
1853 atl2_reset_hw(&adapter->hw);
1854
1855 clear_bit(__ATL2_RESETTING, &adapter->flags);
1856 return 0;
1857}
1858
1859static u32 atl2_get_msglevel(struct net_device *netdev)
1860{
1861 return 0;
1862}
1863
1864/*
1865 * It's sane for this to be empty, but we might want to take advantage of this.
1866 */
1867static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1868{
1869}
1870
1871static int atl2_get_regs_len(struct net_device *netdev)
1872{
1873#define ATL2_REGS_LEN 42
1874 return sizeof(u32) * ATL2_REGS_LEN;
1875}
1876
1877static void atl2_get_regs(struct net_device *netdev,
1878 struct ethtool_regs *regs, void *p)
1879{
1880 struct atl2_adapter *adapter = netdev_priv(netdev);
1881 struct atl2_hw *hw = &adapter->hw;
1882 u32 *regs_buff = p;
1883 u16 phy_data;
1884
1885 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1886
1887 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1888
1889 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1890 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1891 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1892 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1893 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1894 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1895 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1896 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1897 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1898 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1899 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1900 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1901 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1902 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1903 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1904 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1905 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1906 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1907 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1908 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1909 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1910 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1911 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1912 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1913 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1914 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1915 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1916 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1917 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1918 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1919 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1920 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1921 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1922 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1923 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1924 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1925 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1926 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1927 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1928
1929 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1930 regs_buff[40] = (u32)phy_data;
1931 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1932 regs_buff[41] = (u32)phy_data;
1933}
1934
1935static int atl2_get_eeprom_len(struct net_device *netdev)
1936{
1937 struct atl2_adapter *adapter = netdev_priv(netdev);
1938
1939 if (!atl2_check_eeprom_exist(&adapter->hw))
1940 return 512;
1941 else
1942 return 0;
1943}
1944
1945static int atl2_get_eeprom(struct net_device *netdev,
1946 struct ethtool_eeprom *eeprom, u8 *bytes)
1947{
1948 struct atl2_adapter *adapter = netdev_priv(netdev);
1949 struct atl2_hw *hw = &adapter->hw;
1950 u32 *eeprom_buff;
1951 int first_dword, last_dword;
1952 int ret_val = 0;
1953 int i;
1954
1955 if (eeprom->len == 0)
1956 return -EINVAL;
1957
1958 if (atl2_check_eeprom_exist(hw))
1959 return -EINVAL;
1960
1961 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1962
1963 first_dword = eeprom->offset >> 2;
1964 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1965
1966 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1967 GFP_KERNEL);
1968 if (!eeprom_buff)
1969 return -ENOMEM;
1970
1971 for (i = first_dword; i < last_dword; i++) {
1972 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) {
1973 ret_val = -EIO;
1974 goto free;
1975 }
1976 }
1977
1978 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1979 eeprom->len);
1980free:
1981 kfree(eeprom_buff);
1982
1983 return ret_val;
1984}
1985
1986static int atl2_set_eeprom(struct net_device *netdev,
1987 struct ethtool_eeprom *eeprom, u8 *bytes)
1988{
1989 struct atl2_adapter *adapter = netdev_priv(netdev);
1990 struct atl2_hw *hw = &adapter->hw;
1991 u32 *eeprom_buff;
1992 u32 *ptr;
1993 int max_len, first_dword, last_dword, ret_val = 0;
1994 int i;
1995
1996 if (eeprom->len == 0)
1997 return -EOPNOTSUPP;
1998
1999 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
2000 return -EFAULT;
2001
2002 max_len = 512;
2003
2004 first_dword = eeprom->offset >> 2;
2005 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
2006 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
2007 if (!eeprom_buff)
2008 return -ENOMEM;
2009
2010 ptr = eeprom_buff;
2011
2012 if (eeprom->offset & 3) {
2013 /* need read/modify/write of first changed EEPROM word */
2014 /* only the second byte of the word is being modified */
2015 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) {
2016 ret_val = -EIO;
2017 goto out;
2018 }
2019 ptr++;
2020 }
2021 if (((eeprom->offset + eeprom->len) & 3)) {
2022 /*
2023 * need read/modify/write of last changed EEPROM word
2024 * only the first byte of the word is being modified
2025 */
2026 if (!atl2_read_eeprom(hw, last_dword * 4,
2027 &(eeprom_buff[last_dword - first_dword]))) {
2028 ret_val = -EIO;
2029 goto out;
2030 }
2031 }
2032
2033 /* Device's eeprom is always little-endian, word addressable */
2034 memcpy(ptr, bytes, eeprom->len);
2035
2036 for (i = 0; i < last_dword - first_dword + 1; i++) {
2037 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) {
2038 ret_val = -EIO;
2039 goto out;
2040 }
2041 }
2042 out:
2043 kfree(eeprom_buff);
2044 return ret_val;
2045}
2046
2047static void atl2_get_drvinfo(struct net_device *netdev,
2048 struct ethtool_drvinfo *drvinfo)
2049{
2050 struct atl2_adapter *adapter = netdev_priv(netdev);
2051
2052 strncpy(drvinfo->driver, atl2_driver_name, 32);
2053 strncpy(drvinfo->version, atl2_driver_version, 32);
2054 strncpy(drvinfo->fw_version, "L2", 32);
2055 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2056 drvinfo->n_stats = 0;
2057 drvinfo->testinfo_len = 0;
2058 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2059 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2060}
2061
2062static void atl2_get_wol(struct net_device *netdev,
2063 struct ethtool_wolinfo *wol)
2064{
2065 struct atl2_adapter *adapter = netdev_priv(netdev);
2066
2067 wol->supported = WAKE_MAGIC;
2068 wol->wolopts = 0;
2069
2070 if (adapter->wol & ATLX_WUFC_EX)
2071 wol->wolopts |= WAKE_UCAST;
2072 if (adapter->wol & ATLX_WUFC_MC)
2073 wol->wolopts |= WAKE_MCAST;
2074 if (adapter->wol & ATLX_WUFC_BC)
2075 wol->wolopts |= WAKE_BCAST;
2076 if (adapter->wol & ATLX_WUFC_MAG)
2077 wol->wolopts |= WAKE_MAGIC;
2078 if (adapter->wol & ATLX_WUFC_LNKC)
2079 wol->wolopts |= WAKE_PHY;
2080}
2081
2082static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2083{
2084 struct atl2_adapter *adapter = netdev_priv(netdev);
2085
2086 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2087 return -EOPNOTSUPP;
2088
2089 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
2090 return -EOPNOTSUPP;
2091
2092 /* these settings will always override what we currently have */
2093 adapter->wol = 0;
2094
2095 if (wol->wolopts & WAKE_MAGIC)
2096 adapter->wol |= ATLX_WUFC_MAG;
2097 if (wol->wolopts & WAKE_PHY)
2098 adapter->wol |= ATLX_WUFC_LNKC;
2099
2100 return 0;
2101}
2102
2103static int atl2_nway_reset(struct net_device *netdev)
2104{
2105 struct atl2_adapter *adapter = netdev_priv(netdev);
2106 if (netif_running(netdev))
2107 atl2_reinit_locked(adapter);
2108 return 0;
2109}
2110
2111static const struct ethtool_ops atl2_ethtool_ops = {
2112 .get_settings = atl2_get_settings,
2113 .set_settings = atl2_set_settings,
2114 .get_drvinfo = atl2_get_drvinfo,
2115 .get_regs_len = atl2_get_regs_len,
2116 .get_regs = atl2_get_regs,
2117 .get_wol = atl2_get_wol,
2118 .set_wol = atl2_set_wol,
2119 .get_msglevel = atl2_get_msglevel,
2120 .set_msglevel = atl2_set_msglevel,
2121 .nway_reset = atl2_nway_reset,
2122 .get_link = ethtool_op_get_link,
2123 .get_eeprom_len = atl2_get_eeprom_len,
2124 .get_eeprom = atl2_get_eeprom,
2125 .set_eeprom = atl2_set_eeprom,
2126};
2127
2128static void atl2_set_ethtool_ops(struct net_device *netdev)
2129{
2130 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2131}
2132
2133#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2134 (((a) & 0xff00ff00) >> 8))
2135#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2136#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2137
2138/*
2139 * Reset the transmit and receive units; mask and clear all interrupts.
2140 *
2141 * hw - Struct containing variables accessed by shared code
2142 * return : 0 or idle status (if error)
2143 */
2144static s32 atl2_reset_hw(struct atl2_hw *hw)
2145{
2146 u32 icr;
2147 u16 pci_cfg_cmd_word;
2148 int i;
2149
2150 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2151 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2152 if ((pci_cfg_cmd_word &
2153 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2154 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2155 pci_cfg_cmd_word |=
2156 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2157 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2158 }
2159
2160 /* Clear Interrupt mask to stop board from generating
2161 * interrupts & Clear any pending interrupt events
2162 */
2163 /* FIXME */
2164 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2165 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2166
2167 /* Issue Soft Reset to the MAC. This will reset the chip's
2168 * transmit, receive, DMA. It will not effect
2169 * the current PCI configuration. The global reset bit is self-
2170 * clearing, and should clear within a microsecond.
2171 */
2172 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2173 wmb();
2174 msleep(1); /* delay about 1ms */
2175
2176 /* Wait at least 10ms for All module to be Idle */
2177 for (i = 0; i < 10; i++) {
2178 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2179 if (!icr)
2180 break;
2181 msleep(1); /* delay 1 ms */
2182 cpu_relax();
2183 }
2184
2185 if (icr)
2186 return icr;
2187
2188 return 0;
2189}
2190
2191#define CUSTOM_SPI_CS_SETUP 2
2192#define CUSTOM_SPI_CLK_HI 2
2193#define CUSTOM_SPI_CLK_LO 2
2194#define CUSTOM_SPI_CS_HOLD 2
2195#define CUSTOM_SPI_CS_HI 3
2196
2197static struct atl2_spi_flash_dev flash_table[] =
2198{
2199/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2200{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2201{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2202{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2203};
2204
2205static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2206{
2207 int i;
2208 u32 value;
2209
2210 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2211 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2212
2213 value = SPI_FLASH_CTRL_WAIT_READY |
2214 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2215 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2216 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2217 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2218 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2219 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2220 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2221 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2222 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2223 SPI_FLASH_CTRL_CS_HI_SHIFT |
2224 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2225
2226 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2227
2228 value |= SPI_FLASH_CTRL_START;
2229
2230 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2231
2232 for (i = 0; i < 10; i++) {
2233 msleep(1);
2234 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2235 if (!(value & SPI_FLASH_CTRL_START))
2236 break;
2237 }
2238
2239 if (value & SPI_FLASH_CTRL_START)
2240 return false;
2241
2242 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2243
2244 return true;
2245}
2246
2247/*
2248 * get_permanent_address
2249 * return 0 if get valid mac address,
2250 */
2251static int get_permanent_address(struct atl2_hw *hw)
2252{
2253 u32 Addr[2];
2254 u32 i, Control;
2255 u16 Register;
2256 u8 EthAddr[NODE_ADDRESS_SIZE];
2257 bool KeyValid;
2258
2259 if (is_valid_ether_addr(hw->perm_mac_addr))
2260 return 0;
2261
2262 Addr[0] = 0;
2263 Addr[1] = 0;
2264
2265 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2266 Register = 0;
2267 KeyValid = false;
2268
2269 /* Read out all EEPROM content */
2270 i = 0;
2271 while (1) {
2272 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2273 if (KeyValid) {
2274 if (Register == REG_MAC_STA_ADDR)
2275 Addr[0] = Control;
2276 else if (Register ==
2277 (REG_MAC_STA_ADDR + 4))
2278 Addr[1] = Control;
2279 KeyValid = false;
2280 } else if ((Control & 0xff) == 0x5A) {
2281 KeyValid = true;
2282 Register = (u16) (Control >> 16);
2283 } else {
2284 /* assume data end while encount an invalid KEYWORD */
2285 break;
2286 }
2287 } else {
2288 break; /* read error */
2289 }
2290 i += 4;
2291 }
2292
2293 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2294 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2295
2296 if (is_valid_ether_addr(EthAddr)) {
2297 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2298 return 0;
2299 }
2300 return 1;
2301 }
2302
2303 /* see if SPI flash exists? */
2304 Addr[0] = 0;
2305 Addr[1] = 0;
2306 Register = 0;
2307 KeyValid = false;
2308 i = 0;
2309 while (1) {
2310 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2311 if (KeyValid) {
2312 if (Register == REG_MAC_STA_ADDR)
2313 Addr[0] = Control;
2314 else if (Register == (REG_MAC_STA_ADDR + 4))
2315 Addr[1] = Control;
2316 KeyValid = false;
2317 } else if ((Control & 0xff) == 0x5A) {
2318 KeyValid = true;
2319 Register = (u16) (Control >> 16);
2320 } else {
2321 break; /* data end */
2322 }
2323 } else {
2324 break; /* read error */
2325 }
2326 i += 4;
2327 }
2328
2329 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2330 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2331 if (is_valid_ether_addr(EthAddr)) {
2332 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2333 return 0;
2334 }
2335 /* maybe MAC-address is from BIOS */
2336 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2337 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2338 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2339 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2340
2341 if (is_valid_ether_addr(EthAddr)) {
2342 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2343 return 0;
2344 }
2345
2346 return 1;
2347}
2348
2349/*
2350 * Reads the adapter's MAC address from the EEPROM
2351 *
2352 * hw - Struct containing variables accessed by shared code
2353 */
2354static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2355{
2356 u16 i;
2357
2358 if (get_permanent_address(hw)) {
2359 /* for test */
2360 /* FIXME: shouldn't we use random_ether_addr() here? */
2361 hw->perm_mac_addr[0] = 0x00;
2362 hw->perm_mac_addr[1] = 0x13;
2363 hw->perm_mac_addr[2] = 0x74;
2364 hw->perm_mac_addr[3] = 0x00;
2365 hw->perm_mac_addr[4] = 0x5c;
2366 hw->perm_mac_addr[5] = 0x38;
2367 }
2368
2369 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2370 hw->mac_addr[i] = hw->perm_mac_addr[i];
2371
2372 return 0;
2373}
2374
2375/*
2376 * Hashes an address to determine its location in the multicast table
2377 *
2378 * hw - Struct containing variables accessed by shared code
2379 * mc_addr - the multicast address to hash
2380 *
2381 * atl2_hash_mc_addr
2382 * purpose
2383 * set hash value for a multicast address
2384 * hash calcu processing :
2385 * 1. calcu 32bit CRC for multicast address
2386 * 2. reverse crc with MSB to LSB
2387 */
2388static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2389{
2390 u32 crc32, value;
2391 int i;
2392
2393 value = 0;
2394 crc32 = ether_crc_le(6, mc_addr);
2395
2396 for (i = 0; i < 32; i++)
2397 value |= (((crc32 >> i) & 1) << (31 - i));
2398
2399 return value;
2400}
2401
2402/*
2403 * Sets the bit in the multicast table corresponding to the hash value.
2404 *
2405 * hw - Struct containing variables accessed by shared code
2406 * hash_value - Multicast address hash value
2407 */
2408static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2409{
2410 u32 hash_bit, hash_reg;
2411 u32 mta;
2412
2413 /* The HASH Table is a register array of 2 32-bit registers.
2414 * It is treated like an array of 64 bits. We want to set
2415 * bit BitArray[hash_value]. So we figure out what register
2416 * the bit is in, read it, OR in the new bit, then write
2417 * back the new value. The register is determined by the
2418 * upper 7 bits of the hash value and the bit within that
2419 * register are determined by the lower 5 bits of the value.
2420 */
2421 hash_reg = (hash_value >> 31) & 0x1;
2422 hash_bit = (hash_value >> 26) & 0x1F;
2423
2424 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2425
2426 mta |= (1 << hash_bit);
2427
2428 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2429}
2430
2431/*
2432 * atl2_init_pcie - init PCIE module
2433 */
2434static void atl2_init_pcie(struct atl2_hw *hw)
2435{
2436 u32 value;
2437 value = LTSSM_TEST_MODE_DEF;
2438 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2439
2440 value = PCIE_DLL_TX_CTRL1_DEF;
2441 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2442}
2443
2444static void atl2_init_flash_opcode(struct atl2_hw *hw)
2445{
2446 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2447 hw->flash_vendor = 0; /* ATMEL */
2448
2449 /* Init OP table */
2450 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2451 flash_table[hw->flash_vendor].cmdPROGRAM);
2452 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2453 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2454 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2455 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2456 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2457 flash_table[hw->flash_vendor].cmdRDID);
2458 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2459 flash_table[hw->flash_vendor].cmdWREN);
2460 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2461 flash_table[hw->flash_vendor].cmdRDSR);
2462 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2463 flash_table[hw->flash_vendor].cmdWRSR);
2464 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2465 flash_table[hw->flash_vendor].cmdREAD);
2466}
2467
2468/********************************************************************
2469* Performs basic configuration of the adapter.
2470*
2471* hw - Struct containing variables accessed by shared code
2472* Assumes that the controller has previously been reset and is in a
2473* post-reset uninitialized state. Initializes multicast table,
2474* and Calls routines to setup link
2475* Leaves the transmit and receive units disabled and uninitialized.
2476********************************************************************/
2477static s32 atl2_init_hw(struct atl2_hw *hw)
2478{
2479 u32 ret_val = 0;
2480
2481 atl2_init_pcie(hw);
2482
2483 /* Zero out the Multicast HASH table */
2484 /* clear the old settings from the multicast hash table */
2485 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2486 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2487
2488 atl2_init_flash_opcode(hw);
2489
2490 ret_val = atl2_phy_init(hw);
2491
2492 return ret_val;
2493}
2494
2495/*
2496 * Detects the current speed and duplex settings of the hardware.
2497 *
2498 * hw - Struct containing variables accessed by shared code
2499 * speed - Speed of the connection
2500 * duplex - Duplex setting of the connection
2501 */
2502static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2503 u16 *duplex)
2504{
2505 s32 ret_val;
2506 u16 phy_data;
2507
2508 /* Read PHY Specific Status Register (17) */
2509 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2510 if (ret_val)
2511 return ret_val;
2512
2513 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2514 return ATLX_ERR_PHY_RES;
2515
2516 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2517 case MII_ATLX_PSSR_100MBS:
2518 *speed = SPEED_100;
2519 break;
2520 case MII_ATLX_PSSR_10MBS:
2521 *speed = SPEED_10;
2522 break;
2523 default:
2524 return ATLX_ERR_PHY_SPEED;
2525 break;
2526 }
2527
2528 if (phy_data & MII_ATLX_PSSR_DPLX)
2529 *duplex = FULL_DUPLEX;
2530 else
2531 *duplex = HALF_DUPLEX;
2532
2533 return 0;
2534}
2535
2536/*
2537 * Reads the value from a PHY register
2538 * hw - Struct containing variables accessed by shared code
2539 * reg_addr - address of the PHY register to read
2540 */
2541static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2542{
2543 u32 val;
2544 int i;
2545
2546 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2547 MDIO_START |
2548 MDIO_SUP_PREAMBLE |
2549 MDIO_RW |
2550 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2551 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2552
2553 wmb();
2554
2555 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2556 udelay(2);
2557 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2558 if (!(val & (MDIO_START | MDIO_BUSY)))
2559 break;
2560 wmb();
2561 }
2562 if (!(val & (MDIO_START | MDIO_BUSY))) {
2563 *phy_data = (u16)val;
2564 return 0;
2565 }
2566
2567 return ATLX_ERR_PHY;
2568}
2569
2570/*
2571 * Writes a value to a PHY register
2572 * hw - Struct containing variables accessed by shared code
2573 * reg_addr - address of the PHY register to write
2574 * data - data to write to the PHY
2575 */
2576static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2577{
2578 int i;
2579 u32 val;
2580
2581 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2582 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2583 MDIO_SUP_PREAMBLE |
2584 MDIO_START |
2585 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2586 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2587
2588 wmb();
2589
2590 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2591 udelay(2);
2592 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2593 if (!(val & (MDIO_START | MDIO_BUSY)))
2594 break;
2595
2596 wmb();
2597 }
2598
2599 if (!(val & (MDIO_START | MDIO_BUSY)))
2600 return 0;
2601
2602 return ATLX_ERR_PHY;
2603}
2604
2605/*
2606 * Configures PHY autoneg and flow control advertisement settings
2607 *
2608 * hw - Struct containing variables accessed by shared code
2609 */
2610static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2611{
2612 s32 ret_val;
2613 s16 mii_autoneg_adv_reg;
2614
2615 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2616 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2617
2618 /* Need to parse autoneg_advertised and set up
2619 * the appropriate PHY registers. First we will parse for
2620 * autoneg_advertised software override. Since we can advertise
2621 * a plethora of combinations, we need to check each bit
2622 * individually.
2623 */
2624
2625 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2626 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2627 * the 1000Base-T Control Register (Address 9). */
2628 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2629
2630 /* Need to parse MediaType and setup the
2631 * appropriate PHY registers. */
2632 switch (hw->MediaType) {
2633 case MEDIA_TYPE_AUTO_SENSOR:
2634 mii_autoneg_adv_reg |=
2635 (MII_AR_10T_HD_CAPS |
2636 MII_AR_10T_FD_CAPS |
2637 MII_AR_100TX_HD_CAPS|
2638 MII_AR_100TX_FD_CAPS);
2639 hw->autoneg_advertised =
2640 ADVERTISE_10_HALF |
2641 ADVERTISE_10_FULL |
2642 ADVERTISE_100_HALF|
2643 ADVERTISE_100_FULL;
2644 break;
2645 case MEDIA_TYPE_100M_FULL:
2646 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2647 hw->autoneg_advertised = ADVERTISE_100_FULL;
2648 break;
2649 case MEDIA_TYPE_100M_HALF:
2650 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2651 hw->autoneg_advertised = ADVERTISE_100_HALF;
2652 break;
2653 case MEDIA_TYPE_10M_FULL:
2654 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2655 hw->autoneg_advertised = ADVERTISE_10_FULL;
2656 break;
2657 default:
2658 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2659 hw->autoneg_advertised = ADVERTISE_10_HALF;
2660 break;
2661 }
2662
2663 /* flow control fixed to enable all */
2664 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2665
2666 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2667
2668 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2669
2670 if (ret_val)
2671 return ret_val;
2672
2673 return 0;
2674}
2675
2676/*
2677 * Resets the PHY and make all config validate
2678 *
2679 * hw - Struct containing variables accessed by shared code
2680 *
2681 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2682 */
2683static s32 atl2_phy_commit(struct atl2_hw *hw)
2684{
2685 s32 ret_val;
2686 u16 phy_data;
2687
2688 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2689 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2690 if (ret_val) {
2691 u32 val;
2692 int i;
2693 /* pcie serdes link may be down ! */
2694 for (i = 0; i < 25; i++) {
2695 msleep(1);
2696 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2697 if (!(val & (MDIO_START | MDIO_BUSY)))
2698 break;
2699 }
2700
2701 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2702 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2703 return ret_val;
2704 }
2705 }
2706 return 0;
2707}
2708
2709static s32 atl2_phy_init(struct atl2_hw *hw)
2710{
2711 s32 ret_val;
2712 u16 phy_val;
2713
2714 if (hw->phy_configured)
2715 return 0;
2716
2717 /* Enable PHY */
2718 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2719 ATL2_WRITE_FLUSH(hw);
2720 msleep(1);
2721
2722 /* check if the PHY is in powersaving mode */
2723 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2724 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2725
2726 /* 024E / 124E 0r 0274 / 1274 ? */
2727 if (phy_val & 0x1000) {
2728 phy_val &= ~0x1000;
2729 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2730 }
2731
2732 msleep(1);
2733
2734 /*Enable PHY LinkChange Interrupt */
2735 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2736 if (ret_val)
2737 return ret_val;
2738
2739 /* setup AutoNeg parameters */
2740 ret_val = atl2_phy_setup_autoneg_adv(hw);
2741 if (ret_val)
2742 return ret_val;
2743
2744 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2745 ret_val = atl2_phy_commit(hw);
2746 if (ret_val)
2747 return ret_val;
2748
2749 hw->phy_configured = true;
2750
2751 return ret_val;
2752}
2753
2754static void atl2_set_mac_addr(struct atl2_hw *hw)
2755{
2756 u32 value;
2757 /* 00-0B-6A-F6-00-DC
2758 * 0: 6AF600DC 1: 000B
2759 * low dword */
2760 value = (((u32)hw->mac_addr[2]) << 24) |
2761 (((u32)hw->mac_addr[3]) << 16) |
2762 (((u32)hw->mac_addr[4]) << 8) |
2763 (((u32)hw->mac_addr[5]));
2764 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2765 /* hight dword */
2766 value = (((u32)hw->mac_addr[0]) << 8) |
2767 (((u32)hw->mac_addr[1]));
2768 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2769}
2770
2771/*
2772 * check_eeprom_exist
2773 * return 0 if eeprom exist
2774 */
2775static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2776{
2777 u32 value;
2778
2779 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2780 if (value & SPI_FLASH_CTRL_EN_VPD) {
2781 value &= ~SPI_FLASH_CTRL_EN_VPD;
2782 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2783 }
2784 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2785 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2786}
2787
2788/* FIXME: This doesn't look right. -- CHS */
2789static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2790{
2791 return true;
2792}
2793
2794static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2795{
2796 int i;
2797 u32 Control;
2798
2799 if (Offset & 0x3)
2800 return false; /* address do not align */
2801
2802 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2803 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2804 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2805
2806 for (i = 0; i < 10; i++) {
2807 msleep(2);
2808 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2809 if (Control & VPD_CAP_VPD_FLAG)
2810 break;
2811 }
2812
2813 if (Control & VPD_CAP_VPD_FLAG) {
2814 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2815 return true;
2816 }
2817 return false; /* timeout */
2818}
2819
2820static void atl2_force_ps(struct atl2_hw *hw)
2821{
2822 u16 phy_val;
2823
2824 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2825 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2826 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2827
2828 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2829 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2830 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2831 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2832}
2833
2834/* This is the only thing that needs to be changed to adjust the
2835 * maximum number of ports that the driver can manage.
2836 */
2837#define ATL2_MAX_NIC 4
2838
2839#define OPTION_UNSET -1
2840#define OPTION_DISABLED 0
2841#define OPTION_ENABLED 1
2842
2843/* All parameters are treated the same, as an integer array of values.
2844 * This macro just reduces the need to repeat the same declaration code
2845 * over and over (plus this helps to avoid typo bugs).
2846 */
2847#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2848#ifndef module_param_array
2849/* Module Parameters are always initialized to -1, so that the driver
2850 * can tell the difference between no user specified value or the
2851 * user asking for the default value.
2852 * The true default values are loaded in when atl2_check_options is called.
2853 *
2854 * This is a GCC extension to ANSI C.
2855 * See the item "Labeled Elements in Initializers" in the section
2856 * "Extensions to the C Language Family" of the GCC documentation.
2857 */
2858
2859#define ATL2_PARAM(X, desc) \
2860 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2861 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2862 MODULE_PARM_DESC(X, desc);
2863#else
2864#define ATL2_PARAM(X, desc) \
2865 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2866 static unsigned int num_##X; \
2867 module_param_array_named(X, X, int, &num_##X, 0); \
2868 MODULE_PARM_DESC(X, desc);
2869#endif
2870
2871/*
2872 * Transmit Memory Size
2873 * Valid Range: 64-2048
2874 * Default Value: 128
2875 */
2876#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2877#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2878#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2879ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2880
2881/*
2882 * Receive Memory Block Count
2883 * Valid Range: 16-512
2884 * Default Value: 128
2885 */
2886#define ATL2_MIN_RXD_COUNT 16
2887#define ATL2_MAX_RXD_COUNT 512
2888#define ATL2_DEFAULT_RXD_COUNT 64
2889ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2890
2891/*
2892 * User Specified MediaType Override
2893 *
2894 * Valid Range: 0-5
2895 * - 0 - auto-negotiate at all supported speeds
2896 * - 1 - only link at 1000Mbps Full Duplex
2897 * - 2 - only link at 100Mbps Full Duplex
2898 * - 3 - only link at 100Mbps Half Duplex
2899 * - 4 - only link at 10Mbps Full Duplex
2900 * - 5 - only link at 10Mbps Half Duplex
2901 * Default Value: 0
2902 */
2903ATL2_PARAM(MediaType, "MediaType Select");
2904
2905/*
2906 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2907 * Valid Range: 10-65535
2908 * Default Value: 45000(90ms)
2909 */
2910#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2911#define INT_MOD_MAX_CNT 65000
2912#define INT_MOD_MIN_CNT 50
2913ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2914
2915/*
2916 * FlashVendor
2917 * Valid Range: 0-2
2918 * 0 - Atmel
2919 * 1 - SST
2920 * 2 - ST
2921 */
2922ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2923
2924#define AUTONEG_ADV_DEFAULT 0x2F
2925#define AUTONEG_ADV_MASK 0x2F
2926#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2927
2928#define FLASH_VENDOR_DEFAULT 0
2929#define FLASH_VENDOR_MIN 0
2930#define FLASH_VENDOR_MAX 2
2931
2932struct atl2_option {
2933 enum { enable_option, range_option, list_option } type;
2934 char *name;
2935 char *err;
2936 int def;
2937 union {
2938 struct { /* range_option info */
2939 int min;
2940 int max;
2941 } r;
2942 struct { /* list_option info */
2943 int nr;
2944 struct atl2_opt_list { int i; char *str; } *p;
2945 } l;
2946 } arg;
2947};
2948
2949static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2950{
2951 int i;
2952 struct atl2_opt_list *ent;
2953
2954 if (*value == OPTION_UNSET) {
2955 *value = opt->def;
2956 return 0;
2957 }
2958
2959 switch (opt->type) {
2960 case enable_option:
2961 switch (*value) {
2962 case OPTION_ENABLED:
2963 printk(KERN_INFO "%s Enabled\n", opt->name);
2964 return 0;
2965 break;
2966 case OPTION_DISABLED:
2967 printk(KERN_INFO "%s Disabled\n", opt->name);
2968 return 0;
2969 break;
2970 }
2971 break;
2972 case range_option:
2973 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2974 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2975 return 0;
2976 }
2977 break;
2978 case list_option:
2979 for (i = 0; i < opt->arg.l.nr; i++) {
2980 ent = &opt->arg.l.p[i];
2981 if (*value == ent->i) {
2982 if (ent->str[0] != '\0')
2983 printk(KERN_INFO "%s\n", ent->str);
2984 return 0;
2985 }
2986 }
2987 break;
2988 default:
2989 BUG();
2990 }
2991
2992 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2993 opt->name, *value, opt->err);
2994 *value = opt->def;
2995 return -1;
2996}
2997
2998/*
2999 * atl2_check_options - Range Checking for Command Line Parameters
3000 * @adapter: board private structure
3001 *
3002 * This routine checks all command line parameters for valid user
3003 * input. If an invalid value is given, or if no user specified
3004 * value exists, a default value is used. The final value is stored
3005 * in a variable in the adapter structure.
3006 */
3007static void __devinit atl2_check_options(struct atl2_adapter *adapter)
3008{
3009 int val;
3010 struct atl2_option opt;
3011 int bd = adapter->bd_number;
3012 if (bd >= ATL2_MAX_NIC) {
3013 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3014 bd);
3015 printk(KERN_NOTICE "Using defaults for all values\n");
3016#ifndef module_param_array
3017 bd = ATL2_MAX_NIC;
3018#endif
3019 }
3020
3021 /* Bytes of Transmit Memory */
3022 opt.type = range_option;
3023 opt.name = "Bytes of Transmit Memory";
3024 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3025 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3026 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3027 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3028#ifdef module_param_array
3029 if (num_TxMemSize > bd) {
3030#endif
3031 val = TxMemSize[bd];
3032 atl2_validate_option(&val, &opt);
3033 adapter->txd_ring_size = ((u32) val) * 1024;
3034#ifdef module_param_array
3035 } else
3036 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3037#endif
3038 /* txs ring size: */
3039 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3040 if (adapter->txs_ring_size > 160)
3041 adapter->txs_ring_size = 160;
3042
3043 /* Receive Memory Block Count */
3044 opt.type = range_option;
3045 opt.name = "Number of receive memory block";
3046 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3047 opt.def = ATL2_DEFAULT_RXD_COUNT;
3048 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3049 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3050#ifdef module_param_array
3051 if (num_RxMemBlock > bd) {
3052#endif
3053 val = RxMemBlock[bd];
3054 atl2_validate_option(&val, &opt);
3055 adapter->rxd_ring_size = (u32)val;
3056 /* FIXME */
3057 /* ((u16)val)&~1; */ /* even number */
3058#ifdef module_param_array
3059 } else
3060 adapter->rxd_ring_size = (u32)opt.def;
3061#endif
3062 /* init RXD Flow control value */
3063 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3064 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3065 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3066 (adapter->rxd_ring_size / 12);
3067
3068 /* Interrupt Moderate Timer */
3069 opt.type = range_option;
3070 opt.name = "Interrupt Moderate Timer";
3071 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3072 opt.def = INT_MOD_DEFAULT_CNT;
3073 opt.arg.r.min = INT_MOD_MIN_CNT;
3074 opt.arg.r.max = INT_MOD_MAX_CNT;
3075#ifdef module_param_array
3076 if (num_IntModTimer > bd) {
3077#endif
3078 val = IntModTimer[bd];
3079 atl2_validate_option(&val, &opt);
3080 adapter->imt = (u16) val;
3081#ifdef module_param_array
3082 } else
3083 adapter->imt = (u16)(opt.def);
3084#endif
3085 /* Flash Vendor */
3086 opt.type = range_option;
3087 opt.name = "SPI Flash Vendor";
3088 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3089 opt.def = FLASH_VENDOR_DEFAULT;
3090 opt.arg.r.min = FLASH_VENDOR_MIN;
3091 opt.arg.r.max = FLASH_VENDOR_MAX;
3092#ifdef module_param_array
3093 if (num_FlashVendor > bd) {
3094#endif
3095 val = FlashVendor[bd];
3096 atl2_validate_option(&val, &opt);
3097 adapter->hw.flash_vendor = (u8) val;
3098#ifdef module_param_array
3099 } else
3100 adapter->hw.flash_vendor = (u8)(opt.def);
3101#endif
3102 /* MediaType */
3103 opt.type = range_option;
3104 opt.name = "Speed/Duplex Selection";
3105 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3106 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3107 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3108 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3109#ifdef module_param_array
3110 if (num_MediaType > bd) {
3111#endif
3112 val = MediaType[bd];
3113 atl2_validate_option(&val, &opt);
3114 adapter->hw.MediaType = (u16) val;
3115#ifdef module_param_array
3116 } else
3117 adapter->hw.MediaType = (u16)(opt.def);
3118#endif
3119}
diff --git a/drivers/net/atlx/atl2.h b/drivers/net/atlx/atl2.h
new file mode 100644
index 00000000000..bf9016ebdd9
--- /dev/null
+++ b/drivers/net/atlx/atl2.h
@@ -0,0 +1,525 @@
1/* atl2.h -- atl2 driver definitions
2 *
3 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
4 * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com>
5 * Copyright(c) 2007 Chris Snook <csnook@redhat.com>
6 *
7 * Derived from Intel e1000 driver
8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 */
24
25#ifndef _ATL2_H_
26#define _ATL2_H_
27
28#include <linux/atomic.h>
29#include <linux/netdevice.h>
30
31#ifndef _ATL2_HW_H_
32#define _ATL2_HW_H_
33
34#ifndef _ATL2_OSDEP_H_
35#define _ATL2_OSDEP_H_
36
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/if_ether.h>
41
42#include "atlx.h"
43
44#ifdef ETHTOOL_OPS_COMPAT
45extern int ethtool_ioctl(struct ifreq *ifr);
46#endif
47
48#define PCI_COMMAND_REGISTER PCI_COMMAND
49#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
50#define ETH_ADDR_LEN ETH_ALEN
51
52#define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \
53 ((a)->hw_addr + (reg))))
54
55#define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr))
56
57#define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg)))
58
59#define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \
60 ((a)->hw_addr + (reg))))
61
62#define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg)))
63
64#define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \
65 ((a)->hw_addr + (reg))))
66
67#define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg)))
68
69#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \
70 (iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2))))
71
72#define ATL2_READ_REG_ARRAY(a, reg, offset) \
73 (ioread32(((a)->hw_addr + (reg)) + ((offset) << 2)))
74
75#endif /* _ATL2_OSDEP_H_ */
76
77struct atl2_adapter;
78struct atl2_hw;
79
80/* function prototype */
81static s32 atl2_reset_hw(struct atl2_hw *hw);
82static s32 atl2_read_mac_addr(struct atl2_hw *hw);
83static s32 atl2_init_hw(struct atl2_hw *hw);
84static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
85 u16 *duplex);
86static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr);
87static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value);
88static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data);
89static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data);
90static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
91static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
92static void atl2_set_mac_addr(struct atl2_hw *hw);
93static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue);
94static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value);
95static s32 atl2_phy_init(struct atl2_hw *hw);
96static int atl2_check_eeprom_exist(struct atl2_hw *hw);
97static void atl2_force_ps(struct atl2_hw *hw);
98
99/* register definition */
100
101/* Block IDLE Status Register */
102#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC is non-IDLE */
103#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC is non-IDLE */
104#define IDLE_STATUS_DMAR 8 /* 1: DMAR is non-IDLE */
105#define IDLE_STATUS_DMAW 4 /* 1: DMAW is non-IDLE */
106
107/* MDIO Control Register */
108#define MDIO_WAIT_TIMES 10
109
110/* MAC Control Register */
111#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: TX max backoff */
112#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: 25MHz from phy */
113#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28
114#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* MAC retry buf x32B */
115
116/* Internal SRAM Partition Register */
117#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM
118 * default: 2byte*1024 */
119#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM
120 * default: 2byte*1024 */
121
122/* Descriptor Control register */
123#define REG_TXD_BASE_ADDR_LO 0x1544 /* The base address of the Transmit
124 * Data Mem low 32-bit(dword align) */
125#define REG_TXD_MEM_SIZE 0x1548 /* Transmit Data Memory size(by
126 * double word , max 256KB) */
127#define REG_TXS_BASE_ADDR_LO 0x154C /* The base address of the Transmit
128 * Status Memory low 32-bit(dword word
129 * align) */
130#define REG_TXS_MEM_SIZE 0x1550 /* double word unit, max 4*2047
131 * bytes. */
132#define REG_RXD_BASE_ADDR_LO 0x1554 /* The base address of the Transmit
133 * Status Memory low 32-bit(unit 8
134 * bytes) */
135#define REG_RXD_BUF_NUM 0x1558 /* Receive Data & Status Memory buffer
136 * number (unit 1536bytes, max
137 * 1536*2047) */
138
139/* DMAR Control Register */
140#define REG_DMAR 0x1580
141#define DMAR_EN 0x1 /* 1: Enable DMAR */
142
143/* TX Cur-Through (early tx threshold) Control Register */
144#define REG_TX_CUT_THRESH 0x1590 /* TxMac begin transmit packet
145 * threshold(unit word) */
146
147/* DMAW Control Register */
148#define REG_DMAW 0x15A0
149#define DMAW_EN 0x1
150
151/* Flow control register */
152#define REG_PAUSE_ON_TH 0x15A8 /* RXD high watermark of overflow
153 * threshold configuration register */
154#define REG_PAUSE_OFF_TH 0x15AA /* RXD lower watermark of overflow
155 * threshold configuration register */
156
157/* Mailbox Register */
158#define REG_MB_TXD_WR_IDX 0x15f0 /* double word align */
159#define REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */
160
161/* Interrupt Status Register */
162#define ISR_TIMER 1 /* Interrupt when Timer counts down to zero */
163#define ISR_MANUAL 2 /* Software manual interrupt, for debug. Set
164 * when SW_MAN_INT_EN is set in Table 51
165 * Selene Master Control Register
166 * (Offset 0x1400). */
167#define ISR_RXF_OV 4 /* RXF overflow interrupt */
168#define ISR_TXF_UR 8 /* TXF underrun interrupt */
169#define ISR_TXS_OV 0x10 /* Internal transmit status buffer full
170 * interrupt */
171#define ISR_RXS_OV 0x20 /* Internal receive status buffer full
172 * interrupt */
173#define ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */
174#define ISR_HOST_TXD_UR 0x80
175#define ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */
176#define ISR_DMAR_TO_RST 0x200 /* DMAR op timeout interrupt. SW should
177 * do Reset */
178#define ISR_DMAW_TO_RST 0x400
179#define ISR_PHY 0x800 /* phy interrupt */
180#define ISR_TS_UPDATE 0x10000 /* interrupt after new tx pkt status written
181 * to host */
182#define ISR_RS_UPDATE 0x20000 /* interrupt ater new rx pkt status written
183 * to host. */
184#define ISR_TX_EARLY 0x40000 /* interrupt when txmac begin transmit one
185 * packet */
186
187#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | ISR_HOST_TXD_UR |\
188 ISR_TS_UPDATE | ISR_TX_EARLY)
189#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | ISR_HOST_RXD_OV |\
190 ISR_RS_UPDATE)
191
192#define IMR_NORMAL_MASK (\
193 /*ISR_LINK_CHG |*/\
194 ISR_MANUAL |\
195 ISR_DMAR_TO_RST |\
196 ISR_DMAW_TO_RST |\
197 ISR_PHY |\
198 ISR_PHY_LINKDOWN |\
199 ISR_TS_UPDATE |\
200 ISR_RS_UPDATE)
201
202/* Receive MAC Statistics Registers */
203#define REG_STS_RX_PAUSE 0x1700 /* Num pause packets received */
204#define REG_STS_RXD_OV 0x1704 /* Num frames dropped due to RX
205 * FIFO overflow */
206#define REG_STS_RXS_OV 0x1708 /* Num frames dropped due to RX
207 * Status Buffer Overflow */
208#define REG_STS_RX_FILTER 0x170C /* Num packets dropped due to
209 * address filtering */
210
211/* MII definitions */
212
213/* PHY Common Register */
214#define MII_SMARTSPEED 0x14
215#define MII_DBG_ADDR 0x1D
216#define MII_DBG_DATA 0x1E
217
218/* PCI Command Register Bit Definitions */
219#define PCI_REG_COMMAND 0x04
220#define CMD_IO_SPACE 0x0001
221#define CMD_MEMORY_SPACE 0x0002
222#define CMD_BUS_MASTER 0x0004
223
224#define MEDIA_TYPE_100M_FULL 1
225#define MEDIA_TYPE_100M_HALF 2
226#define MEDIA_TYPE_10M_FULL 3
227#define MEDIA_TYPE_10M_HALF 4
228
229#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */
230
231/* The size (in bytes) of a ethernet packet */
232#define ENET_HEADER_SIZE 14
233#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */
234#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */
235#define ETHERNET_FCS_SIZE 4
236#define MAX_JUMBO_FRAME_SIZE 0x2000
237#define VLAN_SIZE 4
238
239struct tx_pkt_header {
240 unsigned pkt_size:11;
241 unsigned:4; /* reserved */
242 unsigned ins_vlan:1; /* txmac should insert vlan */
243 unsigned short vlan; /* vlan tag */
244};
245/* FIXME: replace above bitfields with MASK/SHIFT defines below */
246#define TX_PKT_HEADER_SIZE_MASK 0x7FF
247#define TX_PKT_HEADER_SIZE_SHIFT 0
248#define TX_PKT_HEADER_INS_VLAN_MASK 0x1
249#define TX_PKT_HEADER_INS_VLAN_SHIFT 15
250#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF
251#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16
252
253struct tx_pkt_status {
254 unsigned pkt_size:11;
255 unsigned:5; /* reserved */
256 unsigned ok:1; /* current packet transmitted without error */
257 unsigned bcast:1; /* broadcast packet */
258 unsigned mcast:1; /* multicast packet */
259 unsigned pause:1; /* transmiited a pause frame */
260 unsigned ctrl:1;
261 unsigned defer:1; /* current packet is xmitted with defer */
262 unsigned exc_defer:1;
263 unsigned single_col:1;
264 unsigned multi_col:1;
265 unsigned late_col:1;
266 unsigned abort_col:1;
267 unsigned underun:1; /* current packet is aborted
268 * due to txram underrun */
269 unsigned:3; /* reserved */
270 unsigned update:1; /* always 1'b1 in tx_status_buf */
271};
272/* FIXME: replace above bitfields with MASK/SHIFT defines below */
273#define TX_PKT_STATUS_SIZE_MASK 0x7FF
274#define TX_PKT_STATUS_SIZE_SHIFT 0
275#define TX_PKT_STATUS_OK_MASK 0x1
276#define TX_PKT_STATUS_OK_SHIFT 16
277#define TX_PKT_STATUS_BCAST_MASK 0x1
278#define TX_PKT_STATUS_BCAST_SHIFT 17
279#define TX_PKT_STATUS_MCAST_MASK 0x1
280#define TX_PKT_STATUS_MCAST_SHIFT 18
281#define TX_PKT_STATUS_PAUSE_MASK 0x1
282#define TX_PKT_STATUS_PAUSE_SHIFT 19
283#define TX_PKT_STATUS_CTRL_MASK 0x1
284#define TX_PKT_STATUS_CTRL_SHIFT 20
285#define TX_PKT_STATUS_DEFER_MASK 0x1
286#define TX_PKT_STATUS_DEFER_SHIFT 21
287#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1
288#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22
289#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1
290#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23
291#define TX_PKT_STATUS_MULTI_COL_MASK 0x1
292#define TX_PKT_STATUS_MULTI_COL_SHIFT 24
293#define TX_PKT_STATUS_LATE_COL_MASK 0x1
294#define TX_PKT_STATUS_LATE_COL_SHIFT 25
295#define TX_PKT_STATUS_ABORT_COL_MASK 0x1
296#define TX_PKT_STATUS_ABORT_COL_SHIFT 26
297#define TX_PKT_STATUS_UNDERRUN_MASK 0x1
298#define TX_PKT_STATUS_UNDERRUN_SHIFT 27
299#define TX_PKT_STATUS_UPDATE_MASK 0x1
300#define TX_PKT_STATUS_UPDATE_SHIFT 31
301
302struct rx_pkt_status {
303 unsigned pkt_size:11; /* packet size, max 2047 bytes */
304 unsigned:5; /* reserved */
305 unsigned ok:1; /* current packet received ok without error */
306 unsigned bcast:1; /* current packet is broadcast */
307 unsigned mcast:1; /* current packet is multicast */
308 unsigned pause:1;
309 unsigned ctrl:1;
310 unsigned crc:1; /* received a packet with crc error */
311 unsigned code:1; /* received a packet with code error */
312 unsigned runt:1; /* received a packet less than 64 bytes
313 * with good crc */
314 unsigned frag:1; /* received a packet less than 64 bytes
315 * with bad crc */
316 unsigned trunc:1; /* current frame truncated due to rxram full */
317 unsigned align:1; /* this packet is alignment error */
318 unsigned vlan:1; /* this packet has vlan */
319 unsigned:3; /* reserved */
320 unsigned update:1;
321 unsigned short vtag; /* vlan tag */
322 unsigned:16;
323};
324/* FIXME: replace above bitfields with MASK/SHIFT defines below */
325#define RX_PKT_STATUS_SIZE_MASK 0x7FF
326#define RX_PKT_STATUS_SIZE_SHIFT 0
327#define RX_PKT_STATUS_OK_MASK 0x1
328#define RX_PKT_STATUS_OK_SHIFT 16
329#define RX_PKT_STATUS_BCAST_MASK 0x1
330#define RX_PKT_STATUS_BCAST_SHIFT 17
331#define RX_PKT_STATUS_MCAST_MASK 0x1
332#define RX_PKT_STATUS_MCAST_SHIFT 18
333#define RX_PKT_STATUS_PAUSE_MASK 0x1
334#define RX_PKT_STATUS_PAUSE_SHIFT 19
335#define RX_PKT_STATUS_CTRL_MASK 0x1
336#define RX_PKT_STATUS_CTRL_SHIFT 20
337#define RX_PKT_STATUS_CRC_MASK 0x1
338#define RX_PKT_STATUS_CRC_SHIFT 21
339#define RX_PKT_STATUS_CODE_MASK 0x1
340#define RX_PKT_STATUS_CODE_SHIFT 22
341#define RX_PKT_STATUS_RUNT_MASK 0x1
342#define RX_PKT_STATUS_RUNT_SHIFT 23
343#define RX_PKT_STATUS_FRAG_MASK 0x1
344#define RX_PKT_STATUS_FRAG_SHIFT 24
345#define RX_PKT_STATUS_TRUNK_MASK 0x1
346#define RX_PKT_STATUS_TRUNK_SHIFT 25
347#define RX_PKT_STATUS_ALIGN_MASK 0x1
348#define RX_PKT_STATUS_ALIGN_SHIFT 26
349#define RX_PKT_STATUS_VLAN_MASK 0x1
350#define RX_PKT_STATUS_VLAN_SHIFT 27
351#define RX_PKT_STATUS_UPDATE_MASK 0x1
352#define RX_PKT_STATUS_UPDATE_SHIFT 31
353#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF
354#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32
355
356struct rx_desc {
357 struct rx_pkt_status status;
358 unsigned char packet[1536-sizeof(struct rx_pkt_status)];
359};
360
361enum atl2_speed_duplex {
362 atl2_10_half = 0,
363 atl2_10_full = 1,
364 atl2_100_half = 2,
365 atl2_100_full = 3
366};
367
368struct atl2_spi_flash_dev {
369 const char *manu_name; /* manufacturer id */
370 /* op-code */
371 u8 cmdWRSR;
372 u8 cmdREAD;
373 u8 cmdPROGRAM;
374 u8 cmdWREN;
375 u8 cmdWRDI;
376 u8 cmdRDSR;
377 u8 cmdRDID;
378 u8 cmdSECTOR_ERASE;
379 u8 cmdCHIP_ERASE;
380};
381
382/* Structure containing variables used by the shared code (atl2_hw.c) */
383struct atl2_hw {
384 u8 __iomem *hw_addr;
385 void *back;
386
387 u8 preamble_len;
388 u8 max_retry; /* Retransmission maximum, afterwards the
389 * packet will be discarded. */
390 u8 jam_ipg; /* IPG to start JAM for collision based flow
391 * control in half-duplex mode. In unit of
392 * 8-bit time. */
393 u8 ipgt; /* Desired back to back inter-packet gap. The
394 * default is 96-bit time. */
395 u8 min_ifg; /* Minimum number of IFG to enforce in between
396 * RX frames. Frame gap below such IFP is
397 * dropped. */
398 u8 ipgr1; /* 64bit Carrier-Sense window */
399 u8 ipgr2; /* 96-bit IPG window */
400 u8 retry_buf; /* When half-duplex mode, should hold some
401 * bytes for mac retry . (8*4bytes unit) */
402
403 u16 fc_rxd_hi;
404 u16 fc_rxd_lo;
405 u16 lcol; /* Collision Window */
406 u16 max_frame_size;
407
408 u16 MediaType;
409 u16 autoneg_advertised;
410 u16 pci_cmd_word;
411
412 u16 mii_autoneg_adv_reg;
413
414 u32 mem_rang;
415 u32 txcw;
416 u32 mc_filter_type;
417 u32 num_mc_addrs;
418 u32 collision_delta;
419 u32 tx_packet_delta;
420 u16 phy_spd_default;
421
422 u16 device_id;
423 u16 vendor_id;
424 u16 subsystem_id;
425 u16 subsystem_vendor_id;
426 u8 revision_id;
427
428 /* spi flash */
429 u8 flash_vendor;
430
431 u8 dma_fairness;
432 u8 mac_addr[NODE_ADDRESS_SIZE];
433 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
434
435 /* FIXME */
436 /* bool phy_preamble_sup; */
437 bool phy_configured;
438};
439
440#endif /* _ATL2_HW_H_ */
441
442struct atl2_ring_header {
443 /* pointer to the descriptor ring memory */
444 void *desc;
445 /* physical address of the descriptor ring */
446 dma_addr_t dma;
447 /* length of descriptor ring in bytes */
448 unsigned int size;
449};
450
451/* board specific private data structure */
452struct atl2_adapter {
453 /* OS defined structs */
454 struct net_device *netdev;
455 struct pci_dev *pdev;
456 u32 wol;
457 u16 link_speed;
458 u16 link_duplex;
459
460 spinlock_t stats_lock;
461
462 struct work_struct reset_task;
463 struct work_struct link_chg_task;
464 struct timer_list watchdog_timer;
465 struct timer_list phy_config_timer;
466
467 unsigned long cfg_phy;
468 bool mac_disabled;
469
470 /* All Descriptor memory */
471 dma_addr_t ring_dma;
472 void *ring_vir_addr;
473 int ring_size;
474
475 struct tx_pkt_header *txd_ring;
476 dma_addr_t txd_dma;
477
478 struct tx_pkt_status *txs_ring;
479 dma_addr_t txs_dma;
480
481 struct rx_desc *rxd_ring;
482 dma_addr_t rxd_dma;
483
484 u32 txd_ring_size; /* bytes per unit */
485 u32 txs_ring_size; /* dwords per unit */
486 u32 rxd_ring_size; /* 1536 bytes per unit */
487
488 /* read /write ptr: */
489 /* host */
490 u32 txd_write_ptr;
491 u32 txs_next_clear;
492 u32 rxd_read_ptr;
493
494 /* nic */
495 atomic_t txd_read_ptr;
496 atomic_t txs_write_ptr;
497 u32 rxd_write_ptr;
498
499 /* Interrupt Moderator timer ( 2us resolution) */
500 u16 imt;
501 /* Interrupt Clear timer (2us resolution) */
502 u16 ict;
503
504 unsigned long flags;
505 /* structs defined in atl2_hw.h */
506 u32 bd_number; /* board number */
507 bool pci_using_64;
508 bool have_msi;
509 struct atl2_hw hw;
510
511 u32 usr_cmd;
512 /* FIXME */
513 /* u32 regs_buff[ATL2_REGS_LEN]; */
514 u32 pci_state[16];
515
516 u32 *config_space;
517};
518
519enum atl2_state_t {
520 __ATL2_TESTING,
521 __ATL2_RESETTING,
522 __ATL2_DOWN
523};
524
525#endif /* _ATL2_H_ */
diff --git a/drivers/net/atlx/atlx.c b/drivers/net/atlx/atlx.c
new file mode 100644
index 00000000000..aabcf4b5745
--- /dev/null
+++ b/drivers/net/atlx/atlx.c
@@ -0,0 +1,269 @@
1/* atlx.c -- common functions for Attansic network drivers
2 *
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
6 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
7 *
8 * Derived from Intel e1000 driver
9 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 */
25
26/* Including this file like a header is a temporary hack, I promise. -- CHS */
27#ifndef ATLX_C
28#define ATLX_C
29
30#include <linux/device.h>
31#include <linux/errno.h>
32#include <linux/etherdevice.h>
33#include <linux/if.h>
34#include <linux/netdevice.h>
35#include <linux/socket.h>
36#include <linux/sockios.h>
37#include <linux/spinlock.h>
38#include <linux/string.h>
39#include <linux/types.h>
40#include <linux/workqueue.h>
41
42#include "atlx.h"
43
44static s32 atlx_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
45static u32 atlx_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
46static void atlx_set_mac_addr(struct atl1_hw *hw);
47
48static struct atlx_spi_flash_dev flash_table[] = {
49/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SEC_ERS CHIP_ERS */
50 {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
51 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
52 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
53};
54
55static int atlx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
56{
57 switch (cmd) {
58 case SIOCGMIIPHY:
59 case SIOCGMIIREG:
60 case SIOCSMIIREG:
61 return atlx_mii_ioctl(netdev, ifr, cmd);
62 default:
63 return -EOPNOTSUPP;
64 }
65}
66
67/*
68 * atlx_set_mac - Change the Ethernet Address of the NIC
69 * @netdev: network interface device structure
70 * @p: pointer to an address structure
71 *
72 * Returns 0 on success, negative on failure
73 */
74static int atlx_set_mac(struct net_device *netdev, void *p)
75{
76 struct atlx_adapter *adapter = netdev_priv(netdev);
77 struct sockaddr *addr = p;
78
79 if (netif_running(netdev))
80 return -EBUSY;
81
82 if (!is_valid_ether_addr(addr->sa_data))
83 return -EADDRNOTAVAIL;
84
85 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
86 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
87
88 atlx_set_mac_addr(&adapter->hw);
89 return 0;
90}
91
92static void atlx_check_for_link(struct atlx_adapter *adapter)
93{
94 struct net_device *netdev = adapter->netdev;
95 u16 phy_data = 0;
96
97 spin_lock(&adapter->lock);
98 adapter->phy_timer_pending = false;
99 atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
100 atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
101 spin_unlock(&adapter->lock);
102
103 /* notify upper layer link down ASAP */
104 if (!(phy_data & BMSR_LSTATUS)) {
105 /* Link Down */
106 if (netif_carrier_ok(netdev)) {
107 /* old link state: Up */
108 dev_info(&adapter->pdev->dev, "%s link is down\n",
109 netdev->name);
110 adapter->link_speed = SPEED_0;
111 netif_carrier_off(netdev);
112 }
113 }
114 schedule_work(&adapter->link_chg_task);
115}
116
117/*
118 * atlx_set_multi - Multicast and Promiscuous mode set
119 * @netdev: network interface device structure
120 *
121 * The set_multi entry point is called whenever the multicast address
122 * list or the network interface flags are updated. This routine is
123 * responsible for configuring the hardware for proper multicast,
124 * promiscuous mode, and all-multi behavior.
125 */
126static void atlx_set_multi(struct net_device *netdev)
127{
128 struct atlx_adapter *adapter = netdev_priv(netdev);
129 struct atlx_hw *hw = &adapter->hw;
130 struct netdev_hw_addr *ha;
131 u32 rctl;
132 u32 hash_value;
133
134 /* Check for Promiscuous and All Multicast modes */
135 rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
136 if (netdev->flags & IFF_PROMISC)
137 rctl |= MAC_CTRL_PROMIS_EN;
138 else if (netdev->flags & IFF_ALLMULTI) {
139 rctl |= MAC_CTRL_MC_ALL_EN;
140 rctl &= ~MAC_CTRL_PROMIS_EN;
141 } else
142 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
143
144 iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
145
146 /* clear the old settings from the multicast hash table */
147 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
148 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
149
150 /* compute mc addresses' hash value ,and put it into hash table */
151 netdev_for_each_mc_addr(ha, netdev) {
152 hash_value = atlx_hash_mc_addr(hw, ha->addr);
153 atlx_hash_set(hw, hash_value);
154 }
155}
156
157/*
158 * atlx_irq_enable - Enable default interrupt generation settings
159 * @adapter: board private structure
160 */
161static void atlx_irq_enable(struct atlx_adapter *adapter)
162{
163 iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
164 ioread32(adapter->hw.hw_addr + REG_IMR);
165}
166
167/*
168 * atlx_irq_disable - Mask off interrupt generation on the NIC
169 * @adapter: board private structure
170 */
171static void atlx_irq_disable(struct atlx_adapter *adapter)
172{
173 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
174 ioread32(adapter->hw.hw_addr + REG_IMR);
175 synchronize_irq(adapter->pdev->irq);
176}
177
178static void atlx_clear_phy_int(struct atlx_adapter *adapter)
179{
180 u16 phy_data;
181 unsigned long flags;
182
183 spin_lock_irqsave(&adapter->lock, flags);
184 atlx_read_phy_reg(&adapter->hw, 19, &phy_data);
185 spin_unlock_irqrestore(&adapter->lock, flags);
186}
187
188/*
189 * atlx_tx_timeout - Respond to a Tx Hang
190 * @netdev: network interface device structure
191 */
192static void atlx_tx_timeout(struct net_device *netdev)
193{
194 struct atlx_adapter *adapter = netdev_priv(netdev);
195 /* Do the reset outside of interrupt context */
196 schedule_work(&adapter->tx_timeout_task);
197}
198
199/*
200 * atlx_link_chg_task - deal with link change event Out of interrupt context
201 */
202static void atlx_link_chg_task(struct work_struct *work)
203{
204 struct atlx_adapter *adapter;
205 unsigned long flags;
206
207 adapter = container_of(work, struct atlx_adapter, link_chg_task);
208
209 spin_lock_irqsave(&adapter->lock, flags);
210 atlx_check_link(adapter);
211 spin_unlock_irqrestore(&adapter->lock, flags);
212}
213
214static void __atlx_vlan_mode(u32 features, u32 *ctrl)
215{
216 if (features & NETIF_F_HW_VLAN_RX) {
217 /* enable VLAN tag insert/strip */
218 *ctrl |= MAC_CTRL_RMV_VLAN;
219 } else {
220 /* disable VLAN tag insert/strip */
221 *ctrl &= ~MAC_CTRL_RMV_VLAN;
222 }
223}
224
225static void atlx_vlan_mode(struct net_device *netdev, u32 features)
226{
227 struct atlx_adapter *adapter = netdev_priv(netdev);
228 unsigned long flags;
229 u32 ctrl;
230
231 spin_lock_irqsave(&adapter->lock, flags);
232 /* atlx_irq_disable(adapter); FIXME: confirm/remove */
233 ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
234 __atlx_vlan_mode(features, &ctrl);
235 iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
236 /* atlx_irq_enable(adapter); FIXME */
237 spin_unlock_irqrestore(&adapter->lock, flags);
238}
239
240static void atlx_restore_vlan(struct atlx_adapter *adapter)
241{
242 atlx_vlan_mode(adapter->netdev, adapter->netdev->features);
243}
244
245static u32 atlx_fix_features(struct net_device *netdev, u32 features)
246{
247 /*
248 * Since there is no support for separate rx/tx vlan accel
249 * enable/disable make sure tx flag is always in same state as rx.
250 */
251 if (features & NETIF_F_HW_VLAN_RX)
252 features |= NETIF_F_HW_VLAN_TX;
253 else
254 features &= ~NETIF_F_HW_VLAN_TX;
255
256 return features;
257}
258
259static int atlx_set_features(struct net_device *netdev, u32 features)
260{
261 u32 changed = netdev->features ^ features;
262
263 if (changed & NETIF_F_HW_VLAN_RX)
264 atlx_vlan_mode(netdev, features);
265
266 return 0;
267}
268
269#endif /* ATLX_C */
diff --git a/drivers/net/atlx/atlx.h b/drivers/net/atlx/atlx.h
new file mode 100644
index 00000000000..14054b75aa6
--- /dev/null
+++ b/drivers/net/atlx/atlx.h
@@ -0,0 +1,503 @@
1/* atlx_hw.h -- common hardware definitions for Attansic network drivers
2 *
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
6 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
7 *
8 * Derived from Intel e1000 driver
9 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 */
25
26#ifndef ATLX_H
27#define ATLX_H
28
29#include <linux/module.h>
30#include <linux/types.h>
31
32#define ATLX_ERR_PHY 2
33#define ATLX_ERR_PHY_SPEED 7
34#define ATLX_ERR_PHY_RES 8
35
36#define SPEED_0 0xffff
37#define SPEED_10 10
38#define SPEED_100 100
39#define SPEED_1000 1000
40#define HALF_DUPLEX 1
41#define FULL_DUPLEX 2
42
43#define MEDIA_TYPE_AUTO_SENSOR 0
44
45/* register definitions */
46#define REG_PM_CTRLSTAT 0x44
47
48#define REG_PCIE_CAP_LIST 0x58
49
50#define REG_VPD_CAP 0x6C
51#define VPD_CAP_ID_MASK 0xFF
52#define VPD_CAP_ID_SHIFT 0
53#define VPD_CAP_NEXT_PTR_MASK 0xFF
54#define VPD_CAP_NEXT_PTR_SHIFT 8
55#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
56#define VPD_CAP_VPD_ADDR_SHIFT 16
57#define VPD_CAP_VPD_FLAG 0x80000000
58
59#define REG_VPD_DATA 0x70
60
61#define REG_SPI_FLASH_CTRL 0x200
62#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
63#define SPI_FLASH_CTRL_STS_WEN 0x2
64#define SPI_FLASH_CTRL_STS_WPEN 0x80
65#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
66#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
67#define SPI_FLASH_CTRL_INS_MASK 0x7
68#define SPI_FLASH_CTRL_INS_SHIFT 8
69#define SPI_FLASH_CTRL_START 0x800
70#define SPI_FLASH_CTRL_EN_VPD 0x2000
71#define SPI_FLASH_CTRL_LDSTART 0x8000
72#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
73#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
74#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
75#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
76#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
77#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
78#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
79#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
80#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
81#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
82#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
83#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
84#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
85
86#define REG_SPI_ADDR 0x204
87
88#define REG_SPI_DATA 0x208
89
90#define REG_SPI_FLASH_CONFIG 0x20C
91#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
92#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
93#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
94#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
95#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
96
97#define REG_SPI_FLASH_OP_PROGRAM 0x210
98#define REG_SPI_FLASH_OP_SC_ERASE 0x211
99#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
100#define REG_SPI_FLASH_OP_RDID 0x213
101#define REG_SPI_FLASH_OP_WREN 0x214
102#define REG_SPI_FLASH_OP_RDSR 0x215
103#define REG_SPI_FLASH_OP_WRSR 0x216
104#define REG_SPI_FLASH_OP_READ 0x217
105
106#define REG_TWSI_CTRL 0x218
107#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
108#define TWSI_CTRL_LD_OFFSET_SHIFT 0
109#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
110#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
111#define TWSI_CTRL_SW_LDSTART 0x800
112#define TWSI_CTRL_HW_LDSTART 0x1000
113#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
114#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
115#define TWSI_CTRL_LD_EXIST 0x400000
116#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
117#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
118#define TWSI_CTRL_FREQ_SEL_100K 0
119#define TWSI_CTRL_FREQ_SEL_200K 1
120#define TWSI_CTRL_FREQ_SEL_300K 2
121#define TWSI_CTRL_FREQ_SEL_400K 3
122#define TWSI_CTRL_SMB_SLV_ADDR /* FIXME: define or remove */
123#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
124#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
125
126#define REG_PCIE_DEV_MISC_CTRL 0x21C
127#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
128#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
129#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
130#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
131#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
132
133#define REG_PCIE_PHYMISC 0x1000
134#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
135
136#define REG_PCIE_DLL_TX_CTRL1 0x1104
137#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400
138#define PCIE_DLL_TX_CTRL1_DEF 0x568
139
140#define REG_LTSSM_TEST_MODE 0x12FC
141#define LTSSM_TEST_MODE_DEF 0x6500
142
143/* Master Control Register */
144#define REG_MASTER_CTRL 0x1400
145#define MASTER_CTRL_SOFT_RST 0x1
146#define MASTER_CTRL_MTIMER_EN 0x2
147#define MASTER_CTRL_ITIMER_EN 0x4
148#define MASTER_CTRL_MANUAL_INT 0x8
149#define MASTER_CTRL_REV_NUM_SHIFT 16
150#define MASTER_CTRL_REV_NUM_MASK 0xFF
151#define MASTER_CTRL_DEV_ID_SHIFT 24
152#define MASTER_CTRL_DEV_ID_MASK 0xFF
153
154/* Timer Initial Value Register */
155#define REG_MANUAL_TIMER_INIT 0x1404
156
157/* IRQ Moderator Timer Initial Value Register */
158#define REG_IRQ_MODU_TIMER_INIT 0x1408
159
160#define REG_PHY_ENABLE 0x140C
161
162/* IRQ Anti-Lost Timer Initial Value Register */
163#define REG_CMBDISDMA_TIMER 0x140E
164
165/* Block IDLE Status Register */
166#define REG_IDLE_STATUS 0x1410
167
168/* MDIO Control Register */
169#define REG_MDIO_CTRL 0x1414
170#define MDIO_DATA_MASK 0xFFFF
171#define MDIO_DATA_SHIFT 0
172#define MDIO_REG_ADDR_MASK 0x1F
173#define MDIO_REG_ADDR_SHIFT 16
174#define MDIO_RW 0x200000
175#define MDIO_SUP_PREAMBLE 0x400000
176#define MDIO_START 0x800000
177#define MDIO_CLK_SEL_SHIFT 24
178#define MDIO_CLK_25_4 0
179#define MDIO_CLK_25_6 2
180#define MDIO_CLK_25_8 3
181#define MDIO_CLK_25_10 4
182#define MDIO_CLK_25_14 5
183#define MDIO_CLK_25_20 6
184#define MDIO_CLK_25_28 7
185#define MDIO_BUSY 0x8000000
186
187/* MII PHY Status Register */
188#define REG_PHY_STATUS 0x1418
189
190/* BIST Control and Status Register0 (for the Packet Memory) */
191#define REG_BIST0_CTRL 0x141C
192#define BIST0_NOW 0x1
193#define BIST0_SRAM_FAIL 0x2
194#define BIST0_FUSE_FLAG 0x4
195#define REG_BIST1_CTRL 0x1420
196#define BIST1_NOW 0x1
197#define BIST1_SRAM_FAIL 0x2
198#define BIST1_FUSE_FLAG 0x4
199
200/* SerDes Lock Detect Control and Status Register */
201#define REG_SERDES_LOCK 0x1424
202#define SERDES_LOCK_DETECT 1
203#define SERDES_LOCK_DETECT_EN 2
204
205/* MAC Control Register */
206#define REG_MAC_CTRL 0x1480
207#define MAC_CTRL_TX_EN 1
208#define MAC_CTRL_RX_EN 2
209#define MAC_CTRL_TX_FLOW 4
210#define MAC_CTRL_RX_FLOW 8
211#define MAC_CTRL_LOOPBACK 0x10
212#define MAC_CTRL_DUPLX 0x20
213#define MAC_CTRL_ADD_CRC 0x40
214#define MAC_CTRL_PAD 0x80
215#define MAC_CTRL_LENCHK 0x100
216#define MAC_CTRL_HUGE_EN 0x200
217#define MAC_CTRL_PRMLEN_SHIFT 10
218#define MAC_CTRL_PRMLEN_MASK 0xF
219#define MAC_CTRL_RMV_VLAN 0x4000
220#define MAC_CTRL_PROMIS_EN 0x8000
221#define MAC_CTRL_MC_ALL_EN 0x2000000
222#define MAC_CTRL_BC_EN 0x4000000
223
224/* MAC IPG/IFG Control Register */
225#define REG_MAC_IPG_IFG 0x1484
226#define MAC_IPG_IFG_IPGT_SHIFT 0
227#define MAC_IPG_IFG_IPGT_MASK 0x7F
228#define MAC_IPG_IFG_MIFG_SHIFT 8
229#define MAC_IPG_IFG_MIFG_MASK 0xFF
230#define MAC_IPG_IFG_IPGR1_SHIFT 16
231#define MAC_IPG_IFG_IPGR1_MASK 0x7F
232#define MAC_IPG_IFG_IPGR2_SHIFT 24
233#define MAC_IPG_IFG_IPGR2_MASK 0x7F
234
235/* MAC STATION ADDRESS */
236#define REG_MAC_STA_ADDR 0x1488
237
238/* Hash table for multicast address */
239#define REG_RX_HASH_TABLE 0x1490
240
241/* MAC Half-Duplex Control Register */
242#define REG_MAC_HALF_DUPLX_CTRL 0x1498
243#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
244#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3FF
245#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
246#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xF
247#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
248#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
249#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
250#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
251#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
252#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xF
253#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
254#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xF
255
256/* Maximum Frame Length Control Register */
257#define REG_MTU 0x149C
258
259/* Wake-On-Lan control register */
260#define REG_WOL_CTRL 0x14A0
261#define WOL_PATTERN_EN 0x1
262#define WOL_PATTERN_PME_EN 0x2
263#define WOL_MAGIC_EN 0x4
264#define WOL_MAGIC_PME_EN 0x8
265#define WOL_LINK_CHG_EN 0x10
266#define WOL_LINK_CHG_PME_EN 0x20
267#define WOL_PATTERN_ST 0x100
268#define WOL_MAGIC_ST 0x200
269#define WOL_LINKCHG_ST 0x400
270#define WOL_PT0_EN 0x10000
271#define WOL_PT1_EN 0x20000
272#define WOL_PT2_EN 0x40000
273#define WOL_PT3_EN 0x80000
274#define WOL_PT4_EN 0x100000
275#define WOL_PT0_MATCH 0x1000000
276#define WOL_PT1_MATCH 0x2000000
277#define WOL_PT2_MATCH 0x4000000
278#define WOL_PT3_MATCH 0x8000000
279#define WOL_PT4_MATCH 0x10000000
280
281/* Internal SRAM Partition Register, high 32 bits */
282#define REG_SRAM_RFD_ADDR 0x1500
283
284/* Descriptor Control register, high 32 bits */
285#define REG_DESC_BASE_ADDR_HI 0x1540
286
287/* Interrupt Status Register */
288#define REG_ISR 0x1600
289#define ISR_UR_DETECTED 0x1000000
290#define ISR_FERR_DETECTED 0x2000000
291#define ISR_NFERR_DETECTED 0x4000000
292#define ISR_CERR_DETECTED 0x8000000
293#define ISR_PHY_LINKDOWN 0x10000000
294#define ISR_DIS_INT 0x80000000
295
296/* Interrupt Mask Register */
297#define REG_IMR 0x1604
298
299#define REG_RFD_RRD_IDX 0x1800
300#define REG_TPD_IDX 0x1804
301
302/* MII definitions */
303
304/* PHY Common Register */
305#define MII_ATLX_CR 0x09
306#define MII_ATLX_SR 0x0A
307#define MII_ATLX_ESR 0x0F
308#define MII_ATLX_PSCR 0x10
309#define MII_ATLX_PSSR 0x11
310
311/* PHY Control Register */
312#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100,
313 * 00=10
314 */
315#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
316#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
317#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
318#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
319#define MII_CR_POWER_DOWN 0x0800 /* Power down */
320#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
321#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100,
322 * 00=10
323 */
324#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
325#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
326#define MII_CR_SPEED_MASK 0x2040
327#define MII_CR_SPEED_1000 0x0040
328#define MII_CR_SPEED_100 0x2000
329#define MII_CR_SPEED_10 0x0000
330
331/* PHY Status Register */
332#define MII_SR_EXTENDED_CAPS 0x0001 /* Ext register capabilities */
333#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
334#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
335#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
336#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
337#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
338#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
339#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext stat info in Reg 0x0F */
340#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
341#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
342#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
343#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
344#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
345#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
346#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
347
348/* Link partner ability register */
349#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
350#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
351#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
352#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
353#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
354#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
355#define MII_LPA_PAUSE 0x0400 /* PAUSE */
356#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
357#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
358#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
359#define MII_LPA_NPAGE 0x8000 /* Next page bit */
360
361/* Autoneg Advertisement Register */
362#define MII_AR_SELECTOR_FIELD 0x0001 /* IEEE 802.3 CSMA/CD */
363#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
364#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
365#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
366#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
367#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
368#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
369#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Dir bit */
370#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
371#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability support */
372#define MII_AR_SPEED_MASK 0x01E0
373#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
374
375/* 1000BASE-T Control Register */
376#define MII_ATLX_CR_1000T_HD_CAPS 0x0100 /* Adv 1000T HD cap */
377#define MII_ATLX_CR_1000T_FD_CAPS 0x0200 /* Adv 1000T FD cap */
378#define MII_ATLX_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device,
379 * 0=DTE device */
380#define MII_ATLX_CR_1000T_MS_VALUE 0x0800 /* 1=Config PHY as Master,
381 * 0=Configure PHY as Slave */
382#define MII_ATLX_CR_1000T_MS_ENABLE 0x1000 /* 1=Man Master/Slave config,
383 * 0=Auto Master/Slave config
384 */
385#define MII_ATLX_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
386#define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
387#define MII_ATLX_CR_1000T_TEST_MODE_2 0x4000 /* Master Xmit Jitter test */
388#define MII_ATLX_CR_1000T_TEST_MODE_3 0x6000 /* Slave Xmit Jitter test */
389#define MII_ATLX_CR_1000T_TEST_MODE_4 0x8000 /* Xmitter Distortion test */
390#define MII_ATLX_CR_1000T_SPEED_MASK 0x0300
391#define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK 0x0300
392
393/* 1000BASE-T Status Register */
394#define MII_ATLX_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
395#define MII_ATLX_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
396#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
397#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
398#define MII_ATLX_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master
399 * 0=Slave
400 */
401#define MII_ATLX_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config
402 * fault */
403#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
404#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
405
406/* Extended Status Register */
407#define MII_ATLX_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
408#define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
409#define MII_ATLX_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
410#define MII_ATLX_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
411
412/* ATLX PHY Specific Control Register */
413#define MII_ATLX_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Func disabled */
414#define MII_ATLX_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enbld */
415#define MII_ATLX_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
416#define MII_ATLX_PSCR_MAC_POWERDOWN 0x0008
417#define MII_ATLX_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low
418 * 0=CLK125 toggling
419 */
420#define MII_ATLX_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5,
421 * Manual MDI configuration
422 */
423#define MII_ATLX_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
424#define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover
425 * 100BASE-TX/10BASE-T: MDI
426 * Mode */
427#define MII_ATLX_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
428 * all speeds.
429 */
430#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended
431 * 10BASE-T distance
432 * (Lower 10BASE-T RX
433 * Threshold)
434 * 0=Normal 10BASE-T RX
435 * Threshold
436 */
437#define MII_ATLX_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in
438 * 100BASE-TX
439 * 0=MII interface in
440 * 100BASE-TX
441 */
442#define MII_ATLX_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler dsbl */
443#define MII_ATLX_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
444#define MII_ATLX_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
445#define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT 1
446#define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT 5
447#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
448
449/* ATLX PHY Specific Status Register */
450#define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
451#define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
452#define MII_ATLX_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
453#define MII_ATLX_PSSR_10MBS 0x0000 /* 00=10Mbs */
454#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */
455#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
456
457#define MII_DBG_ADDR 0x1D
458#define MII_DBG_DATA 0x1E
459
460/* PCI Command Register Bit Definitions */
461#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
462#define CMD_IO_SPACE 0x0001
463#define CMD_MEMORY_SPACE 0x0002
464#define CMD_BUS_MASTER 0x0004
465
466/* Wake Up Filter Control */
467#define ATLX_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
468#define ATLX_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
469#define ATLX_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
470#define ATLX_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
471#define ATLX_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
472
473#define ADVERTISE_10_HALF 0x0001
474#define ADVERTISE_10_FULL 0x0002
475#define ADVERTISE_100_HALF 0x0004
476#define ADVERTISE_100_FULL 0x0008
477#define ADVERTISE_1000_HALF 0x0010
478#define ADVERTISE_1000_FULL 0x0020
479#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
480#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
481
482#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
483#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
484
485/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */
486#define EEPROM_SUM 0xBABA
487#define NODE_ADDRESS_SIZE 6
488
489struct atlx_spi_flash_dev {
490 const char *manu_name; /* manufacturer id */
491 /* op-code */
492 u8 cmd_wrsr;
493 u8 cmd_read;
494 u8 cmd_program;
495 u8 cmd_wren;
496 u8 cmd_wrdi;
497 u8 cmd_rdsr;
498 u8 cmd_rdid;
499 u8 cmd_sector_erase;
500 u8 cmd_chip_erase;
501};
502
503#endif /* ATLX_H */
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