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authorHuang Shijie <b32955@freescale.com>2011-09-07 22:47:10 -0400
committerArtem Bityutskiy <artem.bityutskiy@intel.com>2011-09-11 08:02:18 -0400
commit45dfc1a09a35963234a50617c0700f7eb2b3b9c2 (patch)
tree413aff3a31a8e68d4aab0f3c3474d914f09aff4a /drivers/mtd/nand
parent4d523b60ef9d1953d9e12745ca0ed3e2dc98c189 (diff)
mtd: add helper functions library and header files for GPMI NAND driver
bch-regs.h : registers file for BCH module gpmi-regs.h: registers file for GPMI module gpmi-lib.c: helper functions library. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Tested-by: Koen Beel <koen.beel@barco.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
Diffstat (limited to 'drivers/mtd/nand')
-rw-r--r--drivers/mtd/nand/gpmi-nand/bch-regs.h84
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-lib.c1057
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-regs.h172
3 files changed, 1313 insertions, 0 deletions
diff --git a/drivers/mtd/nand/gpmi-nand/bch-regs.h b/drivers/mtd/nand/gpmi-nand/bch-regs.h
new file mode 100644
index 00000000000..4effb8c579d
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nand/bch-regs.h
@@ -0,0 +1,84 @@
1/*
2 * Freescale GPMI NAND Flash Driver
3 *
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21#ifndef __GPMI_NAND_BCH_REGS_H
22#define __GPMI_NAND_BCH_REGS_H
23
24#define HW_BCH_CTRL 0x00000000
25#define HW_BCH_CTRL_SET 0x00000004
26#define HW_BCH_CTRL_CLR 0x00000008
27#define HW_BCH_CTRL_TOG 0x0000000c
28
29#define BM_BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
30#define BM_BCH_CTRL_COMPLETE_IRQ (1 << 0)
31
32#define HW_BCH_STATUS0 0x00000010
33#define HW_BCH_MODE 0x00000020
34#define HW_BCH_ENCODEPTR 0x00000030
35#define HW_BCH_DATAPTR 0x00000040
36#define HW_BCH_METAPTR 0x00000050
37#define HW_BCH_LAYOUTSELECT 0x00000070
38
39#define HW_BCH_FLASH0LAYOUT0 0x00000080
40
41#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
42#define BM_BCH_FLASH0LAYOUT0_NBLOCKS (0xff << BP_BCH_FLASH0LAYOUT0_NBLOCKS)
43#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
44 (((v) << BP_BCH_FLASH0LAYOUT0_NBLOCKS) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
45
46#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
47#define BM_BCH_FLASH0LAYOUT0_META_SIZE (0xff << BP_BCH_FLASH0LAYOUT0_META_SIZE)
48#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \
49 (((v) << BP_BCH_FLASH0LAYOUT0_META_SIZE)\
50 & BM_BCH_FLASH0LAYOUT0_META_SIZE)
51
52#define BP_BCH_FLASH0LAYOUT0_ECC0 12
53#define BM_BCH_FLASH0LAYOUT0_ECC0 (0xf << BP_BCH_FLASH0LAYOUT0_ECC0)
54#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \
55 (((v) << BP_BCH_FLASH0LAYOUT0_ECC0) & BM_BCH_FLASH0LAYOUT0_ECC0)
56
57#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
58#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE \
59 (0xfff << BP_BCH_FLASH0LAYOUT0_DATA0_SIZE)
60#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \
61 (((v) << BP_BCH_FLASH0LAYOUT0_DATA0_SIZE)\
62 & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
63
64#define HW_BCH_FLASH0LAYOUT1 0x00000090
65
66#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
67#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE \
68 (0xffff << BP_BCH_FLASH0LAYOUT1_PAGE_SIZE)
69#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
70 (((v) << BP_BCH_FLASH0LAYOUT1_PAGE_SIZE) \
71 & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
72
73#define BP_BCH_FLASH0LAYOUT1_ECCN 12
74#define BM_BCH_FLASH0LAYOUT1_ECCN (0xf << BP_BCH_FLASH0LAYOUT1_ECCN)
75#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \
76 (((v) << BP_BCH_FLASH0LAYOUT1_ECCN) & BM_BCH_FLASH0LAYOUT1_ECCN)
77
78#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
79#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE \
80 (0xfff << BP_BCH_FLASH0LAYOUT1_DATAN_SIZE)
81#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \
82 (((v) << BP_BCH_FLASH0LAYOUT1_DATAN_SIZE) \
83 & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
84#endif
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
new file mode 100644
index 00000000000..de4db7604a3
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -0,0 +1,1057 @@
1/*
2 * Freescale GPMI NAND Flash Driver
3 *
4 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
5 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21#include <linux/mtd/gpmi-nand.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <mach/mxs.h>
25
26#include "gpmi-nand.h"
27#include "gpmi-regs.h"
28#include "bch-regs.h"
29
30struct timing_threshod timing_default_threshold = {
31 .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
32 BP_GPMI_TIMING0_DATA_SETUP),
33 .internal_data_setup_in_ns = 0,
34 .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
35 BP_GPMI_CTRL1_RDN_DELAY),
36 .max_dll_clock_period_in_ns = 32,
37 .max_dll_delay_in_ns = 16,
38};
39
40/*
41 * Clear the bit and poll it cleared. This is usually called with
42 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
43 * (bit 30).
44 */
45static int clear_poll_bit(void __iomem *addr, u32 mask)
46{
47 int timeout = 0x400;
48
49 /* clear the bit */
50 __mxs_clrl(mask, addr);
51
52 /*
53 * SFTRST needs 3 GPMI clocks to settle, the reference manual
54 * recommends to wait 1us.
55 */
56 udelay(1);
57
58 /* poll the bit becoming clear */
59 while ((readl(addr) & mask) && --timeout)
60 /* nothing */;
61
62 return !timeout;
63}
64
65#define MODULE_CLKGATE (1 << 30)
66#define MODULE_SFTRST (1 << 31)
67/*
68 * The current mxs_reset_block() will do two things:
69 * [1] enable the module.
70 * [2] reset the module.
71 *
72 * In most of the cases, it's ok. But there is a hardware bug in the BCH block.
73 * If you try to soft reset the BCH block, it becomes unusable until
74 * the next hard reset. This case occurs in the NAND boot mode. When the board
75 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
76 * So If the driver tries to reset the BCH again, the BCH will not work anymore.
77 * You will see a DMA timeout in this case.
78 *
79 * To avoid this bug, just add a new parameter `just_enable` for
80 * the mxs_reset_block(), and rewrite it here.
81 */
82int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
83{
84 int ret;
85 int timeout = 0x400;
86
87 /* clear and poll SFTRST */
88 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
89 if (unlikely(ret))
90 goto error;
91
92 /* clear CLKGATE */
93 __mxs_clrl(MODULE_CLKGATE, reset_addr);
94
95 if (!just_enable) {
96 /* set SFTRST to reset the block */
97 __mxs_setl(MODULE_SFTRST, reset_addr);
98 udelay(1);
99
100 /* poll CLKGATE becoming set */
101 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
102 /* nothing */;
103 if (unlikely(!timeout))
104 goto error;
105 }
106
107 /* clear and poll SFTRST */
108 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
109 if (unlikely(ret))
110 goto error;
111
112 /* clear and poll CLKGATE */
113 ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
114 if (unlikely(ret))
115 goto error;
116
117 return 0;
118
119error:
120 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
121 return -ETIMEDOUT;
122}
123
124int gpmi_init(struct gpmi_nand_data *this)
125{
126 struct resources *r = &this->resources;
127 int ret;
128
129 ret = clk_enable(r->clock);
130 if (ret)
131 goto err_out;
132 ret = gpmi_reset_block(r->gpmi_regs, false);
133 if (ret)
134 goto err_out;
135
136 /* Choose NAND mode. */
137 writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
138
139 /* Set the IRQ polarity. */
140 writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
141 r->gpmi_regs + HW_GPMI_CTRL1_SET);
142
143 /* Disable Write-Protection. */
144 writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
145
146 /* Select BCH ECC. */
147 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
148
149 clk_disable(r->clock);
150 return 0;
151err_out:
152 return ret;
153}
154
155/* This function is very useful. It is called only when the bug occur. */
156void gpmi_dump_info(struct gpmi_nand_data *this)
157{
158 struct resources *r = &this->resources;
159 struct bch_geometry *geo = &this->bch_geometry;
160 u32 reg;
161 int i;
162
163 pr_err("Show GPMI registers :\n");
164 for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
165 reg = readl(r->gpmi_regs + i * 0x10);
166 pr_err("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
167 }
168
169 /* start to print out the BCH info */
170 pr_err("BCH Geometry :\n");
171 pr_err("GF length : %u\n", geo->gf_len);
172 pr_err("ECC Strength : %u\n", geo->ecc_strength);
173 pr_err("Page Size in Bytes : %u\n", geo->page_size);
174 pr_err("Metadata Size in Bytes : %u\n", geo->metadata_size);
175 pr_err("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size);
176 pr_err("ECC Chunk Count : %u\n", geo->ecc_chunk_count);
177 pr_err("Payload Size in Bytes : %u\n", geo->payload_size);
178 pr_err("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size);
179 pr_err("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
180 pr_err("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
181 pr_err("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset);
182}
183
184/* Configures the geometry for BCH. */
185int bch_set_geometry(struct gpmi_nand_data *this)
186{
187 struct resources *r = &this->resources;
188 struct bch_geometry *bch_geo = &this->bch_geometry;
189 unsigned int block_count;
190 unsigned int block_size;
191 unsigned int metadata_size;
192 unsigned int ecc_strength;
193 unsigned int page_size;
194 int ret;
195
196 if (common_nfc_set_geometry(this))
197 return !0;
198
199 block_count = bch_geo->ecc_chunk_count - 1;
200 block_size = bch_geo->ecc_chunk_size;
201 metadata_size = bch_geo->metadata_size;
202 ecc_strength = bch_geo->ecc_strength >> 1;
203 page_size = bch_geo->page_size;
204
205 ret = clk_enable(r->clock);
206 if (ret)
207 goto err_out;
208
209 ret = gpmi_reset_block(r->bch_regs, true);
210 if (ret)
211 goto err_out;
212
213 /* Configure layout 0. */
214 writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
215 | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
216 | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)
217 | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size),
218 r->bch_regs + HW_BCH_FLASH0LAYOUT0);
219
220 writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
221 | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)
222 | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size),
223 r->bch_regs + HW_BCH_FLASH0LAYOUT1);
224
225 /* Set *all* chip selects to use layout 0. */
226 writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
227
228 /* Enable interrupts. */
229 writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
230 r->bch_regs + HW_BCH_CTRL_SET);
231
232 clk_disable(r->clock);
233 return 0;
234err_out:
235 return ret;
236}
237
238/* Converts time in nanoseconds to cycles. */
239static unsigned int ns_to_cycles(unsigned int time,
240 unsigned int period, unsigned int min)
241{
242 unsigned int k;
243
244 k = (time + period - 1) / period;
245 return max(k, min);
246}
247
248/* Apply timing to current hardware conditions. */
249static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
250 struct gpmi_nfc_hardware_timing *hw)
251{
252 struct gpmi_nand_platform_data *pdata = this->pdata;
253 struct timing_threshod *nfc = &timing_default_threshold;
254 struct nand_chip *nand = &this->nand;
255 struct nand_timing target = this->timing;
256 bool improved_timing_is_available;
257 unsigned long clock_frequency_in_hz;
258 unsigned int clock_period_in_ns;
259 bool dll_use_half_periods;
260 unsigned int dll_delay_shift;
261 unsigned int max_sample_delay_in_ns;
262 unsigned int address_setup_in_cycles;
263 unsigned int data_setup_in_ns;
264 unsigned int data_setup_in_cycles;
265 unsigned int data_hold_in_cycles;
266 int ideal_sample_delay_in_ns;
267 unsigned int sample_delay_factor;
268 int tEYE;
269 unsigned int min_prop_delay_in_ns = pdata->min_prop_delay_in_ns;
270 unsigned int max_prop_delay_in_ns = pdata->max_prop_delay_in_ns;
271
272 /*
273 * If there are multiple chips, we need to relax the timings to allow
274 * for signal distortion due to higher capacitance.
275 */
276 if (nand->numchips > 2) {
277 target.data_setup_in_ns += 10;
278 target.data_hold_in_ns += 10;
279 target.address_setup_in_ns += 10;
280 } else if (nand->numchips > 1) {
281 target.data_setup_in_ns += 5;
282 target.data_hold_in_ns += 5;
283 target.address_setup_in_ns += 5;
284 }
285
286 /* Check if improved timing information is available. */
287 improved_timing_is_available =
288 (target.tREA_in_ns >= 0) &&
289 (target.tRLOH_in_ns >= 0) &&
290 (target.tRHOH_in_ns >= 0) ;
291
292 /* Inspect the clock. */
293 clock_frequency_in_hz = nfc->clock_frequency_in_hz;
294 clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
295
296 /*
297 * The NFC quantizes setup and hold parameters in terms of clock cycles.
298 * Here, we quantize the setup and hold timing parameters to the
299 * next-highest clock period to make sure we apply at least the
300 * specified times.
301 *
302 * For data setup and data hold, the hardware interprets a value of zero
303 * as the largest possible delay. This is not what's intended by a zero
304 * in the input parameter, so we impose a minimum of one cycle.
305 */
306 data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns,
307 clock_period_in_ns, 1);
308 data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns,
309 clock_period_in_ns, 1);
310 address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
311 clock_period_in_ns, 0);
312
313 /*
314 * The clock's period affects the sample delay in a number of ways:
315 *
316 * (1) The NFC HAL tells us the maximum clock period the sample delay
317 * DLL can tolerate. If the clock period is greater than half that
318 * maximum, we must configure the DLL to be driven by half periods.
319 *
320 * (2) We need to convert from an ideal sample delay, in ns, to a
321 * "sample delay factor," which the NFC uses. This factor depends on
322 * whether we're driving the DLL with full or half periods.
323 * Paraphrasing the reference manual:
324 *
325 * AD = SDF x 0.125 x RP
326 *
327 * where:
328 *
329 * AD is the applied delay, in ns.
330 * SDF is the sample delay factor, which is dimensionless.
331 * RP is the reference period, in ns, which is a full clock period
332 * if the DLL is being driven by full periods, or half that if
333 * the DLL is being driven by half periods.
334 *
335 * Let's re-arrange this in a way that's more useful to us:
336 *
337 * 8
338 * SDF = AD x ----
339 * RP
340 *
341 * The reference period is either the clock period or half that, so this
342 * is:
343 *
344 * 8 AD x DDF
345 * SDF = AD x ----- = --------
346 * f x P P
347 *
348 * where:
349 *
350 * f is 1 or 1/2, depending on how we're driving the DLL.
351 * P is the clock period.
352 * DDF is the DLL Delay Factor, a dimensionless value that
353 * incorporates all the constants in the conversion.
354 *
355 * DDF will be either 8 or 16, both of which are powers of two. We can
356 * reduce the cost of this conversion by using bit shifts instead of
357 * multiplication or division. Thus:
358 *
359 * AD << DDS
360 * SDF = ---------
361 * P
362 *
363 * or
364 *
365 * AD = (SDF >> DDS) x P
366 *
367 * where:
368 *
369 * DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF.
370 */
371 if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
372 dll_use_half_periods = true;
373 dll_delay_shift = 3 + 1;
374 } else {
375 dll_use_half_periods = false;
376 dll_delay_shift = 3;
377 }
378
379 /*
380 * Compute the maximum sample delay the NFC allows, under current
381 * conditions. If the clock is running too slowly, no sample delay is
382 * possible.
383 */
384 if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
385 max_sample_delay_in_ns = 0;
386 else {
387 /*
388 * Compute the delay implied by the largest sample delay factor
389 * the NFC allows.
390 */
391 max_sample_delay_in_ns =
392 (nfc->max_sample_delay_factor * clock_period_in_ns) >>
393 dll_delay_shift;
394
395 /*
396 * Check if the implied sample delay larger than the NFC
397 * actually allows.
398 */
399 if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
400 max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
401 }
402
403 /*
404 * Check if improved timing information is available. If not, we have to
405 * use a less-sophisticated algorithm.
406 */
407 if (!improved_timing_is_available) {
408 /*
409 * Fold the read setup time required by the NFC into the ideal
410 * sample delay.
411 */
412 ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
413 nfc->internal_data_setup_in_ns;
414
415 /*
416 * The ideal sample delay may be greater than the maximum
417 * allowed by the NFC. If so, we can trade off sample delay time
418 * for more data setup time.
419 *
420 * In each iteration of the following loop, we add a cycle to
421 * the data setup time and subtract a corresponding amount from
422 * the sample delay until we've satisified the constraints or
423 * can't do any better.
424 */
425 while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
426 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
427
428 data_setup_in_cycles++;
429 ideal_sample_delay_in_ns -= clock_period_in_ns;
430
431 if (ideal_sample_delay_in_ns < 0)
432 ideal_sample_delay_in_ns = 0;
433
434 }
435
436 /*
437 * Compute the sample delay factor that corresponds most closely
438 * to the ideal sample delay. If the result is too large for the
439 * NFC, use the maximum value.
440 *
441 * Notice that we use the ns_to_cycles function to compute the
442 * sample delay factor. We do this because the form of the
443 * computation is the same as that for calculating cycles.
444 */
445 sample_delay_factor =
446 ns_to_cycles(
447 ideal_sample_delay_in_ns << dll_delay_shift,
448 clock_period_in_ns, 0);
449
450 if (sample_delay_factor > nfc->max_sample_delay_factor)
451 sample_delay_factor = nfc->max_sample_delay_factor;
452
453 /* Skip to the part where we return our results. */
454 goto return_results;
455 }
456
457 /*
458 * If control arrives here, we have more detailed timing information,
459 * so we can use a better algorithm.
460 */
461
462 /*
463 * Fold the read setup time required by the NFC into the maximum
464 * propagation delay.
465 */
466 max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
467
468 /*
469 * Earlier, we computed the number of clock cycles required to satisfy
470 * the data setup time. Now, we need to know the actual nanoseconds.
471 */
472 data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
473
474 /*
475 * Compute tEYE, the width of the data eye when reading from the NAND
476 * Flash. The eye width is fundamentally determined by the data setup
477 * time, perturbed by propagation delays and some characteristics of the
478 * NAND Flash device.
479 *
480 * start of the eye = max_prop_delay + tREA
481 * end of the eye = min_prop_delay + tRHOH + data_setup
482 */
483 tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
484 (int)data_setup_in_ns;
485
486 tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
487
488 /*
489 * The eye must be open. If it's not, we can try to open it by
490 * increasing its main forcer, the data setup time.
491 *
492 * In each iteration of the following loop, we increase the data setup
493 * time by a single clock cycle. We do this until either the eye is
494 * open or we run into NFC limits.
495 */
496 while ((tEYE <= 0) &&
497 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
498 /* Give a cycle to data setup. */
499 data_setup_in_cycles++;
500 /* Synchronize the data setup time with the cycles. */
501 data_setup_in_ns += clock_period_in_ns;
502 /* Adjust tEYE accordingly. */
503 tEYE += clock_period_in_ns;
504 }
505
506 /*
507 * When control arrives here, the eye is open. The ideal time to sample
508 * the data is in the center of the eye:
509 *
510 * end of the eye + start of the eye
511 * --------------------------------- - data_setup
512 * 2
513 *
514 * After some algebra, this simplifies to the code immediately below.
515 */
516 ideal_sample_delay_in_ns =
517 ((int)max_prop_delay_in_ns +
518 (int)target.tREA_in_ns +
519 (int)min_prop_delay_in_ns +
520 (int)target.tRHOH_in_ns -
521 (int)data_setup_in_ns) >> 1;
522
523 /*
524 * The following figure illustrates some aspects of a NAND Flash read:
525 *
526 *
527 * __ _____________________________________
528 * RDN \_________________/
529 *
530 * <---- tEYE ----->
531 * /-----------------\
532 * Read Data ----------------------------< >---------
533 * \-----------------/
534 * ^ ^ ^ ^
535 * | | | |
536 * |<--Data Setup -->|<--Delay Time -->| |
537 * | | | |
538 * | | |
539 * | |<-- Quantized Delay Time -->|
540 * | | |
541 *
542 *
543 * We have some issues we must now address:
544 *
545 * (1) The *ideal* sample delay time must not be negative. If it is, we
546 * jam it to zero.
547 *
548 * (2) The *ideal* sample delay time must not be greater than that
549 * allowed by the NFC. If it is, we can increase the data setup
550 * time, which will reduce the delay between the end of the data
551 * setup and the center of the eye. It will also make the eye
552 * larger, which might help with the next issue...
553 *
554 * (3) The *quantized* sample delay time must not fall either before the
555 * eye opens or after it closes (the latter is the problem
556 * illustrated in the above figure).
557 */
558
559 /* Jam a negative ideal sample delay to zero. */
560 if (ideal_sample_delay_in_ns < 0)
561 ideal_sample_delay_in_ns = 0;
562
563 /*
564 * Extend the data setup as needed to reduce the ideal sample delay
565 * below the maximum permitted by the NFC.
566 */
567 while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
568 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
569
570 /* Give a cycle to data setup. */
571 data_setup_in_cycles++;
572 /* Synchronize the data setup time with the cycles. */
573 data_setup_in_ns += clock_period_in_ns;
574 /* Adjust tEYE accordingly. */
575 tEYE += clock_period_in_ns;
576
577 /*
578 * Decrease the ideal sample delay by one half cycle, to keep it
579 * in the middle of the eye.
580 */
581 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
582
583 /* Jam a negative ideal sample delay to zero. */
584 if (ideal_sample_delay_in_ns < 0)
585 ideal_sample_delay_in_ns = 0;
586 }
587
588 /*
589 * Compute the sample delay factor that corresponds to the ideal sample
590 * delay. If the result is too large, then use the maximum allowed
591 * value.
592 *
593 * Notice that we use the ns_to_cycles function to compute the sample
594 * delay factor. We do this because the form of the computation is the
595 * same as that for calculating cycles.
596 */
597 sample_delay_factor =
598 ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
599 clock_period_in_ns, 0);
600
601 if (sample_delay_factor > nfc->max_sample_delay_factor)
602 sample_delay_factor = nfc->max_sample_delay_factor;
603
604 /*
605 * These macros conveniently encapsulate a computation we'll use to
606 * continuously evaluate whether or not the data sample delay is inside
607 * the eye.
608 */
609 #define IDEAL_DELAY ((int) ideal_sample_delay_in_ns)
610
611 #define QUANTIZED_DELAY \
612 ((int) ((sample_delay_factor * clock_period_in_ns) >> \
613 dll_delay_shift))
614
615 #define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY))
616
617 #define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1))
618
619 /*
620 * While the quantized sample time falls outside the eye, reduce the
621 * sample delay or extend the data setup to move the sampling point back
622 * toward the eye. Do not allow the number of data setup cycles to
623 * exceed the maximum allowed by the NFC.
624 */
625 while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
626 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
627 /*
628 * If control arrives here, the quantized sample delay falls
629 * outside the eye. Check if it's before the eye opens, or after
630 * the eye closes.
631 */
632 if (QUANTIZED_DELAY > IDEAL_DELAY) {
633 /*
634 * If control arrives here, the quantized sample delay
635 * falls after the eye closes. Decrease the quantized
636 * delay time and then go back to re-evaluate.
637 */
638 if (sample_delay_factor != 0)
639 sample_delay_factor--;
640 continue;
641 }
642
643 /*
644 * If control arrives here, the quantized sample delay falls
645 * before the eye opens. Shift the sample point by increasing
646 * data setup time. This will also make the eye larger.
647 */
648
649 /* Give a cycle to data setup. */
650 data_setup_in_cycles++;
651 /* Synchronize the data setup time with the cycles. */
652 data_setup_in_ns += clock_period_in_ns;
653 /* Adjust tEYE accordingly. */
654 tEYE += clock_period_in_ns;
655
656 /*
657 * Decrease the ideal sample delay by one half cycle, to keep it
658 * in the middle of the eye.
659 */
660 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
661
662 /* ...and one less period for the delay time. */
663 ideal_sample_delay_in_ns -= clock_period_in_ns;
664
665 /* Jam a negative ideal sample delay to zero. */
666 if (ideal_sample_delay_in_ns < 0)
667 ideal_sample_delay_in_ns = 0;
668
669 /*
670 * We have a new ideal sample delay, so re-compute the quantized
671 * delay.
672 */
673 sample_delay_factor =
674 ns_to_cycles(
675 ideal_sample_delay_in_ns << dll_delay_shift,
676 clock_period_in_ns, 0);
677
678 if (sample_delay_factor > nfc->max_sample_delay_factor)
679 sample_delay_factor = nfc->max_sample_delay_factor;
680 }
681
682 /* Control arrives here when we're ready to return our results. */
683return_results:
684 hw->data_setup_in_cycles = data_setup_in_cycles;
685 hw->data_hold_in_cycles = data_hold_in_cycles;
686 hw->address_setup_in_cycles = address_setup_in_cycles;
687 hw->use_half_periods = dll_use_half_periods;
688 hw->sample_delay_factor = sample_delay_factor;
689
690 /* Return success. */
691 return 0;
692}
693
694/* Begin the I/O */
695void gpmi_begin(struct gpmi_nand_data *this)
696{
697 struct resources *r = &this->resources;
698 struct timing_threshod *nfc = &timing_default_threshold;
699 unsigned char *gpmi_regs = r->gpmi_regs;
700 unsigned int clock_period_in_ns;
701 uint32_t reg;
702 unsigned int dll_wait_time_in_us;
703 struct gpmi_nfc_hardware_timing hw;
704 int ret;
705
706 /* Enable the clock. */
707 ret = clk_enable(r->clock);
708 if (ret) {
709 pr_err("We failed in enable the clk\n");
710 goto err_out;
711 }
712
713 /* set ready/busy timeout */
714 writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT,
715 gpmi_regs + HW_GPMI_TIMING1);
716
717 /* Get the timing information we need. */
718 nfc->clock_frequency_in_hz = clk_get_rate(r->clock);
719 clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
720
721 gpmi_nfc_compute_hardware_timing(this, &hw);
722
723 /* Set up all the simple timing parameters. */
724 reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
725 BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
726 BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
727
728 writel(reg, gpmi_regs + HW_GPMI_TIMING0);
729
730 /*
731 * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
732 */
733 writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
734
735 /* Clear out the DLL control fields. */
736 writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR);
737 writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
738
739 /* If no sample delay is called for, return immediately. */
740 if (!hw.sample_delay_factor)
741 return;
742
743 /* Configure the HALF_PERIOD flag. */
744 if (hw.use_half_periods)
745 writel(BM_GPMI_CTRL1_HALF_PERIOD,
746 gpmi_regs + HW_GPMI_CTRL1_SET);
747
748 /* Set the delay factor. */
749 writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
750 gpmi_regs + HW_GPMI_CTRL1_SET);
751
752 /* Enable the DLL. */
753 writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
754
755 /*
756 * After we enable the GPMI DLL, we have to wait 64 clock cycles before
757 * we can use the GPMI.
758 *
759 * Calculate the amount of time we need to wait, in microseconds.
760 */
761 dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
762
763 if (!dll_wait_time_in_us)
764 dll_wait_time_in_us = 1;
765
766 /* Wait for the DLL to settle. */
767 udelay(dll_wait_time_in_us);
768
769err_out:
770 return;
771}
772
773void gpmi_end(struct gpmi_nand_data *this)
774{
775 struct resources *r = &this->resources;
776 clk_disable(r->clock);
777}
778
779/* Clears a BCH interrupt. */
780void gpmi_clear_bch(struct gpmi_nand_data *this)
781{
782 struct resources *r = &this->resources;
783 writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
784}
785
786/* Returns the Ready/Busy status of the given chip. */
787int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
788{
789 struct resources *r = &this->resources;
790 uint32_t mask = 0;
791 uint32_t reg = 0;
792
793 if (GPMI_IS_MX23(this)) {
794 mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
795 reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
796 } else if (GPMI_IS_MX28(this)) {
797 mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
798 reg = readl(r->gpmi_regs + HW_GPMI_STAT);
799 } else
800 pr_err("unknow arch.\n");
801 return reg & mask;
802}
803
804static inline void set_dma_type(struct gpmi_nand_data *this,
805 enum dma_ops_type type)
806{
807 this->last_dma_type = this->dma_type;
808 this->dma_type = type;
809}
810
811int gpmi_send_command(struct gpmi_nand_data *this)
812{
813 struct dma_chan *channel = get_dma_chan(this);
814 struct dma_async_tx_descriptor *desc;
815 struct scatterlist *sgl;
816 int chip = this->current_chip;
817 u32 pio[3];
818
819 /* [1] send out the PIO words */
820 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
821 | BM_GPMI_CTRL0_WORD_LENGTH
822 | BF_GPMI_CTRL0_CS(chip, this)
823 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
824 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
825 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
826 | BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
827 pio[1] = pio[2] = 0;
828 desc = channel->device->device_prep_slave_sg(channel,
829 (struct scatterlist *)pio,
830 ARRAY_SIZE(pio), DMA_NONE, 0);
831 if (!desc) {
832 pr_err("step 1 error\n");
833 return -1;
834 }
835
836 /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
837 sgl = &this->cmd_sgl;
838
839 sg_init_one(sgl, this->cmd_buffer, this->command_length);
840 dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
841 desc = channel->device->device_prep_slave_sg(channel,
842 sgl, 1, DMA_TO_DEVICE, 1);
843 if (!desc) {
844 pr_err("step 2 error\n");
845 return -1;
846 }
847
848 /* [3] submit the DMA */
849 set_dma_type(this, DMA_FOR_COMMAND);
850 return start_dma_without_bch_irq(this, desc);
851}
852
853int gpmi_send_data(struct gpmi_nand_data *this)
854{
855 struct dma_async_tx_descriptor *desc;
856 struct dma_chan *channel = get_dma_chan(this);
857 int chip = this->current_chip;
858 uint32_t command_mode;
859 uint32_t address;
860 u32 pio[2];
861
862 /* [1] PIO */
863 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
864 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
865
866 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
867 | BM_GPMI_CTRL0_WORD_LENGTH
868 | BF_GPMI_CTRL0_CS(chip, this)
869 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
870 | BF_GPMI_CTRL0_ADDRESS(address)
871 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
872 pio[1] = 0;
873 desc = channel->device->device_prep_slave_sg(channel,
874 (struct scatterlist *)pio,
875 ARRAY_SIZE(pio), DMA_NONE, 0);
876 if (!desc) {
877 pr_err("step 1 error\n");
878 return -1;
879 }
880
881 /* [2] send DMA request */
882 prepare_data_dma(this, DMA_TO_DEVICE);
883 desc = channel->device->device_prep_slave_sg(channel, &this->data_sgl,
884 1, DMA_TO_DEVICE, 1);
885 if (!desc) {
886 pr_err("step 2 error\n");
887 return -1;
888 }
889 /* [3] submit the DMA */
890 set_dma_type(this, DMA_FOR_WRITE_DATA);
891 return start_dma_without_bch_irq(this, desc);
892}
893
894int gpmi_read_data(struct gpmi_nand_data *this)
895{
896 struct dma_async_tx_descriptor *desc;
897 struct dma_chan *channel = get_dma_chan(this);
898 int chip = this->current_chip;
899 u32 pio[2];
900
901 /* [1] : send PIO */
902 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
903 | BM_GPMI_CTRL0_WORD_LENGTH
904 | BF_GPMI_CTRL0_CS(chip, this)
905 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
906 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
907 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
908 pio[1] = 0;
909 desc = channel->device->device_prep_slave_sg(channel,
910 (struct scatterlist *)pio,
911 ARRAY_SIZE(pio), DMA_NONE, 0);
912 if (!desc) {
913 pr_err("step 1 error\n");
914 return -1;
915 }
916
917 /* [2] : send DMA request */
918 prepare_data_dma(this, DMA_FROM_DEVICE);
919 desc = channel->device->device_prep_slave_sg(channel, &this->data_sgl,
920 1, DMA_FROM_DEVICE, 1);
921 if (!desc) {
922 pr_err("step 2 error\n");
923 return -1;
924 }
925
926 /* [3] : submit the DMA */
927 set_dma_type(this, DMA_FOR_READ_DATA);
928 return start_dma_without_bch_irq(this, desc);
929}
930
931int gpmi_send_page(struct gpmi_nand_data *this,
932 dma_addr_t payload, dma_addr_t auxiliary)
933{
934 struct bch_geometry *geo = &this->bch_geometry;
935 uint32_t command_mode;
936 uint32_t address;
937 uint32_t ecc_command;
938 uint32_t buffer_mask;
939 struct dma_async_tx_descriptor *desc;
940 struct dma_chan *channel = get_dma_chan(this);
941 int chip = this->current_chip;
942 u32 pio[6];
943
944 /* A DMA descriptor that does an ECC page read. */
945 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
946 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
947 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
948 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
949 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
950
951 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
952 | BM_GPMI_CTRL0_WORD_LENGTH
953 | BF_GPMI_CTRL0_CS(chip, this)
954 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
955 | BF_GPMI_CTRL0_ADDRESS(address)
956 | BF_GPMI_CTRL0_XFER_COUNT(0);
957 pio[1] = 0;
958 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
959 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
960 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
961 pio[3] = geo->page_size;
962 pio[4] = payload;
963 pio[5] = auxiliary;
964
965 desc = channel->device->device_prep_slave_sg(channel,
966 (struct scatterlist *)pio,
967 ARRAY_SIZE(pio), DMA_NONE, 0);
968 if (!desc) {
969 pr_err("step 2 error\n");
970 return -1;
971 }
972 set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE);
973 return start_dma_with_bch_irq(this, desc);
974}
975
976int gpmi_read_page(struct gpmi_nand_data *this,
977 dma_addr_t payload, dma_addr_t auxiliary)
978{
979 struct bch_geometry *geo = &this->bch_geometry;
980 uint32_t command_mode;
981 uint32_t address;
982 uint32_t ecc_command;
983 uint32_t buffer_mask;
984 struct dma_async_tx_descriptor *desc;
985 struct dma_chan *channel = get_dma_chan(this);
986 int chip = this->current_chip;
987 u32 pio[6];
988
989 /* [1] Wait for the chip to report ready. */
990 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
991 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
992
993 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
994 | BM_GPMI_CTRL0_WORD_LENGTH
995 | BF_GPMI_CTRL0_CS(chip, this)
996 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
997 | BF_GPMI_CTRL0_ADDRESS(address)
998 | BF_GPMI_CTRL0_XFER_COUNT(0);
999 pio[1] = 0;
1000 desc = channel->device->device_prep_slave_sg(channel,
1001 (struct scatterlist *)pio, 2, DMA_NONE, 0);
1002 if (!desc) {
1003 pr_err("step 1 error\n");
1004 return -1;
1005 }
1006
1007 /* [2] Enable the BCH block and read. */
1008 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
1009 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1010 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
1011 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
1012 | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
1013
1014 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1015 | BM_GPMI_CTRL0_WORD_LENGTH
1016 | BF_GPMI_CTRL0_CS(chip, this)
1017 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1018 | BF_GPMI_CTRL0_ADDRESS(address)
1019 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1020
1021 pio[1] = 0;
1022 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
1023 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1024 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1025 pio[3] = geo->page_size;
1026 pio[4] = payload;
1027 pio[5] = auxiliary;
1028 desc = channel->device->device_prep_slave_sg(channel,
1029 (struct scatterlist *)pio,
1030 ARRAY_SIZE(pio), DMA_NONE, 1);
1031 if (!desc) {
1032 pr_err("step 2 error\n");
1033 return -1;
1034 }
1035
1036 /* [3] Disable the BCH block */
1037 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1038 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1039
1040 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1041 | BM_GPMI_CTRL0_WORD_LENGTH
1042 | BF_GPMI_CTRL0_CS(chip, this)
1043 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1044 | BF_GPMI_CTRL0_ADDRESS(address)
1045 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1046 pio[1] = 0;
1047 desc = channel->device->device_prep_slave_sg(channel,
1048 (struct scatterlist *)pio, 2, DMA_NONE, 1);
1049 if (!desc) {
1050 pr_err("step 3 error\n");
1051 return -1;
1052 }
1053
1054 /* [4] submit the DMA */
1055 set_dma_type(this, DMA_FOR_READ_ECC_PAGE);
1056 return start_dma_with_bch_irq(this, desc);
1057}
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
new file mode 100644
index 00000000000..83431240e2f
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
@@ -0,0 +1,172 @@
1/*
2 * Freescale GPMI NAND Flash Driver
3 *
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21#ifndef __GPMI_NAND_GPMI_REGS_H
22#define __GPMI_NAND_GPMI_REGS_H
23
24#define HW_GPMI_CTRL0 0x00000000
25#define HW_GPMI_CTRL0_SET 0x00000004
26#define HW_GPMI_CTRL0_CLR 0x00000008
27#define HW_GPMI_CTRL0_TOG 0x0000000c
28
29#define BP_GPMI_CTRL0_COMMAND_MODE 24
30#define BM_GPMI_CTRL0_COMMAND_MODE (3 << BP_GPMI_CTRL0_COMMAND_MODE)
31#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
32 (((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE)
33#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
34#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
35#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
36#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
37
38#define BM_GPMI_CTRL0_WORD_LENGTH (1 << 23)
39#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
40#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
41
42/*
43 * Difference in LOCK_CS between imx23 and imx28 :
44 * This bit may impact the _POWER_ consumption. So some chips
45 * do not set it.
46 */
47#define MX23_BP_GPMI_CTRL0_LOCK_CS 22
48#define MX28_BP_GPMI_CTRL0_LOCK_CS 27
49#define LOCK_CS_ENABLE 0x1
50#define BF_GPMI_CTRL0_LOCK_CS(v, x) 0x0
51
52/* Difference in CS between imx23 and imx28 */
53#define BP_GPMI_CTRL0_CS 20
54#define MX23_BM_GPMI_CTRL0_CS (3 << BP_GPMI_CTRL0_CS)
55#define MX28_BM_GPMI_CTRL0_CS (7 << BP_GPMI_CTRL0_CS)
56#define BF_GPMI_CTRL0_CS(v, x) (((v) << BP_GPMI_CTRL0_CS) & \
57 (GPMI_IS_MX23((x)) \
58 ? MX23_BM_GPMI_CTRL0_CS \
59 : MX28_BM_GPMI_CTRL0_CS))
60
61#define BP_GPMI_CTRL0_ADDRESS 17
62#define BM_GPMI_CTRL0_ADDRESS (3 << BP_GPMI_CTRL0_ADDRESS)
63#define BF_GPMI_CTRL0_ADDRESS(v) \
64 (((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS)
65#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
66#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
67#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
68
69#define BM_GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
70#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
71#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
72
73#define BP_GPMI_CTRL0_XFER_COUNT 0
74#define BM_GPMI_CTRL0_XFER_COUNT (0xffff << BP_GPMI_CTRL0_XFER_COUNT)
75#define BF_GPMI_CTRL0_XFER_COUNT(v) \
76 (((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT)
77
78#define HW_GPMI_COMPARE 0x00000010
79
80#define HW_GPMI_ECCCTRL 0x00000020
81#define HW_GPMI_ECCCTRL_SET 0x00000024
82#define HW_GPMI_ECCCTRL_CLR 0x00000028
83#define HW_GPMI_ECCCTRL_TOG 0x0000002c
84
85#define BP_GPMI_ECCCTRL_ECC_CMD 13
86#define BM_GPMI_ECCCTRL_ECC_CMD (3 << BP_GPMI_ECCCTRL_ECC_CMD)
87#define BF_GPMI_ECCCTRL_ECC_CMD(v) \
88 (((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD)
89#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
90#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
91
92#define BM_GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
93#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1
94#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
95
96#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
97#define BM_GPMI_ECCCTRL_BUFFER_MASK (0x1ff << BP_GPMI_ECCCTRL_BUFFER_MASK)
98#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \
99 (((v) << BP_GPMI_ECCCTRL_BUFFER_MASK) & BM_GPMI_ECCCTRL_BUFFER_MASK)
100#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
101#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
102
103#define HW_GPMI_ECCCOUNT 0x00000030
104#define HW_GPMI_PAYLOAD 0x00000040
105#define HW_GPMI_AUXILIARY 0x00000050
106#define HW_GPMI_CTRL1 0x00000060
107#define HW_GPMI_CTRL1_SET 0x00000064
108#define HW_GPMI_CTRL1_CLR 0x00000068
109#define HW_GPMI_CTRL1_TOG 0x0000006c
110
111#define BM_GPMI_CTRL1_BCH_MODE (1 << 18)
112
113#define BP_GPMI_CTRL1_DLL_ENABLE 17
114#define BM_GPMI_CTRL1_DLL_ENABLE (1 << BP_GPMI_CTRL1_DLL_ENABLE)
115
116#define BP_GPMI_CTRL1_HALF_PERIOD 16
117#define BM_GPMI_CTRL1_HALF_PERIOD (1 << BP_GPMI_CTRL1_HALF_PERIOD)
118
119#define BP_GPMI_CTRL1_RDN_DELAY 12
120#define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY)
121#define BF_GPMI_CTRL1_RDN_DELAY(v) \
122 (((v) << BP_GPMI_CTRL1_RDN_DELAY) & BM_GPMI_CTRL1_RDN_DELAY)
123
124#define BM_GPMI_CTRL1_DEV_RESET (1 << 3)
125#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
126#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
127
128#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
129#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
130#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
131
132#define BM_GPMI_CTRL1_CAMERA_MODE (1 << 1)
133#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
134#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
135
136#define BM_GPMI_CTRL1_GPMI_MODE (1 << 0)
137
138#define HW_GPMI_TIMING0 0x00000070
139
140#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
141#define BM_GPMI_TIMING0_ADDRESS_SETUP (0xff << BP_GPMI_TIMING0_ADDRESS_SETUP)
142#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
143 (((v) << BP_GPMI_TIMING0_ADDRESS_SETUP) & BM_GPMI_TIMING0_ADDRESS_SETUP)
144
145#define BP_GPMI_TIMING0_DATA_HOLD 8
146#define BM_GPMI_TIMING0_DATA_HOLD (0xff << BP_GPMI_TIMING0_DATA_HOLD)
147#define BF_GPMI_TIMING0_DATA_HOLD(v) \
148 (((v) << BP_GPMI_TIMING0_DATA_HOLD) & BM_GPMI_TIMING0_DATA_HOLD)
149
150#define BP_GPMI_TIMING0_DATA_SETUP 0
151#define BM_GPMI_TIMING0_DATA_SETUP (0xff << BP_GPMI_TIMING0_DATA_SETUP)
152#define BF_GPMI_TIMING0_DATA_SETUP(v) \
153 (((v) << BP_GPMI_TIMING0_DATA_SETUP) & BM_GPMI_TIMING0_DATA_SETUP)
154
155#define HW_GPMI_TIMING1 0x00000080
156#define BP_GPMI_TIMING1_BUSY_TIMEOUT 16
157
158#define HW_GPMI_TIMING2 0x00000090
159#define HW_GPMI_DATA 0x000000a0
160
161/* MX28 uses this to detect READY. */
162#define HW_GPMI_STAT 0x000000b0
163#define MX28_BP_GPMI_STAT_READY_BUSY 24
164#define MX28_BM_GPMI_STAT_READY_BUSY (0xff << MX28_BP_GPMI_STAT_READY_BUSY)
165#define MX28_BF_GPMI_STAT_READY_BUSY(v) \
166 (((v) << MX28_BP_GPMI_STAT_READY_BUSY) & MX28_BM_GPMI_STAT_READY_BUSY)
167
168/* MX23 uses this to detect READY. */
169#define HW_GPMI_DEBUG 0x000000c0
170#define MX23_BP_GPMI_DEBUG_READY0 28
171#define MX23_BM_GPMI_DEBUG_READY0 (1 << MX23_BP_GPMI_DEBUG_READY0)
172#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 11:58:48 -0500