OMAP4 ES2: HSMMC soft reset change

The omap4 es2 hsmmc has a updated soft reset logic.After the
reset is issued monitor a 0->1 transition first. The reset of
CMD or DATA lines is complete only after a 0->1->0 transition
of SRC or SRD bits.

Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Tested-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 53f8fa599cf..69858e75020 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -982,6 +982,17 @@ static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
         OMAP_HSMMC_WRITE(host->base, SYSCTL,
                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 
+        /*
+         * OMAP4 ES2 and greater has an updated reset logic.
+         * Monitor a 0->1 transition first
+         */
+        if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
+                while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit))
+                                        && (i++ < limit))
+                        cpu_relax();
+        }
+        i = 0;
+
         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
                 (i++ < limit))
                 cpu_relax();