diff options
author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2012-05-02 05:14:49 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-05-20 08:19:32 -0400 |
commit | c83a1ff063eb7cd8eb2025c08194f6bcb49334f1 (patch) | |
tree | 043924c0ccedb6b0f467d74e6db0cb2a0bd26330 /drivers/media/video | |
parent | 693f5c40825e91632478624bf0366e6ebf862a25 (diff) |
[media] s5p-fimc: Refactor the register interface functions
Simplify the register API and use FIMC_REG_ prefix for all register
definitions for consistency with FIMC-LITE. The unused image effect
defines are removed.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video')
-rw-r--r-- | drivers/media/video/s5p-fimc/fimc-capture.c | 1 | ||||
-rw-r--r-- | drivers/media/video/s5p-fimc/fimc-core.c | 21 | ||||
-rw-r--r-- | drivers/media/video/s5p-fimc/fimc-core.h | 118 | ||||
-rw-r--r-- | drivers/media/video/s5p-fimc/fimc-m2m.c | 1 | ||||
-rw-r--r-- | drivers/media/video/s5p-fimc/fimc-reg.c | 554 | ||||
-rw-r--r-- | drivers/media/video/s5p-fimc/fimc-reg.h | 326 | ||||
-rw-r--r-- | drivers/media/video/s5p-fimc/regs-fimc.h | 301 |
7 files changed, 641 insertions, 681 deletions
diff --git a/drivers/media/video/s5p-fimc/fimc-capture.c b/drivers/media/video/s5p-fimc/fimc-capture.c index b45da278021..52a5fb469b4 100644 --- a/drivers/media/video/s5p-fimc/fimc-capture.c +++ b/drivers/media/video/s5p-fimc/fimc-capture.c | |||
@@ -29,6 +29,7 @@ | |||
29 | 29 | ||
30 | #include "fimc-mdevice.h" | 30 | #include "fimc-mdevice.h" |
31 | #include "fimc-core.h" | 31 | #include "fimc-core.h" |
32 | #include "fimc-reg.h" | ||
32 | 33 | ||
33 | static int fimc_init_capture(struct fimc_dev *fimc) | 34 | static int fimc_init_capture(struct fimc_dev *fimc) |
34 | { | 35 | { |
diff --git a/drivers/media/video/s5p-fimc/fimc-core.c b/drivers/media/video/s5p-fimc/fimc-core.c index add24cd373a..afd69e3d44c 100644 --- a/drivers/media/video/s5p-fimc/fimc-core.c +++ b/drivers/media/video/s5p-fimc/fimc-core.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <media/videobuf2-dma-contig.h> | 28 | #include <media/videobuf2-dma-contig.h> |
29 | 29 | ||
30 | #include "fimc-core.h" | 30 | #include "fimc-core.h" |
31 | #include "fimc-reg.h" | ||
31 | #include "fimc-mdevice.h" | 32 | #include "fimc-mdevice.h" |
32 | 33 | ||
33 | static char *fimc_clocks[MAX_FIMC_CLOCKS] = { | 34 | static char *fimc_clocks[MAX_FIMC_CLOCKS] = { |
@@ -388,40 +389,40 @@ int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb, | |||
388 | void fimc_set_yuv_order(struct fimc_ctx *ctx) | 389 | void fimc_set_yuv_order(struct fimc_ctx *ctx) |
389 | { | 390 | { |
390 | /* The one only mode supported in SoC. */ | 391 | /* The one only mode supported in SoC. */ |
391 | ctx->in_order_2p = S5P_FIMC_LSB_CRCB; | 392 | ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; |
392 | ctx->out_order_2p = S5P_FIMC_LSB_CRCB; | 393 | ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; |
393 | 394 | ||
394 | /* Set order for 1 plane input formats. */ | 395 | /* Set order for 1 plane input formats. */ |
395 | switch (ctx->s_frame.fmt->color) { | 396 | switch (ctx->s_frame.fmt->color) { |
396 | case S5P_FIMC_YCRYCB422: | 397 | case S5P_FIMC_YCRYCB422: |
397 | ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY; | 398 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY; |
398 | break; | 399 | break; |
399 | case S5P_FIMC_CBYCRY422: | 400 | case S5P_FIMC_CBYCRY422: |
400 | ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB; | 401 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB; |
401 | break; | 402 | break; |
402 | case S5P_FIMC_CRYCBY422: | 403 | case S5P_FIMC_CRYCBY422: |
403 | ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR; | 404 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR; |
404 | break; | 405 | break; |
405 | case S5P_FIMC_YCBYCR422: | 406 | case S5P_FIMC_YCBYCR422: |
406 | default: | 407 | default: |
407 | ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY; | 408 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY; |
408 | break; | 409 | break; |
409 | } | 410 | } |
410 | dbg("ctx->in_order_1p= %d", ctx->in_order_1p); | 411 | dbg("ctx->in_order_1p= %d", ctx->in_order_1p); |
411 | 412 | ||
412 | switch (ctx->d_frame.fmt->color) { | 413 | switch (ctx->d_frame.fmt->color) { |
413 | case S5P_FIMC_YCRYCB422: | 414 | case S5P_FIMC_YCRYCB422: |
414 | ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY; | 415 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY; |
415 | break; | 416 | break; |
416 | case S5P_FIMC_CBYCRY422: | 417 | case S5P_FIMC_CBYCRY422: |
417 | ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB; | 418 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB; |
418 | break; | 419 | break; |
419 | case S5P_FIMC_CRYCBY422: | 420 | case S5P_FIMC_CRYCBY422: |
420 | ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR; | 421 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR; |
421 | break; | 422 | break; |
422 | case S5P_FIMC_YCBYCR422: | 423 | case S5P_FIMC_YCBYCR422: |
423 | default: | 424 | default: |
424 | ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY; | 425 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY; |
425 | break; | 426 | break; |
426 | } | 427 | } |
427 | dbg("ctx->out_order_1p= %d", ctx->out_order_1p); | 428 | dbg("ctx->out_order_1p= %d", ctx->out_order_1p); |
diff --git a/drivers/media/video/s5p-fimc/fimc-core.h b/drivers/media/video/s5p-fimc/fimc-core.h index ef7c6a23ca2..34fbba42469 100644 --- a/drivers/media/video/s5p-fimc/fimc-core.h +++ b/drivers/media/video/s5p-fimc/fimc-core.h | |||
@@ -26,8 +26,6 @@ | |||
26 | #include <media/v4l2-mediabus.h> | 26 | #include <media/v4l2-mediabus.h> |
27 | #include <media/s5p_fimc.h> | 27 | #include <media/s5p_fimc.h> |
28 | 28 | ||
29 | #include "regs-fimc.h" | ||
30 | |||
31 | #define err(fmt, args...) \ | 29 | #define err(fmt, args...) \ |
32 | printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args) | 30 | printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args) |
33 | 31 | ||
@@ -106,17 +104,6 @@ enum fimc_color_fmt { | |||
106 | #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \ | 104 | #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \ |
107 | __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) | 105 | __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) |
108 | 106 | ||
109 | /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */ | ||
110 | #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB | ||
111 | |||
112 | /* The embedded image effect selection */ | ||
113 | #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS | ||
114 | #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY | ||
115 | #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE | ||
116 | #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE | ||
117 | #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING | ||
118 | #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE | ||
119 | |||
120 | /* The hardware context state. */ | 107 | /* The hardware context state. */ |
121 | #define FIMC_PARAMS (1 << 0) | 108 | #define FIMC_PARAMS (1 << 0) |
122 | #define FIMC_SRC_FMT (1 << 3) | 109 | #define FIMC_SRC_FMT (1 << 3) |
@@ -588,54 +575,6 @@ static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt) | |||
588 | }; | 575 | }; |
589 | } | 576 | } |
590 | 577 | ||
591 | static inline void fimc_hw_clear_irq(struct fimc_dev *dev) | ||
592 | { | ||
593 | u32 cfg = readl(dev->regs + S5P_CIGCTRL); | ||
594 | cfg |= S5P_CIGCTRL_IRQ_CLR; | ||
595 | writel(cfg, dev->regs + S5P_CIGCTRL); | ||
596 | } | ||
597 | |||
598 | static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on) | ||
599 | { | ||
600 | u32 cfg = readl(dev->regs + S5P_CISCCTRL); | ||
601 | if (on) | ||
602 | cfg |= S5P_CISCCTRL_SCALERSTART; | ||
603 | else | ||
604 | cfg &= ~S5P_CISCCTRL_SCALERSTART; | ||
605 | writel(cfg, dev->regs + S5P_CISCCTRL); | ||
606 | } | ||
607 | |||
608 | static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on) | ||
609 | { | ||
610 | u32 cfg = readl(dev->regs + S5P_MSCTRL); | ||
611 | if (on) | ||
612 | cfg |= S5P_MSCTRL_ENVID; | ||
613 | else | ||
614 | cfg &= ~S5P_MSCTRL_ENVID; | ||
615 | writel(cfg, dev->regs + S5P_MSCTRL); | ||
616 | } | ||
617 | |||
618 | static inline void fimc_hw_dis_capture(struct fimc_dev *dev) | ||
619 | { | ||
620 | u32 cfg = readl(dev->regs + S5P_CIIMGCPT); | ||
621 | cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC); | ||
622 | writel(cfg, dev->regs + S5P_CIIMGCPT); | ||
623 | } | ||
624 | |||
625 | /** | ||
626 | * fimc_hw_set_dma_seq - configure output DMA buffer sequence | ||
627 | * @mask: each bit corresponds to one of 32 output buffer registers set | ||
628 | * 1 to include buffer in the sequence, 0 to disable | ||
629 | * | ||
630 | * This function mask output DMA ring buffers, i.e. it allows to configure | ||
631 | * which of the output buffer address registers will be used by the DMA | ||
632 | * engine. | ||
633 | */ | ||
634 | static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask) | ||
635 | { | ||
636 | writel(mask, dev->regs + S5P_CIFCNTSEQ); | ||
637 | } | ||
638 | |||
639 | static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx, | 578 | static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx, |
640 | enum v4l2_buf_type type) | 579 | enum v4l2_buf_type type) |
641 | { | 580 | { |
@@ -657,48 +596,6 @@ static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx, | |||
657 | return frame; | 596 | return frame; |
658 | } | 597 | } |
659 | 598 | ||
660 | /* Return an index to the buffer actually being written. */ | ||
661 | static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev) | ||
662 | { | ||
663 | u32 reg; | ||
664 | |||
665 | if (dev->variant->has_cistatus2) { | ||
666 | reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F; | ||
667 | return reg > 0 ? --reg : reg; | ||
668 | } else { | ||
669 | reg = readl(dev->regs + S5P_CISTATUS); | ||
670 | return (reg & S5P_CISTATUS_FRAMECNT_MASK) >> | ||
671 | S5P_CISTATUS_FRAMECNT_SHIFT; | ||
672 | } | ||
673 | } | ||
674 | |||
675 | /* -----------------------------------------------------*/ | ||
676 | /* fimc-reg.c */ | ||
677 | void fimc_hw_reset(struct fimc_dev *fimc); | ||
678 | void fimc_hw_set_rotation(struct fimc_ctx *ctx); | ||
679 | void fimc_hw_set_target_format(struct fimc_ctx *ctx); | ||
680 | void fimc_hw_set_out_dma(struct fimc_ctx *ctx); | ||
681 | void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable); | ||
682 | void fimc_hw_en_irq(struct fimc_dev *fimc, int enable); | ||
683 | void fimc_hw_set_prescaler(struct fimc_ctx *ctx); | ||
684 | void fimc_hw_set_mainscaler(struct fimc_ctx *ctx); | ||
685 | void fimc_hw_en_capture(struct fimc_ctx *ctx); | ||
686 | void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active); | ||
687 | void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx); | ||
688 | void fimc_hw_set_in_dma(struct fimc_ctx *ctx); | ||
689 | void fimc_hw_set_input_path(struct fimc_ctx *ctx); | ||
690 | void fimc_hw_set_output_path(struct fimc_ctx *ctx); | ||
691 | void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr); | ||
692 | void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr, | ||
693 | int index); | ||
694 | int fimc_hw_set_camera_source(struct fimc_dev *fimc, | ||
695 | struct s5p_fimc_isp_info *cam); | ||
696 | int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f); | ||
697 | int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, | ||
698 | struct s5p_fimc_isp_info *cam); | ||
699 | int fimc_hw_set_camera_type(struct fimc_dev *fimc, | ||
700 | struct s5p_fimc_isp_info *cam); | ||
701 | |||
702 | /* -----------------------------------------------------*/ | 599 | /* -----------------------------------------------------*/ |
703 | /* fimc-core.c */ | 600 | /* fimc-core.c */ |
704 | int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv, | 601 | int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv, |
@@ -745,21 +642,6 @@ void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification, | |||
745 | int fimc_capture_suspend(struct fimc_dev *fimc); | 642 | int fimc_capture_suspend(struct fimc_dev *fimc); |
746 | int fimc_capture_resume(struct fimc_dev *fimc); | 643 | int fimc_capture_resume(struct fimc_dev *fimc); |
747 | 644 | ||
748 | /* Locking: the caller holds fimc->slock */ | ||
749 | static inline void fimc_activate_capture(struct fimc_ctx *ctx) | ||
750 | { | ||
751 | fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled); | ||
752 | fimc_hw_en_capture(ctx); | ||
753 | } | ||
754 | |||
755 | static inline void fimc_deactivate_capture(struct fimc_dev *fimc) | ||
756 | { | ||
757 | fimc_hw_en_lastirq(fimc, true); | ||
758 | fimc_hw_dis_capture(fimc); | ||
759 | fimc_hw_enable_scaler(fimc, false); | ||
760 | fimc_hw_en_lastirq(fimc, false); | ||
761 | } | ||
762 | |||
763 | /* | 645 | /* |
764 | * Buffer list manipulation functions. Must be called with fimc.slock held. | 646 | * Buffer list manipulation functions. Must be called with fimc.slock held. |
765 | */ | 647 | */ |
diff --git a/drivers/media/video/s5p-fimc/fimc-m2m.c b/drivers/media/video/s5p-fimc/fimc-m2m.c index 92b6059b25b..70edc75e6fc 100644 --- a/drivers/media/video/s5p-fimc/fimc-m2m.c +++ b/drivers/media/video/s5p-fimc/fimc-m2m.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <media/videobuf2-dma-contig.h> | 28 | #include <media/videobuf2-dma-contig.h> |
29 | 29 | ||
30 | #include "fimc-core.h" | 30 | #include "fimc-core.h" |
31 | #include "fimc-reg.h" | ||
31 | #include "fimc-mdevice.h" | 32 | #include "fimc-mdevice.h" |
32 | 33 | ||
33 | 34 | ||
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.c b/drivers/media/video/s5p-fimc/fimc-reg.c index ff11f10fea0..31a8b99ee71 100644 --- a/drivers/media/video/s5p-fimc/fimc-reg.c +++ b/drivers/media/video/s5p-fimc/fimc-reg.c | |||
@@ -12,9 +12,9 @@ | |||
12 | 12 | ||
13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
14 | #include <linux/delay.h> | 14 | #include <linux/delay.h> |
15 | #include <mach/map.h> | ||
16 | #include <media/s5p_fimc.h> | 15 | #include <media/s5p_fimc.h> |
17 | 16 | ||
17 | #include "fimc-reg.h" | ||
18 | #include "fimc-core.h" | 18 | #include "fimc-core.h" |
19 | 19 | ||
20 | 20 | ||
@@ -22,19 +22,19 @@ void fimc_hw_reset(struct fimc_dev *dev) | |||
22 | { | 22 | { |
23 | u32 cfg; | 23 | u32 cfg; |
24 | 24 | ||
25 | cfg = readl(dev->regs + S5P_CISRCFMT); | 25 | cfg = readl(dev->regs + FIMC_REG_CISRCFMT); |
26 | cfg |= S5P_CISRCFMT_ITU601_8BIT; | 26 | cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; |
27 | writel(cfg, dev->regs + S5P_CISRCFMT); | 27 | writel(cfg, dev->regs + FIMC_REG_CISRCFMT); |
28 | 28 | ||
29 | /* Software reset. */ | 29 | /* Software reset. */ |
30 | cfg = readl(dev->regs + S5P_CIGCTRL); | 30 | cfg = readl(dev->regs + FIMC_REG_CIGCTRL); |
31 | cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL); | 31 | cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); |
32 | writel(cfg, dev->regs + S5P_CIGCTRL); | 32 | writel(cfg, dev->regs + FIMC_REG_CIGCTRL); |
33 | udelay(10); | 33 | udelay(10); |
34 | 34 | ||
35 | cfg = readl(dev->regs + S5P_CIGCTRL); | 35 | cfg = readl(dev->regs + FIMC_REG_CIGCTRL); |
36 | cfg &= ~S5P_CIGCTRL_SWRST; | 36 | cfg &= ~FIMC_REG_CIGCTRL_SWRST; |
37 | writel(cfg, dev->regs + S5P_CIGCTRL); | 37 | writel(cfg, dev->regs + FIMC_REG_CIGCTRL); |
38 | 38 | ||
39 | if (dev->variant->out_buf_count > 4) | 39 | if (dev->variant->out_buf_count > 4) |
40 | fimc_hw_set_dma_seq(dev, 0xF); | 40 | fimc_hw_set_dma_seq(dev, 0xF); |
@@ -42,32 +42,32 @@ void fimc_hw_reset(struct fimc_dev *dev) | |||
42 | 42 | ||
43 | static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx) | 43 | static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx) |
44 | { | 44 | { |
45 | u32 flip = S5P_MSCTRL_FLIP_NORMAL; | 45 | u32 flip = FIMC_REG_MSCTRL_FLIP_NORMAL; |
46 | 46 | ||
47 | if (ctx->hflip) | 47 | if (ctx->hflip) |
48 | flip = S5P_MSCTRL_FLIP_X_MIRROR; | 48 | flip = FIMC_REG_MSCTRL_FLIP_X_MIRROR; |
49 | if (ctx->vflip) | 49 | if (ctx->vflip) |
50 | flip = S5P_MSCTRL_FLIP_Y_MIRROR; | 50 | flip = FIMC_REG_MSCTRL_FLIP_Y_MIRROR; |
51 | 51 | ||
52 | if (ctx->rotation <= 90) | 52 | if (ctx->rotation <= 90) |
53 | return flip; | 53 | return flip; |
54 | 54 | ||
55 | return (flip ^ S5P_MSCTRL_FLIP_180) & S5P_MSCTRL_FLIP_180; | 55 | return (flip ^ FIMC_REG_MSCTRL_FLIP_180) & FIMC_REG_MSCTRL_FLIP_180; |
56 | } | 56 | } |
57 | 57 | ||
58 | static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx) | 58 | static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx) |
59 | { | 59 | { |
60 | u32 flip = S5P_CITRGFMT_FLIP_NORMAL; | 60 | u32 flip = FIMC_REG_CITRGFMT_FLIP_NORMAL; |
61 | 61 | ||
62 | if (ctx->hflip) | 62 | if (ctx->hflip) |
63 | flip |= S5P_CITRGFMT_FLIP_X_MIRROR; | 63 | flip |= FIMC_REG_CITRGFMT_FLIP_X_MIRROR; |
64 | if (ctx->vflip) | 64 | if (ctx->vflip) |
65 | flip |= S5P_CITRGFMT_FLIP_Y_MIRROR; | 65 | flip |= FIMC_REG_CITRGFMT_FLIP_Y_MIRROR; |
66 | 66 | ||
67 | if (ctx->rotation <= 90) | 67 | if (ctx->rotation <= 90) |
68 | return flip; | 68 | return flip; |
69 | 69 | ||
70 | return (flip ^ S5P_CITRGFMT_FLIP_180) & S5P_CITRGFMT_FLIP_180; | 70 | return (flip ^ FIMC_REG_CITRGFMT_FLIP_180) & FIMC_REG_CITRGFMT_FLIP_180; |
71 | } | 71 | } |
72 | 72 | ||
73 | void fimc_hw_set_rotation(struct fimc_ctx *ctx) | 73 | void fimc_hw_set_rotation(struct fimc_ctx *ctx) |
@@ -75,9 +75,9 @@ void fimc_hw_set_rotation(struct fimc_ctx *ctx) | |||
75 | u32 cfg, flip; | 75 | u32 cfg, flip; |
76 | struct fimc_dev *dev = ctx->fimc_dev; | 76 | struct fimc_dev *dev = ctx->fimc_dev; |
77 | 77 | ||
78 | cfg = readl(dev->regs + S5P_CITRGFMT); | 78 | cfg = readl(dev->regs + FIMC_REG_CITRGFMT); |
79 | cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90 | | 79 | cfg &= ~(FIMC_REG_CITRGFMT_INROT90 | FIMC_REG_CITRGFMT_OUTROT90 | |
80 | S5P_CITRGFMT_FLIP_180); | 80 | FIMC_REG_CITRGFMT_FLIP_180); |
81 | 81 | ||
82 | /* | 82 | /* |
83 | * The input and output rotator cannot work simultaneously. | 83 | * The input and output rotator cannot work simultaneously. |
@@ -86,20 +86,20 @@ void fimc_hw_set_rotation(struct fimc_ctx *ctx) | |||
86 | */ | 86 | */ |
87 | if (ctx->rotation == 90 || ctx->rotation == 270) { | 87 | if (ctx->rotation == 90 || ctx->rotation == 270) { |
88 | if (ctx->out_path == FIMC_LCDFIFO) | 88 | if (ctx->out_path == FIMC_LCDFIFO) |
89 | cfg |= S5P_CITRGFMT_INROT90; | 89 | cfg |= FIMC_REG_CITRGFMT_INROT90; |
90 | else | 90 | else |
91 | cfg |= S5P_CITRGFMT_OUTROT90; | 91 | cfg |= FIMC_REG_CITRGFMT_OUTROT90; |
92 | } | 92 | } |
93 | 93 | ||
94 | if (ctx->out_path == FIMC_DMA) { | 94 | if (ctx->out_path == FIMC_DMA) { |
95 | cfg |= fimc_hw_get_target_flip(ctx); | 95 | cfg |= fimc_hw_get_target_flip(ctx); |
96 | writel(cfg, dev->regs + S5P_CITRGFMT); | 96 | writel(cfg, dev->regs + FIMC_REG_CITRGFMT); |
97 | } else { | 97 | } else { |
98 | /* LCD FIFO path */ | 98 | /* LCD FIFO path */ |
99 | flip = readl(dev->regs + S5P_MSCTRL); | 99 | flip = readl(dev->regs + FIMC_REG_MSCTRL); |
100 | flip &= ~S5P_MSCTRL_FLIP_MASK; | 100 | flip &= ~FIMC_REG_MSCTRL_FLIP_MASK; |
101 | flip |= fimc_hw_get_in_flip(ctx); | 101 | flip |= fimc_hw_get_in_flip(ctx); |
102 | writel(flip, dev->regs + S5P_MSCTRL); | 102 | writel(flip, dev->regs + FIMC_REG_MSCTRL); |
103 | } | 103 | } |
104 | } | 104 | } |
105 | 105 | ||
@@ -110,43 +110,40 @@ void fimc_hw_set_target_format(struct fimc_ctx *ctx) | |||
110 | struct fimc_frame *frame = &ctx->d_frame; | 110 | struct fimc_frame *frame = &ctx->d_frame; |
111 | 111 | ||
112 | dbg("w= %d, h= %d color: %d", frame->width, | 112 | dbg("w= %d, h= %d color: %d", frame->width, |
113 | frame->height, frame->fmt->color); | 113 | frame->height, frame->fmt->color); |
114 | 114 | ||
115 | cfg = readl(dev->regs + S5P_CITRGFMT); | 115 | cfg = readl(dev->regs + FIMC_REG_CITRGFMT); |
116 | cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK | | 116 | cfg &= ~(FIMC_REG_CITRGFMT_FMT_MASK | FIMC_REG_CITRGFMT_HSIZE_MASK | |
117 | S5P_CITRGFMT_VSIZE_MASK); | 117 | FIMC_REG_CITRGFMT_VSIZE_MASK); |
118 | 118 | ||
119 | switch (frame->fmt->color) { | 119 | switch (frame->fmt->color) { |
120 | case S5P_FIMC_RGB444...S5P_FIMC_RGB888: | 120 | case S5P_FIMC_RGB444...S5P_FIMC_RGB888: |
121 | cfg |= S5P_CITRGFMT_RGB; | 121 | cfg |= FIMC_REG_CITRGFMT_RGB; |
122 | break; | 122 | break; |
123 | case S5P_FIMC_YCBCR420: | 123 | case S5P_FIMC_YCBCR420: |
124 | cfg |= S5P_CITRGFMT_YCBCR420; | 124 | cfg |= FIMC_REG_CITRGFMT_YCBCR420; |
125 | break; | 125 | break; |
126 | case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422: | 126 | case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422: |
127 | if (frame->fmt->colplanes == 1) | 127 | if (frame->fmt->colplanes == 1) |
128 | cfg |= S5P_CITRGFMT_YCBCR422_1P; | 128 | cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P; |
129 | else | 129 | else |
130 | cfg |= S5P_CITRGFMT_YCBCR422; | 130 | cfg |= FIMC_REG_CITRGFMT_YCBCR422; |
131 | break; | 131 | break; |
132 | default: | 132 | default: |
133 | break; | 133 | break; |
134 | } | 134 | } |
135 | 135 | ||
136 | if (ctx->rotation == 90 || ctx->rotation == 270) { | 136 | if (ctx->rotation == 90 || ctx->rotation == 270) |
137 | cfg |= S5P_CITRGFMT_HSIZE(frame->height); | 137 | cfg |= (frame->height << 16) | frame->width; |
138 | cfg |= S5P_CITRGFMT_VSIZE(frame->width); | 138 | else |
139 | } else { | 139 | cfg |= (frame->width << 16) | frame->height; |
140 | |||
141 | cfg |= S5P_CITRGFMT_HSIZE(frame->width); | ||
142 | cfg |= S5P_CITRGFMT_VSIZE(frame->height); | ||
143 | } | ||
144 | 140 | ||
145 | writel(cfg, dev->regs + S5P_CITRGFMT); | 141 | writel(cfg, dev->regs + FIMC_REG_CITRGFMT); |
146 | 142 | ||
147 | cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK; | 143 | cfg = readl(dev->regs + FIMC_REG_CITAREA); |
144 | cfg &= ~FIMC_REG_CITAREA_MASK; | ||
148 | cfg |= (frame->width * frame->height); | 145 | cfg |= (frame->width * frame->height); |
149 | writel(cfg, dev->regs + S5P_CITAREA); | 146 | writel(cfg, dev->regs + FIMC_REG_CITAREA); |
150 | } | 147 | } |
151 | 148 | ||
152 | static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx) | 149 | static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx) |
@@ -155,87 +152,82 @@ static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx) | |||
155 | struct fimc_frame *frame = &ctx->d_frame; | 152 | struct fimc_frame *frame = &ctx->d_frame; |
156 | u32 cfg; | 153 | u32 cfg; |
157 | 154 | ||
158 | cfg = S5P_ORIG_SIZE_HOR(frame->f_width); | 155 | cfg = (frame->f_height << 16) | frame->f_width; |
159 | cfg |= S5P_ORIG_SIZE_VER(frame->f_height); | 156 | writel(cfg, dev->regs + FIMC_REG_ORGOSIZE); |
160 | writel(cfg, dev->regs + S5P_ORGOSIZE); | ||
161 | 157 | ||
162 | /* Select color space conversion equation (HD/SD size).*/ | 158 | /* Select color space conversion equation (HD/SD size).*/ |
163 | cfg = readl(dev->regs + S5P_CIGCTRL); | 159 | cfg = readl(dev->regs + FIMC_REG_CIGCTRL); |
164 | if (frame->f_width >= 1280) /* HD */ | 160 | if (frame->f_width >= 1280) /* HD */ |
165 | cfg |= S5P_CIGCTRL_CSC_ITU601_709; | 161 | cfg |= FIMC_REG_CIGCTRL_CSC_ITU601_709; |
166 | else /* SD */ | 162 | else /* SD */ |
167 | cfg &= ~S5P_CIGCTRL_CSC_ITU601_709; | 163 | cfg &= ~FIMC_REG_CIGCTRL_CSC_ITU601_709; |
168 | writel(cfg, dev->regs + S5P_CIGCTRL); | 164 | writel(cfg, dev->regs + FIMC_REG_CIGCTRL); |
169 | 165 | ||
170 | } | 166 | } |
171 | 167 | ||
172 | void fimc_hw_set_out_dma(struct fimc_ctx *ctx) | 168 | void fimc_hw_set_out_dma(struct fimc_ctx *ctx) |
173 | { | 169 | { |
174 | u32 cfg; | ||
175 | struct fimc_dev *dev = ctx->fimc_dev; | 170 | struct fimc_dev *dev = ctx->fimc_dev; |
176 | struct fimc_frame *frame = &ctx->d_frame; | 171 | struct fimc_frame *frame = &ctx->d_frame; |
177 | struct fimc_dma_offset *offset = &frame->dma_offset; | 172 | struct fimc_dma_offset *offset = &frame->dma_offset; |
178 | struct fimc_fmt *fmt = frame->fmt; | 173 | struct fimc_fmt *fmt = frame->fmt; |
174 | u32 cfg; | ||
179 | 175 | ||
180 | /* Set the input dma offsets. */ | 176 | /* Set the input dma offsets. */ |
181 | cfg = 0; | 177 | cfg = (offset->y_v << 16) | offset->y_h; |
182 | cfg |= S5P_CIO_OFFS_HOR(offset->y_h); | 178 | writel(cfg, dev->regs + FIMC_REG_CIOYOFF); |
183 | cfg |= S5P_CIO_OFFS_VER(offset->y_v); | ||
184 | writel(cfg, dev->regs + S5P_CIOYOFF); | ||
185 | 179 | ||
186 | cfg = 0; | 180 | cfg = (offset->cb_v << 16) | offset->cb_h; |
187 | cfg |= S5P_CIO_OFFS_HOR(offset->cb_h); | 181 | writel(cfg, dev->regs + FIMC_REG_CIOCBOFF); |
188 | cfg |= S5P_CIO_OFFS_VER(offset->cb_v); | ||
189 | writel(cfg, dev->regs + S5P_CIOCBOFF); | ||
190 | 182 | ||
191 | cfg = 0; | 183 | cfg = (offset->cr_v << 16) | offset->cr_h; |
192 | cfg |= S5P_CIO_OFFS_HOR(offset->cr_h); | 184 | writel(cfg, dev->regs + FIMC_REG_CIOCROFF); |
193 | cfg |= S5P_CIO_OFFS_VER(offset->cr_v); | ||
194 | writel(cfg, dev->regs + S5P_CIOCROFF); | ||
195 | 185 | ||
196 | fimc_hw_set_out_dma_size(ctx); | 186 | fimc_hw_set_out_dma_size(ctx); |
197 | 187 | ||
198 | /* Configure chroma components order. */ | 188 | /* Configure chroma components order. */ |
199 | cfg = readl(dev->regs + S5P_CIOCTRL); | 189 | cfg = readl(dev->regs + FIMC_REG_CIOCTRL); |
200 | 190 | ||
201 | cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK | | 191 | cfg &= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK | |
202 | S5P_CIOCTRL_YCBCR_PLANE_MASK | S5P_CIOCTRL_RGB16FMT_MASK); | 192 | FIMC_REG_CIOCTRL_ORDER422_MASK | |
193 | FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK | | ||
194 | FIMC_REG_CIOCTRL_RGB16FMT_MASK); | ||
203 | 195 | ||
204 | if (fmt->colplanes == 1) | 196 | if (fmt->colplanes == 1) |
205 | cfg |= ctx->out_order_1p; | 197 | cfg |= ctx->out_order_1p; |
206 | else if (fmt->colplanes == 2) | 198 | else if (fmt->colplanes == 2) |
207 | cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE; | 199 | cfg |= ctx->out_order_2p | FIMC_REG_CIOCTRL_YCBCR_2PLANE; |
208 | else if (fmt->colplanes == 3) | 200 | else if (fmt->colplanes == 3) |
209 | cfg |= S5P_CIOCTRL_YCBCR_3PLANE; | 201 | cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE; |
210 | 202 | ||
211 | if (fmt->color == S5P_FIMC_RGB565) | 203 | if (fmt->color == S5P_FIMC_RGB565) |
212 | cfg |= S5P_CIOCTRL_RGB565; | 204 | cfg |= FIMC_REG_CIOCTRL_RGB565; |
213 | else if (fmt->color == S5P_FIMC_RGB555) | 205 | else if (fmt->color == S5P_FIMC_RGB555) |
214 | cfg |= S5P_CIOCTRL_ARGB1555; | 206 | cfg |= FIMC_REG_CIOCTRL_ARGB1555; |
215 | else if (fmt->color == S5P_FIMC_RGB444) | 207 | else if (fmt->color == S5P_FIMC_RGB444) |
216 | cfg |= S5P_CIOCTRL_ARGB4444; | 208 | cfg |= FIMC_REG_CIOCTRL_ARGB4444; |
217 | 209 | ||
218 | writel(cfg, dev->regs + S5P_CIOCTRL); | 210 | writel(cfg, dev->regs + FIMC_REG_CIOCTRL); |
219 | } | 211 | } |
220 | 212 | ||
221 | static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable) | 213 | static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable) |
222 | { | 214 | { |
223 | u32 cfg = readl(dev->regs + S5P_ORGISIZE); | 215 | u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE); |
224 | if (enable) | 216 | if (enable) |
225 | cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN; | 217 | cfg |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN; |
226 | else | 218 | else |
227 | cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN; | 219 | cfg &= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN; |
228 | writel(cfg, dev->regs + S5P_ORGISIZE); | 220 | writel(cfg, dev->regs + FIMC_REG_ORGISIZE); |
229 | } | 221 | } |
230 | 222 | ||
231 | void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable) | 223 | void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable) |
232 | { | 224 | { |
233 | u32 cfg = readl(dev->regs + S5P_CIOCTRL); | 225 | u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL); |
234 | if (enable) | 226 | if (enable) |
235 | cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE; | 227 | cfg |= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE; |
236 | else | 228 | else |
237 | cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE; | 229 | cfg &= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE; |
238 | writel(cfg, dev->regs + S5P_CIOCTRL); | 230 | writel(cfg, dev->regs + FIMC_REG_CIOCTRL); |
239 | } | 231 | } |
240 | 232 | ||
241 | void fimc_hw_set_prescaler(struct fimc_ctx *ctx) | 233 | void fimc_hw_set_prescaler(struct fimc_ctx *ctx) |
@@ -245,15 +237,13 @@ void fimc_hw_set_prescaler(struct fimc_ctx *ctx) | |||
245 | u32 cfg, shfactor; | 237 | u32 cfg, shfactor; |
246 | 238 | ||
247 | shfactor = 10 - (sc->hfactor + sc->vfactor); | 239 | shfactor = 10 - (sc->hfactor + sc->vfactor); |
240 | cfg = shfactor << 28; | ||
248 | 241 | ||
249 | cfg = S5P_CISCPRERATIO_SHFACTOR(shfactor); | 242 | cfg |= (sc->pre_hratio << 16) | sc->pre_vratio; |
250 | cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio); | 243 | writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO); |
251 | cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio); | ||
252 | writel(cfg, dev->regs + S5P_CISCPRERATIO); | ||
253 | 244 | ||
254 | cfg = S5P_CISCPREDST_WIDTH(sc->pre_dst_width); | 245 | cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height; |
255 | cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height); | 246 | writel(cfg, dev->regs + FIMC_REG_CISCPREDST); |
256 | writel(cfg, dev->regs + S5P_CISCPREDST); | ||
257 | } | 247 | } |
258 | 248 | ||
259 | static void fimc_hw_set_scaler(struct fimc_ctx *ctx) | 249 | static void fimc_hw_set_scaler(struct fimc_ctx *ctx) |
@@ -263,39 +253,40 @@ static void fimc_hw_set_scaler(struct fimc_ctx *ctx) | |||
263 | struct fimc_frame *src_frame = &ctx->s_frame; | 253 | struct fimc_frame *src_frame = &ctx->s_frame; |
264 | struct fimc_frame *dst_frame = &ctx->d_frame; | 254 | struct fimc_frame *dst_frame = &ctx->d_frame; |
265 | 255 | ||
266 | u32 cfg = readl(dev->regs + S5P_CISCCTRL); | 256 | u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); |
267 | 257 | ||
268 | cfg &= ~(S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE | | 258 | cfg &= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE | FIMC_REG_CISCCTRL_CSCY2R_WIDE | |
269 | S5P_CISCCTRL_SCALEUP_H | S5P_CISCCTRL_SCALEUP_V | | 259 | FIMC_REG_CISCCTRL_SCALEUP_H | FIMC_REG_CISCCTRL_SCALEUP_V | |
270 | S5P_CISCCTRL_SCALERBYPASS | S5P_CISCCTRL_ONE2ONE | | 260 | FIMC_REG_CISCCTRL_SCALERBYPASS | FIMC_REG_CISCCTRL_ONE2ONE | |
271 | S5P_CISCCTRL_INRGB_FMT_MASK | S5P_CISCCTRL_OUTRGB_FMT_MASK | | 261 | FIMC_REG_CISCCTRL_INRGB_FMT_MASK | FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK | |
272 | S5P_CISCCTRL_INTERLACE | S5P_CISCCTRL_RGB_EXT); | 262 | FIMC_REG_CISCCTRL_INTERLACE | FIMC_REG_CISCCTRL_RGB_EXT); |
273 | 263 | ||
274 | if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW)) | 264 | if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW)) |
275 | cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE); | 265 | cfg |= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE | |
266 | FIMC_REG_CISCCTRL_CSCY2R_WIDE); | ||
276 | 267 | ||
277 | if (!sc->enabled) | 268 | if (!sc->enabled) |
278 | cfg |= S5P_CISCCTRL_SCALERBYPASS; | 269 | cfg |= FIMC_REG_CISCCTRL_SCALERBYPASS; |
279 | 270 | ||
280 | if (sc->scaleup_h) | 271 | if (sc->scaleup_h) |
281 | cfg |= S5P_CISCCTRL_SCALEUP_H; | 272 | cfg |= FIMC_REG_CISCCTRL_SCALEUP_H; |
282 | 273 | ||
283 | if (sc->scaleup_v) | 274 | if (sc->scaleup_v) |
284 | cfg |= S5P_CISCCTRL_SCALEUP_V; | 275 | cfg |= FIMC_REG_CISCCTRL_SCALEUP_V; |
285 | 276 | ||
286 | if (sc->copy_mode) | 277 | if (sc->copy_mode) |
287 | cfg |= S5P_CISCCTRL_ONE2ONE; | 278 | cfg |= FIMC_REG_CISCCTRL_ONE2ONE; |
288 | 279 | ||
289 | if (ctx->in_path == FIMC_DMA) { | 280 | if (ctx->in_path == FIMC_DMA) { |
290 | switch (src_frame->fmt->color) { | 281 | switch (src_frame->fmt->color) { |
291 | case S5P_FIMC_RGB565: | 282 | case S5P_FIMC_RGB565: |
292 | cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565; | 283 | cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565; |
293 | break; | 284 | break; |
294 | case S5P_FIMC_RGB666: | 285 | case S5P_FIMC_RGB666: |
295 | cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666; | 286 | cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666; |
296 | break; | 287 | break; |
297 | case S5P_FIMC_RGB888: | 288 | case S5P_FIMC_RGB888: |
298 | cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888; | 289 | cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888; |
299 | break; | 290 | break; |
300 | } | 291 | } |
301 | } | 292 | } |
@@ -304,19 +295,19 @@ static void fimc_hw_set_scaler(struct fimc_ctx *ctx) | |||
304 | u32 color = dst_frame->fmt->color; | 295 | u32 color = dst_frame->fmt->color; |
305 | 296 | ||
306 | if (color >= S5P_FIMC_RGB444 && color <= S5P_FIMC_RGB565) | 297 | if (color >= S5P_FIMC_RGB444 && color <= S5P_FIMC_RGB565) |
307 | cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565; | 298 | cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565; |
308 | else if (color == S5P_FIMC_RGB666) | 299 | else if (color == S5P_FIMC_RGB666) |
309 | cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666; | 300 | cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666; |
310 | else if (color == S5P_FIMC_RGB888) | 301 | else if (color == S5P_FIMC_RGB888) |
311 | cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888; | 302 | cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888; |
312 | } else { | 303 | } else { |
313 | cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888; | 304 | cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888; |
314 | 305 | ||
315 | if (ctx->flags & FIMC_SCAN_MODE_INTERLACED) | 306 | if (ctx->flags & FIMC_SCAN_MODE_INTERLACED) |
316 | cfg |= S5P_CISCCTRL_INTERLACE; | 307 | cfg |= FIMC_REG_CISCCTRL_INTERLACE; |
317 | } | 308 | } |
318 | 309 | ||
319 | writel(cfg, dev->regs + S5P_CISCCTRL); | 310 | writel(cfg, dev->regs + FIMC_REG_CISCCTRL); |
320 | } | 311 | } |
321 | 312 | ||
322 | void fimc_hw_set_mainscaler(struct fimc_ctx *ctx) | 313 | void fimc_hw_set_mainscaler(struct fimc_ctx *ctx) |
@@ -327,29 +318,30 @@ void fimc_hw_set_mainscaler(struct fimc_ctx *ctx) | |||
327 | u32 cfg; | 318 | u32 cfg; |
328 | 319 | ||
329 | dbg("main_hratio= 0x%X main_vratio= 0x%X", | 320 | dbg("main_hratio= 0x%X main_vratio= 0x%X", |
330 | sc->main_hratio, sc->main_vratio); | 321 | sc->main_hratio, sc->main_vratio); |
331 | 322 | ||
332 | fimc_hw_set_scaler(ctx); | 323 | fimc_hw_set_scaler(ctx); |
333 | 324 | ||
334 | cfg = readl(dev->regs + S5P_CISCCTRL); | 325 | cfg = readl(dev->regs + FIMC_REG_CISCCTRL); |
335 | cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK); | 326 | cfg &= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK | |
327 | FIMC_REG_CISCCTRL_MVRATIO_MASK); | ||
336 | 328 | ||
337 | if (variant->has_mainscaler_ext) { | 329 | if (variant->has_mainscaler_ext) { |
338 | cfg |= S5P_CISCCTRL_MHRATIO_EXT(sc->main_hratio); | 330 | cfg |= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc->main_hratio); |
339 | cfg |= S5P_CISCCTRL_MVRATIO_EXT(sc->main_vratio); | 331 | cfg |= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc->main_vratio); |
340 | writel(cfg, dev->regs + S5P_CISCCTRL); | 332 | writel(cfg, dev->regs + FIMC_REG_CISCCTRL); |
341 | 333 | ||
342 | cfg = readl(dev->regs + S5P_CIEXTEN); | 334 | cfg = readl(dev->regs + FIMC_REG_CIEXTEN); |
343 | 335 | ||
344 | cfg &= ~(S5P_CIEXTEN_MVRATIO_EXT_MASK | | 336 | cfg &= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK | |
345 | S5P_CIEXTEN_MHRATIO_EXT_MASK); | 337 | FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK); |
346 | cfg |= S5P_CIEXTEN_MHRATIO_EXT(sc->main_hratio); | 338 | cfg |= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc->main_hratio); |
347 | cfg |= S5P_CIEXTEN_MVRATIO_EXT(sc->main_vratio); | 339 | cfg |= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc->main_vratio); |
348 | writel(cfg, dev->regs + S5P_CIEXTEN); | 340 | writel(cfg, dev->regs + FIMC_REG_CIEXTEN); |
349 | } else { | 341 | } else { |
350 | cfg |= S5P_CISCCTRL_MHRATIO(sc->main_hratio); | 342 | cfg |= FIMC_REG_CISCCTRL_MHRATIO(sc->main_hratio); |
351 | cfg |= S5P_CISCCTRL_MVRATIO(sc->main_vratio); | 343 | cfg |= FIMC_REG_CISCCTRL_MVRATIO(sc->main_vratio); |
352 | writel(cfg, dev->regs + S5P_CISCCTRL); | 344 | writel(cfg, dev->regs + FIMC_REG_CISCCTRL); |
353 | } | 345 | } |
354 | } | 346 | } |
355 | 347 | ||
@@ -357,22 +349,24 @@ void fimc_hw_en_capture(struct fimc_ctx *ctx) | |||
357 | { | 349 | { |
358 | struct fimc_dev *dev = ctx->fimc_dev; | 350 | struct fimc_dev *dev = ctx->fimc_dev; |
359 | 351 | ||
360 | u32 cfg = readl(dev->regs + S5P_CIIMGCPT); | 352 | u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT); |
361 | 353 | ||
362 | if (ctx->out_path == FIMC_DMA) { | 354 | if (ctx->out_path == FIMC_DMA) { |
363 | /* one shot mode */ | 355 | /* one shot mode */ |
364 | cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE | S5P_CIIMGCPT_IMGCPTEN; | 356 | cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE | |
357 | FIMC_REG_CIIMGCPT_IMGCPTEN; | ||
365 | } else { | 358 | } else { |
366 | /* Continuous frame capture mode (freerun). */ | 359 | /* Continuous frame capture mode (freerun). */ |
367 | cfg &= ~(S5P_CIIMGCPT_CPT_FREN_ENABLE | | 360 | cfg &= ~(FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE | |
368 | S5P_CIIMGCPT_CPT_FRMOD_CNT); | 361 | FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT); |
369 | cfg |= S5P_CIIMGCPT_IMGCPTEN; | 362 | cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN; |
370 | } | 363 | } |
371 | 364 | ||
372 | if (ctx->scaler.enabled) | 365 | if (ctx->scaler.enabled) |
373 | cfg |= S5P_CIIMGCPT_IMGCPTEN_SC; | 366 | cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN_SC; |
374 | 367 | ||
375 | writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT); | 368 | cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN; |
369 | writel(cfg, dev->regs + FIMC_REG_CIIMGCPT); | ||
376 | } | 370 | } |
377 | 371 | ||
378 | void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active) | 372 | void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active) |
@@ -382,15 +376,14 @@ void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active) | |||
382 | u32 cfg = 0; | 376 | u32 cfg = 0; |
383 | 377 | ||
384 | if (active) { | 378 | if (active) { |
385 | cfg |= S5P_CIIMGEFF_IE_SC_AFTER | S5P_CIIMGEFF_IE_ENABLE; | 379 | cfg |= FIMC_REG_CIIMGEFF_IE_SC_AFTER | |
380 | FIMC_REG_CIIMGEFF_IE_ENABLE; | ||
386 | cfg |= effect->type; | 381 | cfg |= effect->type; |
387 | if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) { | 382 | if (effect->type == FIMC_REG_CIIMGEFF_FIN_ARBITRARY) |
388 | cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb); | 383 | cfg |= (effect->pat_cb << 13) | effect->pat_cr; |
389 | cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr); | ||
390 | } | ||
391 | } | 384 | } |
392 | 385 | ||
393 | writel(cfg, dev->regs + S5P_CIIMGEFF); | 386 | writel(cfg, dev->regs + FIMC_REG_CIIMGEFF); |
394 | } | 387 | } |
395 | 388 | ||
396 | void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx) | 389 | void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx) |
@@ -402,10 +395,10 @@ void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx) | |||
402 | if (!(frame->fmt->flags & FMT_HAS_ALPHA)) | 395 | if (!(frame->fmt->flags & FMT_HAS_ALPHA)) |
403 | return; | 396 | return; |
404 | 397 | ||
405 | cfg = readl(dev->regs + S5P_CIOCTRL); | 398 | cfg = readl(dev->regs + FIMC_REG_CIOCTRL); |
406 | cfg &= ~S5P_CIOCTRL_ALPHA_OUT_MASK; | 399 | cfg &= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK; |
407 | cfg |= (frame->alpha << 4); | 400 | cfg |= (frame->alpha << 4); |
408 | writel(cfg, dev->regs + S5P_CIOCTRL); | 401 | writel(cfg, dev->regs + FIMC_REG_CIOCTRL); |
409 | } | 402 | } |
410 | 403 | ||
411 | static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx) | 404 | static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx) |
@@ -416,15 +409,13 @@ static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx) | |||
416 | u32 cfg_r = 0; | 409 | u32 cfg_r = 0; |
417 | 410 | ||
418 | if (FIMC_LCDFIFO == ctx->out_path) | 411 | if (FIMC_LCDFIFO == ctx->out_path) |
419 | cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN; | 412 | cfg_r |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN; |
420 | 413 | ||
421 | cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width); | 414 | cfg_o |= (frame->f_height << 16) | frame->f_width; |
422 | cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height); | 415 | cfg_r |= (frame->height << 16) | frame->width; |
423 | cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width); | ||
424 | cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height); | ||
425 | 416 | ||
426 | writel(cfg_o, dev->regs + S5P_ORGISIZE); | 417 | writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE); |
427 | writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE); | 418 | writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE); |
428 | } | 419 | } |
429 | 420 | ||
430 | void fimc_hw_set_in_dma(struct fimc_ctx *ctx) | 421 | void fimc_hw_set_in_dma(struct fimc_ctx *ctx) |
@@ -435,17 +426,14 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx) | |||
435 | u32 cfg; | 426 | u32 cfg; |
436 | 427 | ||
437 | /* Set the pixel offsets. */ | 428 | /* Set the pixel offsets. */ |
438 | cfg = S5P_CIO_OFFS_HOR(offset->y_h); | 429 | cfg = (offset->y_v << 16) | offset->y_h; |
439 | cfg |= S5P_CIO_OFFS_VER(offset->y_v); | 430 | writel(cfg, dev->regs + FIMC_REG_CIIYOFF); |
440 | writel(cfg, dev->regs + S5P_CIIYOFF); | ||
441 | 431 | ||
442 | cfg = S5P_CIO_OFFS_HOR(offset->cb_h); | 432 | cfg = (offset->cb_v << 16) | offset->cb_h; |
443 | cfg |= S5P_CIO_OFFS_VER(offset->cb_v); | 433 | writel(cfg, dev->regs + FIMC_REG_CIICBOFF); |
444 | writel(cfg, dev->regs + S5P_CIICBOFF); | ||
445 | 434 | ||
446 | cfg = S5P_CIO_OFFS_HOR(offset->cr_h); | 435 | cfg = (offset->cr_v << 16) | offset->cr_h; |
447 | cfg |= S5P_CIO_OFFS_VER(offset->cr_v); | 436 | writel(cfg, dev->regs + FIMC_REG_CIICROFF); |
448 | writel(cfg, dev->regs + S5P_CIICROFF); | ||
449 | 437 | ||
450 | /* Input original and real size. */ | 438 | /* Input original and real size. */ |
451 | fimc_hw_set_in_dma_size(ctx); | 439 | fimc_hw_set_in_dma_size(ctx); |
@@ -454,61 +442,61 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx) | |||
454 | fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO); | 442 | fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO); |
455 | 443 | ||
456 | /* Set the input DMA to process single frame only. */ | 444 | /* Set the input DMA to process single frame only. */ |
457 | cfg = readl(dev->regs + S5P_MSCTRL); | 445 | cfg = readl(dev->regs + FIMC_REG_MSCTRL); |
458 | cfg &= ~(S5P_MSCTRL_INFORMAT_MASK | 446 | cfg &= ~(FIMC_REG_MSCTRL_INFORMAT_MASK |
459 | | S5P_MSCTRL_IN_BURST_COUNT_MASK | 447 | | FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK |
460 | | S5P_MSCTRL_INPUT_MASK | 448 | | FIMC_REG_MSCTRL_INPUT_MASK |
461 | | S5P_MSCTRL_C_INT_IN_MASK | 449 | | FIMC_REG_MSCTRL_C_INT_IN_MASK |
462 | | S5P_MSCTRL_2P_IN_ORDER_MASK); | 450 | | FIMC_REG_MSCTRL_2P_IN_ORDER_MASK); |
463 | 451 | ||
464 | cfg |= (S5P_MSCTRL_IN_BURST_COUNT(4) | 452 | cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4) |
465 | | S5P_MSCTRL_INPUT_MEMORY | 453 | | FIMC_REG_MSCTRL_INPUT_MEMORY |
466 | | S5P_MSCTRL_FIFO_CTRL_FULL); | 454 | | FIMC_REG_MSCTRL_FIFO_CTRL_FULL); |
467 | 455 | ||
468 | switch (frame->fmt->color) { | 456 | switch (frame->fmt->color) { |
469 | case S5P_FIMC_RGB565...S5P_FIMC_RGB888: | 457 | case S5P_FIMC_RGB565...S5P_FIMC_RGB888: |
470 | cfg |= S5P_MSCTRL_INFORMAT_RGB; | 458 | cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB; |
471 | break; | 459 | break; |
472 | case S5P_FIMC_YCBCR420: | 460 | case S5P_FIMC_YCBCR420: |
473 | cfg |= S5P_MSCTRL_INFORMAT_YCBCR420; | 461 | cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420; |
474 | 462 | ||
475 | if (frame->fmt->colplanes == 2) | 463 | if (frame->fmt->colplanes == 2) |
476 | cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE; | 464 | cfg |= ctx->in_order_2p | FIMC_REG_MSCTRL_C_INT_IN_2PLANE; |
477 | else | 465 | else |
478 | cfg |= S5P_MSCTRL_C_INT_IN_3PLANE; | 466 | cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE; |
479 | 467 | ||
480 | break; | 468 | break; |
481 | case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422: | 469 | case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422: |
482 | if (frame->fmt->colplanes == 1) { | 470 | if (frame->fmt->colplanes == 1) { |
483 | cfg |= ctx->in_order_1p | 471 | cfg |= ctx->in_order_1p |
484 | | S5P_MSCTRL_INFORMAT_YCBCR422_1P; | 472 | | FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P; |
485 | } else { | 473 | } else { |
486 | cfg |= S5P_MSCTRL_INFORMAT_YCBCR422; | 474 | cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR422; |
487 | 475 | ||
488 | if (frame->fmt->colplanes == 2) | 476 | if (frame->fmt->colplanes == 2) |
489 | cfg |= ctx->in_order_2p | 477 | cfg |= ctx->in_order_2p |
490 | | S5P_MSCTRL_C_INT_IN_2PLANE; | 478 | | FIMC_REG_MSCTRL_C_INT_IN_2PLANE; |
491 | else | 479 | else |
492 | cfg |= S5P_MSCTRL_C_INT_IN_3PLANE; | 480 | cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE; |
493 | } | 481 | } |
494 | break; | 482 | break; |
495 | default: | 483 | default: |
496 | break; | 484 | break; |
497 | } | 485 | } |
498 | 486 | ||
499 | writel(cfg, dev->regs + S5P_MSCTRL); | 487 | writel(cfg, dev->regs + FIMC_REG_MSCTRL); |
500 | 488 | ||
501 | /* Input/output DMA linear/tiled mode. */ | 489 | /* Input/output DMA linear/tiled mode. */ |
502 | cfg = readl(dev->regs + S5P_CIDMAPARAM); | 490 | cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM); |
503 | cfg &= ~S5P_CIDMAPARAM_TILE_MASK; | 491 | cfg &= ~FIMC_REG_CIDMAPARAM_TILE_MASK; |
504 | 492 | ||
505 | if (tiled_fmt(ctx->s_frame.fmt)) | 493 | if (tiled_fmt(ctx->s_frame.fmt)) |
506 | cfg |= S5P_CIDMAPARAM_R_64X32; | 494 | cfg |= FIMC_REG_CIDMAPARAM_R_64X32; |
507 | 495 | ||
508 | if (tiled_fmt(ctx->d_frame.fmt)) | 496 | if (tiled_fmt(ctx->d_frame.fmt)) |
509 | cfg |= S5P_CIDMAPARAM_W_64X32; | 497 | cfg |= FIMC_REG_CIDMAPARAM_W_64X32; |
510 | 498 | ||
511 | writel(cfg, dev->regs + S5P_CIDMAPARAM); | 499 | writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM); |
512 | } | 500 | } |
513 | 501 | ||
514 | 502 | ||
@@ -516,40 +504,40 @@ void fimc_hw_set_input_path(struct fimc_ctx *ctx) | |||
516 | { | 504 | { |
517 | struct fimc_dev *dev = ctx->fimc_dev; | 505 | struct fimc_dev *dev = ctx->fimc_dev; |
518 | 506 | ||
519 | u32 cfg = readl(dev->regs + S5P_MSCTRL); | 507 | u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL); |
520 | cfg &= ~S5P_MSCTRL_INPUT_MASK; | 508 | cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK; |
521 | 509 | ||
522 | if (ctx->in_path == FIMC_DMA) | 510 | if (ctx->in_path == FIMC_DMA) |
523 | cfg |= S5P_MSCTRL_INPUT_MEMORY; | 511 | cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY; |
524 | else | 512 | else |
525 | cfg |= S5P_MSCTRL_INPUT_EXTCAM; | 513 | cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM; |
526 | 514 | ||
527 | writel(cfg, dev->regs + S5P_MSCTRL); | 515 | writel(cfg, dev->regs + FIMC_REG_MSCTRL); |
528 | } | 516 | } |
529 | 517 | ||
530 | void fimc_hw_set_output_path(struct fimc_ctx *ctx) | 518 | void fimc_hw_set_output_path(struct fimc_ctx *ctx) |
531 | { | 519 | { |
532 | struct fimc_dev *dev = ctx->fimc_dev; | 520 | struct fimc_dev *dev = ctx->fimc_dev; |
533 | 521 | ||
534 | u32 cfg = readl(dev->regs + S5P_CISCCTRL); | 522 | u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); |
535 | cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO; | 523 | cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO; |
536 | if (ctx->out_path == FIMC_LCDFIFO) | 524 | if (ctx->out_path == FIMC_LCDFIFO) |
537 | cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO; | 525 | cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO; |
538 | writel(cfg, dev->regs + S5P_CISCCTRL); | 526 | writel(cfg, dev->regs + FIMC_REG_CISCCTRL); |
539 | } | 527 | } |
540 | 528 | ||
541 | void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr) | 529 | void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr) |
542 | { | 530 | { |
543 | u32 cfg = readl(dev->regs + S5P_CIREAL_ISIZE); | 531 | u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE); |
544 | cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS; | 532 | cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS; |
545 | writel(cfg, dev->regs + S5P_CIREAL_ISIZE); | 533 | writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE); |
546 | 534 | ||
547 | writel(paddr->y, dev->regs + S5P_CIIYSA(0)); | 535 | writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0)); |
548 | writel(paddr->cb, dev->regs + S5P_CIICBSA(0)); | 536 | writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0)); |
549 | writel(paddr->cr, dev->regs + S5P_CIICRSA(0)); | 537 | writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0)); |
550 | 538 | ||
551 | cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS; | 539 | cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS; |
552 | writel(cfg, dev->regs + S5P_CIREAL_ISIZE); | 540 | writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE); |
553 | } | 541 | } |
554 | 542 | ||
555 | void fimc_hw_set_output_addr(struct fimc_dev *dev, | 543 | void fimc_hw_set_output_addr(struct fimc_dev *dev, |
@@ -557,9 +545,9 @@ void fimc_hw_set_output_addr(struct fimc_dev *dev, | |||
557 | { | 545 | { |
558 | int i = (index == -1) ? 0 : index; | 546 | int i = (index == -1) ? 0 : index; |
559 | do { | 547 | do { |
560 | writel(paddr->y, dev->regs + S5P_CIOYSA(i)); | 548 | writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i)); |
561 | writel(paddr->cb, dev->regs + S5P_CIOCBSA(i)); | 549 | writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i)); |
562 | writel(paddr->cr, dev->regs + S5P_CIOCRSA(i)); | 550 | writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i)); |
563 | dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X", | 551 | dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X", |
564 | i, paddr->y, paddr->cb, paddr->cr); | 552 | i, paddr->y, paddr->cb, paddr->cr); |
565 | } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS); | 553 | } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS); |
@@ -568,32 +556,45 @@ void fimc_hw_set_output_addr(struct fimc_dev *dev, | |||
568 | int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, | 556 | int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, |
569 | struct s5p_fimc_isp_info *cam) | 557 | struct s5p_fimc_isp_info *cam) |
570 | { | 558 | { |
571 | u32 cfg = readl(fimc->regs + S5P_CIGCTRL); | 559 | u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL); |
572 | 560 | ||
573 | cfg &= ~(S5P_CIGCTRL_INVPOLPCLK | S5P_CIGCTRL_INVPOLVSYNC | | 561 | cfg &= ~(FIMC_REG_CIGCTRL_INVPOLPCLK | FIMC_REG_CIGCTRL_INVPOLVSYNC | |
574 | S5P_CIGCTRL_INVPOLHREF | S5P_CIGCTRL_INVPOLHSYNC | | 562 | FIMC_REG_CIGCTRL_INVPOLHREF | FIMC_REG_CIGCTRL_INVPOLHSYNC | |
575 | S5P_CIGCTRL_INVPOLFIELD); | 563 | FIMC_REG_CIGCTRL_INVPOLFIELD); |
576 | 564 | ||
577 | if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | 565 | if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
578 | cfg |= S5P_CIGCTRL_INVPOLPCLK; | 566 | cfg |= FIMC_REG_CIGCTRL_INVPOLPCLK; |
579 | 567 | ||
580 | if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) | 568 | if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
581 | cfg |= S5P_CIGCTRL_INVPOLVSYNC; | 569 | cfg |= FIMC_REG_CIGCTRL_INVPOLVSYNC; |
582 | 570 | ||
583 | if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) | 571 | if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
584 | cfg |= S5P_CIGCTRL_INVPOLHREF; | 572 | cfg |= FIMC_REG_CIGCTRL_INVPOLHREF; |
585 | 573 | ||
586 | if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) | 574 | if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
587 | cfg |= S5P_CIGCTRL_INVPOLHSYNC; | 575 | cfg |= FIMC_REG_CIGCTRL_INVPOLHSYNC; |
588 | 576 | ||
589 | if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW) | 577 | if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW) |
590 | cfg |= S5P_CIGCTRL_INVPOLFIELD; | 578 | cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD; |
591 | 579 | ||
592 | writel(cfg, fimc->regs + S5P_CIGCTRL); | 580 | writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); |
593 | 581 | ||
594 | return 0; | 582 | return 0; |
595 | } | 583 | } |
596 | 584 | ||
585 | struct mbus_pixfmt_desc { | ||
586 | u32 pixelcode; | ||
587 | u32 cisrcfmt; | ||
588 | u16 bus_width; | ||
589 | }; | ||
590 | |||
591 | static const struct mbus_pixfmt_desc pix_desc[] = { | ||
592 | { V4L2_MBUS_FMT_YUYV8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCBYCR, 8 }, | ||
593 | { V4L2_MBUS_FMT_YVYU8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCRYCB, 8 }, | ||
594 | { V4L2_MBUS_FMT_VYUY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CRYCBY, 8 }, | ||
595 | { V4L2_MBUS_FMT_UYVY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CBYCRY, 8 }, | ||
596 | }; | ||
597 | |||
597 | int fimc_hw_set_camera_source(struct fimc_dev *fimc, | 598 | int fimc_hw_set_camera_source(struct fimc_dev *fimc, |
598 | struct s5p_fimc_isp_info *cam) | 599 | struct s5p_fimc_isp_info *cam) |
599 | { | 600 | { |
@@ -602,18 +603,6 @@ int fimc_hw_set_camera_source(struct fimc_dev *fimc, | |||
602 | u32 bus_width; | 603 | u32 bus_width; |
603 | int i; | 604 | int i; |
604 | 605 | ||
605 | static const struct { | ||
606 | u32 pixelcode; | ||
607 | u32 cisrcfmt; | ||
608 | u16 bus_width; | ||
609 | } pix_desc[] = { | ||
610 | { V4L2_MBUS_FMT_YUYV8_2X8, S5P_CISRCFMT_ORDER422_YCBYCR, 8 }, | ||
611 | { V4L2_MBUS_FMT_YVYU8_2X8, S5P_CISRCFMT_ORDER422_YCRYCB, 8 }, | ||
612 | { V4L2_MBUS_FMT_VYUY8_2X8, S5P_CISRCFMT_ORDER422_CRYCBY, 8 }, | ||
613 | { V4L2_MBUS_FMT_UYVY8_2X8, S5P_CISRCFMT_ORDER422_CBYCRY, 8 }, | ||
614 | /* TODO: Add pixel codes for 16-bit bus width */ | ||
615 | }; | ||
616 | |||
617 | if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) { | 606 | if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) { |
618 | for (i = 0; i < ARRAY_SIZE(pix_desc); i++) { | 607 | for (i = 0; i < ARRAY_SIZE(pix_desc); i++) { |
619 | if (fimc->vid_cap.mf.code == pix_desc[i].pixelcode) { | 608 | if (fimc->vid_cap.mf.code == pix_desc[i].pixelcode) { |
@@ -632,41 +621,37 @@ int fimc_hw_set_camera_source(struct fimc_dev *fimc, | |||
632 | 621 | ||
633 | if (cam->bus_type == FIMC_ITU_601) { | 622 | if (cam->bus_type == FIMC_ITU_601) { |
634 | if (bus_width == 8) | 623 | if (bus_width == 8) |
635 | cfg |= S5P_CISRCFMT_ITU601_8BIT; | 624 | cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; |
636 | else if (bus_width == 16) | 625 | else if (bus_width == 16) |
637 | cfg |= S5P_CISRCFMT_ITU601_16BIT; | 626 | cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT; |
638 | } /* else defaults to ITU-R BT.656 8-bit */ | 627 | } /* else defaults to ITU-R BT.656 8-bit */ |
639 | } else if (cam->bus_type == FIMC_MIPI_CSI2) { | 628 | } else if (cam->bus_type == FIMC_MIPI_CSI2) { |
640 | if (fimc_fmt_is_jpeg(f->fmt->color)) | 629 | if (fimc_fmt_is_jpeg(f->fmt->color)) |
641 | cfg |= S5P_CISRCFMT_ITU601_8BIT; | 630 | cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; |
642 | } | 631 | } |
643 | 632 | ||
644 | cfg |= S5P_CISRCFMT_HSIZE(f->o_width) | S5P_CISRCFMT_VSIZE(f->o_height); | 633 | cfg |= (f->o_width << 16) | f->o_height; |
645 | writel(cfg, fimc->regs + S5P_CISRCFMT); | 634 | writel(cfg, fimc->regs + FIMC_REG_CISRCFMT); |
646 | return 0; | 635 | return 0; |
647 | } | 636 | } |
648 | 637 | ||
649 | 638 | void fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f) | |
650 | int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f) | ||
651 | { | 639 | { |
652 | u32 hoff2, voff2; | 640 | u32 hoff2, voff2; |
653 | 641 | ||
654 | u32 cfg = readl(fimc->regs + S5P_CIWDOFST); | 642 | u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST); |
655 | 643 | ||
656 | cfg &= ~(S5P_CIWDOFST_HOROFF_MASK | S5P_CIWDOFST_VEROFF_MASK); | 644 | cfg &= ~(FIMC_REG_CIWDOFST_HOROFF_MASK | FIMC_REG_CIWDOFST_VEROFF_MASK); |
657 | cfg |= S5P_CIWDOFST_OFF_EN | | 645 | cfg |= FIMC_REG_CIWDOFST_OFF_EN | |
658 | S5P_CIWDOFST_HOROFF(f->offs_h) | | 646 | (f->offs_h << 16) | f->offs_v; |
659 | S5P_CIWDOFST_VEROFF(f->offs_v); | ||
660 | 647 | ||
661 | writel(cfg, fimc->regs + S5P_CIWDOFST); | 648 | writel(cfg, fimc->regs + FIMC_REG_CIWDOFST); |
662 | 649 | ||
663 | /* See CIWDOFSTn register description in the datasheet for details. */ | 650 | /* See CIWDOFSTn register description in the datasheet for details. */ |
664 | hoff2 = f->o_width - f->width - f->offs_h; | 651 | hoff2 = f->o_width - f->width - f->offs_h; |
665 | voff2 = f->o_height - f->height - f->offs_v; | 652 | voff2 = f->o_height - f->height - f->offs_v; |
666 | cfg = S5P_CIWDOFST2_HOROFF(hoff2) | S5P_CIWDOFST2_VEROFF(voff2); | 653 | cfg = (hoff2 << 16) | voff2; |
667 | 654 | writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2); | |
668 | writel(cfg, fimc->regs + S5P_CIWDOFST2); | ||
669 | return 0; | ||
670 | } | 655 | } |
671 | 656 | ||
672 | int fimc_hw_set_camera_type(struct fimc_dev *fimc, | 657 | int fimc_hw_set_camera_type(struct fimc_dev *fimc, |
@@ -676,27 +661,27 @@ int fimc_hw_set_camera_type(struct fimc_dev *fimc, | |||
676 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; | 661 | struct fimc_vid_cap *vid_cap = &fimc->vid_cap; |
677 | u32 csis_data_alignment = 32; | 662 | u32 csis_data_alignment = 32; |
678 | 663 | ||
679 | cfg = readl(fimc->regs + S5P_CIGCTRL); | 664 | cfg = readl(fimc->regs + FIMC_REG_CIGCTRL); |
680 | 665 | ||
681 | /* Select ITU B interface, disable Writeback path and test pattern. */ | 666 | /* Select ITU B interface, disable Writeback path and test pattern. */ |
682 | cfg &= ~(S5P_CIGCTRL_TESTPAT_MASK | S5P_CIGCTRL_SELCAM_ITU_A | | 667 | cfg &= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK | FIMC_REG_CIGCTRL_SELCAM_ITU_A | |
683 | S5P_CIGCTRL_SELCAM_MIPI | S5P_CIGCTRL_CAMIF_SELWB | | 668 | FIMC_REG_CIGCTRL_SELCAM_MIPI | FIMC_REG_CIGCTRL_CAMIF_SELWB | |
684 | S5P_CIGCTRL_SELCAM_MIPI_A | S5P_CIGCTRL_CAM_JPEG); | 669 | FIMC_REG_CIGCTRL_SELCAM_MIPI_A | FIMC_REG_CIGCTRL_CAM_JPEG); |
685 | 670 | ||
686 | if (cam->bus_type == FIMC_MIPI_CSI2) { | 671 | if (cam->bus_type == FIMC_MIPI_CSI2) { |
687 | cfg |= S5P_CIGCTRL_SELCAM_MIPI; | 672 | cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI; |
688 | 673 | ||
689 | if (cam->mux_id == 0) | 674 | if (cam->mux_id == 0) |
690 | cfg |= S5P_CIGCTRL_SELCAM_MIPI_A; | 675 | cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI_A; |
691 | 676 | ||
692 | /* TODO: add remaining supported formats. */ | 677 | /* TODO: add remaining supported formats. */ |
693 | switch (vid_cap->mf.code) { | 678 | switch (vid_cap->mf.code) { |
694 | case V4L2_MBUS_FMT_VYUY8_2X8: | 679 | case V4L2_MBUS_FMT_VYUY8_2X8: |
695 | tmp = S5P_CSIIMGFMT_YCBCR422_8BIT; | 680 | tmp = FIMC_REG_CSIIMGFMT_YCBCR422_8BIT; |
696 | break; | 681 | break; |
697 | case V4L2_MBUS_FMT_JPEG_1X8: | 682 | case V4L2_MBUS_FMT_JPEG_1X8: |
698 | tmp = S5P_CSIIMGFMT_USER(1); | 683 | tmp = FIMC_REG_CSIIMGFMT_USER(1); |
699 | cfg |= S5P_CIGCTRL_CAM_JPEG; | 684 | cfg |= FIMC_REG_CIGCTRL_CAM_JPEG; |
700 | break; | 685 | break; |
701 | default: | 686 | default: |
702 | v4l2_err(fimc->vid_cap.vfd, | 687 | v4l2_err(fimc->vid_cap.vfd, |
@@ -706,19 +691,84 @@ int fimc_hw_set_camera_type(struct fimc_dev *fimc, | |||
706 | } | 691 | } |
707 | tmp |= (csis_data_alignment == 32) << 8; | 692 | tmp |= (csis_data_alignment == 32) << 8; |
708 | 693 | ||
709 | writel(tmp, fimc->regs + S5P_CSIIMGFMT); | 694 | writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT); |
710 | 695 | ||
711 | } else if (cam->bus_type == FIMC_ITU_601 || | 696 | } else if (cam->bus_type == FIMC_ITU_601 || |
712 | cam->bus_type == FIMC_ITU_656) { | 697 | cam->bus_type == FIMC_ITU_656) { |
713 | if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */ | 698 | if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */ |
714 | cfg |= S5P_CIGCTRL_SELCAM_ITU_A; | 699 | cfg |= FIMC_REG_CIGCTRL_SELCAM_ITU_A; |
715 | } else if (cam->bus_type == FIMC_LCD_WB) { | 700 | } else if (cam->bus_type == FIMC_LCD_WB) { |
716 | cfg |= S5P_CIGCTRL_CAMIF_SELWB; | 701 | cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB; |
717 | } else { | 702 | } else { |
718 | err("invalid camera bus type selected\n"); | 703 | err("invalid camera bus type selected\n"); |
719 | return -EINVAL; | 704 | return -EINVAL; |
720 | } | 705 | } |
721 | writel(cfg, fimc->regs + S5P_CIGCTRL); | 706 | writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); |
722 | 707 | ||
723 | return 0; | 708 | return 0; |
724 | } | 709 | } |
710 | |||
711 | void fimc_hw_clear_irq(struct fimc_dev *dev) | ||
712 | { | ||
713 | u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); | ||
714 | cfg |= FIMC_REG_CIGCTRL_IRQ_CLR; | ||
715 | writel(cfg, dev->regs + FIMC_REG_CIGCTRL); | ||
716 | } | ||
717 | |||
718 | void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on) | ||
719 | { | ||
720 | u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); | ||
721 | if (on) | ||
722 | cfg |= FIMC_REG_CISCCTRL_SCALERSTART; | ||
723 | else | ||
724 | cfg &= ~FIMC_REG_CISCCTRL_SCALERSTART; | ||
725 | writel(cfg, dev->regs + FIMC_REG_CISCCTRL); | ||
726 | } | ||
727 | |||
728 | void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on) | ||
729 | { | ||
730 | u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL); | ||
731 | if (on) | ||
732 | cfg |= FIMC_REG_MSCTRL_ENVID; | ||
733 | else | ||
734 | cfg &= ~FIMC_REG_MSCTRL_ENVID; | ||
735 | writel(cfg, dev->regs + FIMC_REG_MSCTRL); | ||
736 | } | ||
737 | |||
738 | void fimc_hw_dis_capture(struct fimc_dev *dev) | ||
739 | { | ||
740 | u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT); | ||
741 | cfg &= ~(FIMC_REG_CIIMGCPT_IMGCPTEN | FIMC_REG_CIIMGCPT_IMGCPTEN_SC); | ||
742 | writel(cfg, dev->regs + FIMC_REG_CIIMGCPT); | ||
743 | } | ||
744 | |||
745 | /* Return an index to the buffer actually being written. */ | ||
746 | u32 fimc_hw_get_frame_index(struct fimc_dev *dev) | ||
747 | { | ||
748 | u32 reg; | ||
749 | |||
750 | if (dev->variant->has_cistatus2) { | ||
751 | reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3F; | ||
752 | return reg > 0 ? --reg : reg; | ||
753 | } | ||
754 | |||
755 | reg = readl(dev->regs + FIMC_REG_CISTATUS); | ||
756 | |||
757 | return (reg & FIMC_REG_CISTATUS_FRAMECNT_MASK) >> | ||
758 | FIMC_REG_CISTATUS_FRAMECNT_SHIFT; | ||
759 | } | ||
760 | |||
761 | /* Locking: the caller holds fimc->slock */ | ||
762 | void fimc_activate_capture(struct fimc_ctx *ctx) | ||
763 | { | ||
764 | fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled); | ||
765 | fimc_hw_en_capture(ctx); | ||
766 | } | ||
767 | |||
768 | void fimc_deactivate_capture(struct fimc_dev *fimc) | ||
769 | { | ||
770 | fimc_hw_en_lastirq(fimc, true); | ||
771 | fimc_hw_dis_capture(fimc); | ||
772 | fimc_hw_enable_scaler(fimc, false); | ||
773 | fimc_hw_en_lastirq(fimc, false); | ||
774 | } | ||
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.h b/drivers/media/video/s5p-fimc/fimc-reg.h new file mode 100644 index 00000000000..1472880b94f --- /dev/null +++ b/drivers/media/video/s5p-fimc/fimc-reg.h | |||
@@ -0,0 +1,326 @@ | |||
1 | /* | ||
2 | * Samsung camera host interface (FIMC) registers definition | ||
3 | * | ||
4 | * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef FIMC_REG_H_ | ||
12 | #define FIMC_REG_H_ | ||
13 | |||
14 | #include "fimc-core.h" | ||
15 | |||
16 | /* Input source format */ | ||
17 | #define FIMC_REG_CISRCFMT 0x00 | ||
18 | #define FIMC_REG_CISRCFMT_ITU601_8BIT (1 << 31) | ||
19 | #define FIMC_REG_CISRCFMT_ITU601_16BIT (1 << 29) | ||
20 | #define FIMC_REG_CISRCFMT_ORDER422_YCBYCR (0 << 14) | ||
21 | #define FIMC_REG_CISRCFMT_ORDER422_YCRYCB (1 << 14) | ||
22 | #define FIMC_REG_CISRCFMT_ORDER422_CBYCRY (2 << 14) | ||
23 | #define FIMC_REG_CISRCFMT_ORDER422_CRYCBY (3 << 14) | ||
24 | |||
25 | /* Window offset */ | ||
26 | #define FIMC_REG_CIWDOFST 0x04 | ||
27 | #define FIMC_REG_CIWDOFST_OFF_EN (1 << 31) | ||
28 | #define FIMC_REG_CIWDOFST_CLROVFIY (1 << 30) | ||
29 | #define FIMC_REG_CIWDOFST_CLROVRLB (1 << 29) | ||
30 | #define FIMC_REG_CIWDOFST_HOROFF_MASK (0x7ff << 16) | ||
31 | #define FIMC_REG_CIWDOFST_CLROVFICB (1 << 15) | ||
32 | #define FIMC_REG_CIWDOFST_CLROVFICR (1 << 14) | ||
33 | #define FIMC_REG_CIWDOFST_VEROFF_MASK (0xfff << 0) | ||
34 | |||
35 | /* Global control */ | ||
36 | #define FIMC_REG_CIGCTRL 0x08 | ||
37 | #define FIMC_REG_CIGCTRL_SWRST (1 << 31) | ||
38 | #define FIMC_REG_CIGCTRL_CAMRST_A (1 << 30) | ||
39 | #define FIMC_REG_CIGCTRL_SELCAM_ITU_A (1 << 29) | ||
40 | #define FIMC_REG_CIGCTRL_TESTPAT_NORMAL (0 << 27) | ||
41 | #define FIMC_REG_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27) | ||
42 | #define FIMC_REG_CIGCTRL_TESTPAT_HOR_INC (2 << 27) | ||
43 | #define FIMC_REG_CIGCTRL_TESTPAT_VER_INC (3 << 27) | ||
44 | #define FIMC_REG_CIGCTRL_TESTPAT_MASK (3 << 27) | ||
45 | #define FIMC_REG_CIGCTRL_TESTPAT_SHIFT 27 | ||
46 | #define FIMC_REG_CIGCTRL_INVPOLPCLK (1 << 26) | ||
47 | #define FIMC_REG_CIGCTRL_INVPOLVSYNC (1 << 25) | ||
48 | #define FIMC_REG_CIGCTRL_INVPOLHREF (1 << 24) | ||
49 | #define FIMC_REG_CIGCTRL_IRQ_OVFEN (1 << 22) | ||
50 | #define FIMC_REG_CIGCTRL_HREF_MASK (1 << 21) | ||
51 | #define FIMC_REG_CIGCTRL_IRQ_LEVEL (1 << 20) | ||
52 | #define FIMC_REG_CIGCTRL_IRQ_CLR (1 << 19) | ||
53 | #define FIMC_REG_CIGCTRL_IRQ_ENABLE (1 << 16) | ||
54 | #define FIMC_REG_CIGCTRL_SHDW_DISABLE (1 << 12) | ||
55 | #define FIMC_REG_CIGCTRL_CAM_JPEG (1 << 8) | ||
56 | #define FIMC_REG_CIGCTRL_SELCAM_MIPI_A (1 << 7) | ||
57 | #define FIMC_REG_CIGCTRL_CAMIF_SELWB (1 << 6) | ||
58 | /* 0 - ITU601; 1 - ITU709 */ | ||
59 | #define FIMC_REG_CIGCTRL_CSC_ITU601_709 (1 << 5) | ||
60 | #define FIMC_REG_CIGCTRL_INVPOLHSYNC (1 << 4) | ||
61 | #define FIMC_REG_CIGCTRL_SELCAM_MIPI (1 << 3) | ||
62 | #define FIMC_REG_CIGCTRL_INVPOLFIELD (1 << 1) | ||
63 | #define FIMC_REG_CIGCTRL_INTERLACE (1 << 0) | ||
64 | |||
65 | /* Window offset 2 */ | ||
66 | #define FIMC_REG_CIWDOFST2 0x14 | ||
67 | #define FIMC_REG_CIWDOFST2_HOROFF_MASK (0xfff << 16) | ||
68 | #define FIMC_REG_CIWDOFST2_VEROFF_MASK (0xfff << 0) | ||
69 | |||
70 | /* Output DMA Y/Cb/Cr plane start addresses */ | ||
71 | #define FIMC_REG_CIOYSA(n) (0x18 + (n) * 4) | ||
72 | #define FIMC_REG_CIOCBSA(n) (0x28 + (n) * 4) | ||
73 | #define FIMC_REG_CIOCRSA(n) (0x38 + (n) * 4) | ||
74 | |||
75 | /* Target image format */ | ||
76 | #define FIMC_REG_CITRGFMT 0x48 | ||
77 | #define FIMC_REG_CITRGFMT_INROT90 (1 << 31) | ||
78 | #define FIMC_REG_CITRGFMT_YCBCR420 (0 << 29) | ||
79 | #define FIMC_REG_CITRGFMT_YCBCR422 (1 << 29) | ||
80 | #define FIMC_REG_CITRGFMT_YCBCR422_1P (2 << 29) | ||
81 | #define FIMC_REG_CITRGFMT_RGB (3 << 29) | ||
82 | #define FIMC_REG_CITRGFMT_FMT_MASK (3 << 29) | ||
83 | #define FIMC_REG_CITRGFMT_HSIZE_MASK (0xfff << 16) | ||
84 | #define FIMC_REG_CITRGFMT_FLIP_SHIFT 14 | ||
85 | #define FIMC_REG_CITRGFMT_FLIP_NORMAL (0 << 14) | ||
86 | #define FIMC_REG_CITRGFMT_FLIP_X_MIRROR (1 << 14) | ||
87 | #define FIMC_REG_CITRGFMT_FLIP_Y_MIRROR (2 << 14) | ||
88 | #define FIMC_REG_CITRGFMT_FLIP_180 (3 << 14) | ||
89 | #define FIMC_REG_CITRGFMT_FLIP_MASK (3 << 14) | ||
90 | #define FIMC_REG_CITRGFMT_OUTROT90 (1 << 13) | ||
91 | #define FIMC_REG_CITRGFMT_VSIZE_MASK (0xfff << 0) | ||
92 | |||
93 | /* Output DMA control */ | ||
94 | #define FIMC_REG_CIOCTRL 0x4c | ||
95 | #define FIMC_REG_CIOCTRL_ORDER422_MASK (3 << 0) | ||
96 | #define FIMC_REG_CIOCTRL_ORDER422_CRYCBY (0 << 0) | ||
97 | #define FIMC_REG_CIOCTRL_ORDER422_CBYCRY (1 << 0) | ||
98 | #define FIMC_REG_CIOCTRL_ORDER422_YCRYCB (2 << 0) | ||
99 | #define FIMC_REG_CIOCTRL_ORDER422_YCBYCR (3 << 0) | ||
100 | #define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE (1 << 2) | ||
101 | #define FIMC_REG_CIOCTRL_YCBCR_3PLANE (0 << 3) | ||
102 | #define FIMC_REG_CIOCTRL_YCBCR_2PLANE (1 << 3) | ||
103 | #define FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) | ||
104 | #define FIMC_REG_CIOCTRL_ALPHA_OUT_MASK (0xff << 4) | ||
105 | #define FIMC_REG_CIOCTRL_RGB16FMT_MASK (3 << 16) | ||
106 | #define FIMC_REG_CIOCTRL_RGB565 (0 << 16) | ||
107 | #define FIMC_REG_CIOCTRL_ARGB1555 (1 << 16) | ||
108 | #define FIMC_REG_CIOCTRL_ARGB4444 (2 << 16) | ||
109 | #define FIMC_REG_CIOCTRL_ORDER2P_SHIFT 24 | ||
110 | #define FIMC_REG_CIOCTRL_ORDER2P_MASK (3 << 24) | ||
111 | #define FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24) | ||
112 | |||
113 | /* Pre-scaler control 1 */ | ||
114 | #define FIMC_REG_CISCPRERATIO 0x50 | ||
115 | |||
116 | #define FIMC_REG_CISCPREDST 0x54 | ||
117 | |||
118 | /* Main scaler control */ | ||
119 | #define FIMC_REG_CISCCTRL 0x58 | ||
120 | #define FIMC_REG_CISCCTRL_SCALERBYPASS (1 << 31) | ||
121 | #define FIMC_REG_CISCCTRL_SCALEUP_H (1 << 30) | ||
122 | #define FIMC_REG_CISCCTRL_SCALEUP_V (1 << 29) | ||
123 | #define FIMC_REG_CISCCTRL_CSCR2Y_WIDE (1 << 28) | ||
124 | #define FIMC_REG_CISCCTRL_CSCY2R_WIDE (1 << 27) | ||
125 | #define FIMC_REG_CISCCTRL_LCDPATHEN_FIFO (1 << 26) | ||
126 | #define FIMC_REG_CISCCTRL_INTERLACE (1 << 25) | ||
127 | #define FIMC_REG_CISCCTRL_SCALERSTART (1 << 15) | ||
128 | #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB565 (0 << 13) | ||
129 | #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB666 (1 << 13) | ||
130 | #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB888 (2 << 13) | ||
131 | #define FIMC_REG_CISCCTRL_INRGB_FMT_MASK (3 << 13) | ||
132 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11) | ||
133 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) | ||
134 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) | ||
135 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK (3 << 11) | ||
136 | #define FIMC_REG_CISCCTRL_RGB_EXT (1 << 10) | ||
137 | #define FIMC_REG_CISCCTRL_ONE2ONE (1 << 9) | ||
138 | #define FIMC_REG_CISCCTRL_MHRATIO(x) ((x) << 16) | ||
139 | #define FIMC_REG_CISCCTRL_MVRATIO(x) ((x) << 0) | ||
140 | #define FIMC_REG_CISCCTRL_MHRATIO_MASK (0x1ff << 16) | ||
141 | #define FIMC_REG_CISCCTRL_MVRATIO_MASK (0x1ff << 0) | ||
142 | #define FIMC_REG_CISCCTRL_MHRATIO_EXT(x) (((x) >> 6) << 16) | ||
143 | #define FIMC_REG_CISCCTRL_MVRATIO_EXT(x) (((x) >> 6) << 0) | ||
144 | |||
145 | /* Target area */ | ||
146 | #define FIMC_REG_CITAREA 0x5c | ||
147 | #define FIMC_REG_CITAREA_MASK 0x0fffffff | ||
148 | |||
149 | /* General status */ | ||
150 | #define FIMC_REG_CISTATUS 0x64 | ||
151 | #define FIMC_REG_CISTATUS_OVFIY (1 << 31) | ||
152 | #define FIMC_REG_CISTATUS_OVFICB (1 << 30) | ||
153 | #define FIMC_REG_CISTATUS_OVFICR (1 << 29) | ||
154 | #define FIMC_REG_CISTATUS_VSYNC (1 << 28) | ||
155 | #define FIMC_REG_CISTATUS_FRAMECNT_MASK (3 << 26) | ||
156 | #define FIMC_REG_CISTATUS_FRAMECNT_SHIFT 26 | ||
157 | #define FIMC_REG_CISTATUS_WINOFF_EN (1 << 25) | ||
158 | #define FIMC_REG_CISTATUS_IMGCPT_EN (1 << 22) | ||
159 | #define FIMC_REG_CISTATUS_IMGCPT_SCEN (1 << 21) | ||
160 | #define FIMC_REG_CISTATUS_VSYNC_A (1 << 20) | ||
161 | #define FIMC_REG_CISTATUS_VSYNC_B (1 << 19) | ||
162 | #define FIMC_REG_CISTATUS_OVRLB (1 << 18) | ||
163 | #define FIMC_REG_CISTATUS_FRAME_END (1 << 17) | ||
164 | #define FIMC_REG_CISTATUS_LASTCAPT_END (1 << 16) | ||
165 | #define FIMC_REG_CISTATUS_VVALID_A (1 << 15) | ||
166 | #define FIMC_REG_CISTATUS_VVALID_B (1 << 14) | ||
167 | |||
168 | /* Indexes to the last and the currently processed buffer. */ | ||
169 | #define FIMC_REG_CISTATUS2 0x68 | ||
170 | |||
171 | /* Image capture control */ | ||
172 | #define FIMC_REG_CIIMGCPT 0xc0 | ||
173 | #define FIMC_REG_CIIMGCPT_IMGCPTEN (1 << 31) | ||
174 | #define FIMC_REG_CIIMGCPT_IMGCPTEN_SC (1 << 30) | ||
175 | #define FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE (1 << 25) | ||
176 | #define FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) | ||
177 | |||
178 | /* Frame capture sequence */ | ||
179 | #define FIMC_REG_CICPTSEQ 0xc4 | ||
180 | |||
181 | /* Image effect */ | ||
182 | #define FIMC_REG_CIIMGEFF 0xd0 | ||
183 | #define FIMC_REG_CIIMGEFF_IE_ENABLE (1 << 30) | ||
184 | #define FIMC_REG_CIIMGEFF_IE_SC_BEFORE (0 << 29) | ||
185 | #define FIMC_REG_CIIMGEFF_IE_SC_AFTER (1 << 29) | ||
186 | #define FIMC_REG_CIIMGEFF_FIN_BYPASS (0 << 26) | ||
187 | #define FIMC_REG_CIIMGEFF_FIN_ARBITRARY (1 << 26) | ||
188 | #define FIMC_REG_CIIMGEFF_FIN_NEGATIVE (2 << 26) | ||
189 | #define FIMC_REG_CIIMGEFF_FIN_ARTFREEZE (3 << 26) | ||
190 | #define FIMC_REG_CIIMGEFF_FIN_EMBOSSING (4 << 26) | ||
191 | #define FIMC_REG_CIIMGEFF_FIN_SILHOUETTE (5 << 26) | ||
192 | #define FIMC_REG_CIIMGEFF_FIN_MASK (7 << 26) | ||
193 | #define FIMC_REG_CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | 0xff) | ||
194 | |||
195 | /* Input DMA Y/Cb/Cr plane start address 0/1 */ | ||
196 | #define FIMC_REG_CIIYSA(n) (0xd4 + (n) * 0x70) | ||
197 | #define FIMC_REG_CIICBSA(n) (0xd8 + (n) * 0x70) | ||
198 | #define FIMC_REG_CIICRSA(n) (0xdc + (n) * 0x70) | ||
199 | |||
200 | /* Real input DMA image size */ | ||
201 | #define FIMC_REG_CIREAL_ISIZE 0xf8 | ||
202 | #define FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN (1 << 31) | ||
203 | #define FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS (1 << 30) | ||
204 | |||
205 | /* Input DMA control */ | ||
206 | #define FIMC_REG_MSCTRL 0xfc | ||
207 | #define FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK (0xf << 24) | ||
208 | #define FIMC_REG_MSCTRL_2P_IN_ORDER_MASK (3 << 16) | ||
209 | #define FIMC_REG_MSCTRL_2P_IN_ORDER_SHIFT 16 | ||
210 | #define FIMC_REG_MSCTRL_C_INT_IN_3PLANE (0 << 15) | ||
211 | #define FIMC_REG_MSCTRL_C_INT_IN_2PLANE (1 << 15) | ||
212 | #define FIMC_REG_MSCTRL_C_INT_IN_MASK (1 << 15) | ||
213 | #define FIMC_REG_MSCTRL_FLIP_SHIFT 13 | ||
214 | #define FIMC_REG_MSCTRL_FLIP_MASK (3 << 13) | ||
215 | #define FIMC_REG_MSCTRL_FLIP_NORMAL (0 << 13) | ||
216 | #define FIMC_REG_MSCTRL_FLIP_X_MIRROR (1 << 13) | ||
217 | #define FIMC_REG_MSCTRL_FLIP_Y_MIRROR (2 << 13) | ||
218 | #define FIMC_REG_MSCTRL_FLIP_180 (3 << 13) | ||
219 | #define FIMC_REG_MSCTRL_FIFO_CTRL_FULL (1 << 12) | ||
220 | #define FIMC_REG_MSCTRL_ORDER422_SHIFT 4 | ||
221 | #define FIMC_REG_MSCTRL_ORDER422_YCBYCR (0 << 4) | ||
222 | #define FIMC_REG_MSCTRL_ORDER422_CBYCRY (1 << 4) | ||
223 | #define FIMC_REG_MSCTRL_ORDER422_YCRYCB (2 << 4) | ||
224 | #define FIMC_REG_MSCTRL_ORDER422_CRYCBY (3 << 4) | ||
225 | #define FIMC_REG_MSCTRL_ORDER422_MASK (3 << 4) | ||
226 | #define FIMC_REG_MSCTRL_INPUT_EXTCAM (0 << 3) | ||
227 | #define FIMC_REG_MSCTRL_INPUT_MEMORY (1 << 3) | ||
228 | #define FIMC_REG_MSCTRL_INPUT_MASK (1 << 3) | ||
229 | #define FIMC_REG_MSCTRL_INFORMAT_YCBCR420 (0 << 1) | ||
230 | #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422 (1 << 1) | ||
231 | #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1) | ||
232 | #define FIMC_REG_MSCTRL_INFORMAT_RGB (3 << 1) | ||
233 | #define FIMC_REG_MSCTRL_INFORMAT_MASK (3 << 1) | ||
234 | #define FIMC_REG_MSCTRL_ENVID (1 << 0) | ||
235 | #define FIMC_REG_MSCTRL_IN_BURST_COUNT(x) ((x) << 24) | ||
236 | |||
237 | /* Output DMA Y/Cb/Cr offset */ | ||
238 | #define FIMC_REG_CIOYOFF 0x168 | ||
239 | #define FIMC_REG_CIOCBOFF 0x16c | ||
240 | #define FIMC_REG_CIOCROFF 0x170 | ||
241 | |||
242 | /* Input DMA Y/Cb/Cr offset */ | ||
243 | #define FIMC_REG_CIIYOFF 0x174 | ||
244 | #define FIMC_REG_CIICBOFF 0x178 | ||
245 | #define FIMC_REG_CIICROFF 0x17c | ||
246 | |||
247 | /* Input DMA original image size */ | ||
248 | #define FIMC_REG_ORGISIZE 0x180 | ||
249 | |||
250 | /* Output DMA original image size */ | ||
251 | #define FIMC_REG_ORGOSIZE 0x184 | ||
252 | |||
253 | /* Real output DMA image size (extension register) */ | ||
254 | #define FIMC_REG_CIEXTEN 0x188 | ||
255 | #define FIMC_REG_CIEXTEN_MHRATIO_EXT(x) (((x) & 0x3f) << 10) | ||
256 | #define FIMC_REG_CIEXTEN_MVRATIO_EXT(x) ((x) & 0x3f) | ||
257 | #define FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK (0x3f << 10) | ||
258 | #define FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK 0x3f | ||
259 | |||
260 | #define FIMC_REG_CIDMAPARAM 0x18c | ||
261 | #define FIMC_REG_CIDMAPARAM_R_LINEAR (0 << 29) | ||
262 | #define FIMC_REG_CIDMAPARAM_R_64X32 (3 << 29) | ||
263 | #define FIMC_REG_CIDMAPARAM_W_LINEAR (0 << 13) | ||
264 | #define FIMC_REG_CIDMAPARAM_W_64X32 (3 << 13) | ||
265 | #define FIMC_REG_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13)) | ||
266 | |||
267 | /* MIPI CSI image format */ | ||
268 | #define FIMC_REG_CSIIMGFMT 0x194 | ||
269 | #define FIMC_REG_CSIIMGFMT_YCBCR422_8BIT 0x1e | ||
270 | #define FIMC_REG_CSIIMGFMT_RAW8 0x2a | ||
271 | #define FIMC_REG_CSIIMGFMT_RAW10 0x2b | ||
272 | #define FIMC_REG_CSIIMGFMT_RAW12 0x2c | ||
273 | /* User defined formats. x = 0...16. */ | ||
274 | #define FIMC_REG_CSIIMGFMT_USER(x) (0x30 + x - 1) | ||
275 | |||
276 | /* Output frame buffer sequence mask */ | ||
277 | #define FIMC_REG_CIFCNTSEQ 0x1fc | ||
278 | |||
279 | /* | ||
280 | * Function declarations | ||
281 | */ | ||
282 | void fimc_hw_reset(struct fimc_dev *fimc); | ||
283 | void fimc_hw_set_rotation(struct fimc_ctx *ctx); | ||
284 | void fimc_hw_set_target_format(struct fimc_ctx *ctx); | ||
285 | void fimc_hw_set_out_dma(struct fimc_ctx *ctx); | ||
286 | void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable); | ||
287 | void fimc_hw_en_irq(struct fimc_dev *fimc, int enable); | ||
288 | void fimc_hw_set_prescaler(struct fimc_ctx *ctx); | ||
289 | void fimc_hw_set_mainscaler(struct fimc_ctx *ctx); | ||
290 | void fimc_hw_en_capture(struct fimc_ctx *ctx); | ||
291 | void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active); | ||
292 | void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx); | ||
293 | void fimc_hw_set_in_dma(struct fimc_ctx *ctx); | ||
294 | void fimc_hw_set_input_path(struct fimc_ctx *ctx); | ||
295 | void fimc_hw_set_output_path(struct fimc_ctx *ctx); | ||
296 | void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr); | ||
297 | void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr, | ||
298 | int index); | ||
299 | int fimc_hw_set_camera_source(struct fimc_dev *fimc, | ||
300 | struct s5p_fimc_isp_info *cam); | ||
301 | void fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f); | ||
302 | int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, | ||
303 | struct s5p_fimc_isp_info *cam); | ||
304 | int fimc_hw_set_camera_type(struct fimc_dev *fimc, | ||
305 | struct s5p_fimc_isp_info *cam); | ||
306 | void fimc_hw_clear_irq(struct fimc_dev *dev); | ||
307 | void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on); | ||
308 | void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on); | ||
309 | void fimc_hw_dis_capture(struct fimc_dev *dev); | ||
310 | u32 fimc_hw_get_frame_index(struct fimc_dev *dev); | ||
311 | void fimc_activate_capture(struct fimc_ctx *ctx); | ||
312 | void fimc_deactivate_capture(struct fimc_dev *fimc); | ||
313 | |||
314 | /** | ||
315 | * fimc_hw_set_dma_seq - configure output DMA buffer sequence | ||
316 | * @mask: bitmask for the DMA output buffer registers, set to 0 to skip buffer | ||
317 | * This function masks output DMA ring buffers, it allows to select which of | ||
318 | * the 32 available output buffer address registers will be used by the DMA | ||
319 | * engine. | ||
320 | */ | ||
321 | static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask) | ||
322 | { | ||
323 | writel(mask, dev->regs + FIMC_REG_CIFCNTSEQ); | ||
324 | } | ||
325 | |||
326 | #endif /* FIMC_REG_H_ */ | ||
diff --git a/drivers/media/video/s5p-fimc/regs-fimc.h b/drivers/media/video/s5p-fimc/regs-fimc.h deleted file mode 100644 index c7a5bc51d57..00000000000 --- a/drivers/media/video/s5p-fimc/regs-fimc.h +++ /dev/null | |||
@@ -1,301 +0,0 @@ | |||
1 | /* | ||
2 | * Register definition file for Samsung Camera Interface (FIMC) driver | ||
3 | * | ||
4 | * Copyright (c) 2010 Samsung Electronics | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef REGS_FIMC_H_ | ||
12 | #define REGS_FIMC_H_ | ||
13 | |||
14 | /* Input source format */ | ||
15 | #define S5P_CISRCFMT 0x00 | ||
16 | #define S5P_CISRCFMT_ITU601_8BIT (1 << 31) | ||
17 | #define S5P_CISRCFMT_ITU601_16BIT (1 << 29) | ||
18 | #define S5P_CISRCFMT_ORDER422_YCBYCR (0 << 14) | ||
19 | #define S5P_CISRCFMT_ORDER422_YCRYCB (1 << 14) | ||
20 | #define S5P_CISRCFMT_ORDER422_CBYCRY (2 << 14) | ||
21 | #define S5P_CISRCFMT_ORDER422_CRYCBY (3 << 14) | ||
22 | #define S5P_CISRCFMT_HSIZE(x) ((x) << 16) | ||
23 | #define S5P_CISRCFMT_VSIZE(x) ((x) << 0) | ||
24 | |||
25 | /* Window offset */ | ||
26 | #define S5P_CIWDOFST 0x04 | ||
27 | #define S5P_CIWDOFST_OFF_EN (1 << 31) | ||
28 | #define S5P_CIWDOFST_CLROVFIY (1 << 30) | ||
29 | #define S5P_CIWDOFST_CLROVRLB (1 << 29) | ||
30 | #define S5P_CIWDOFST_HOROFF_MASK (0x7ff << 16) | ||
31 | #define S5P_CIWDOFST_CLROVFICB (1 << 15) | ||
32 | #define S5P_CIWDOFST_CLROVFICR (1 << 14) | ||
33 | #define S5P_CIWDOFST_HOROFF(x) ((x) << 16) | ||
34 | #define S5P_CIWDOFST_VEROFF(x) ((x) << 0) | ||
35 | #define S5P_CIWDOFST_VEROFF_MASK (0xfff << 0) | ||
36 | |||
37 | /* Global control */ | ||
38 | #define S5P_CIGCTRL 0x08 | ||
39 | #define S5P_CIGCTRL_SWRST (1 << 31) | ||
40 | #define S5P_CIGCTRL_CAMRST_A (1 << 30) | ||
41 | #define S5P_CIGCTRL_SELCAM_ITU_A (1 << 29) | ||
42 | #define S5P_CIGCTRL_TESTPAT_NORMAL (0 << 27) | ||
43 | #define S5P_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27) | ||
44 | #define S5P_CIGCTRL_TESTPAT_HOR_INC (2 << 27) | ||
45 | #define S5P_CIGCTRL_TESTPAT_VER_INC (3 << 27) | ||
46 | #define S5P_CIGCTRL_TESTPAT_MASK (3 << 27) | ||
47 | #define S5P_CIGCTRL_TESTPAT_SHIFT (27) | ||
48 | #define S5P_CIGCTRL_INVPOLPCLK (1 << 26) | ||
49 | #define S5P_CIGCTRL_INVPOLVSYNC (1 << 25) | ||
50 | #define S5P_CIGCTRL_INVPOLHREF (1 << 24) | ||
51 | #define S5P_CIGCTRL_IRQ_OVFEN (1 << 22) | ||
52 | #define S5P_CIGCTRL_HREF_MASK (1 << 21) | ||
53 | #define S5P_CIGCTRL_IRQ_LEVEL (1 << 20) | ||
54 | #define S5P_CIGCTRL_IRQ_CLR (1 << 19) | ||
55 | #define S5P_CIGCTRL_IRQ_ENABLE (1 << 16) | ||
56 | #define S5P_CIGCTRL_SHDW_DISABLE (1 << 12) | ||
57 | #define S5P_CIGCTRL_CAM_JPEG (1 << 8) | ||
58 | #define S5P_CIGCTRL_SELCAM_MIPI_A (1 << 7) | ||
59 | #define S5P_CIGCTRL_CAMIF_SELWB (1 << 6) | ||
60 | /* 0 - ITU601; 1 - ITU709 */ | ||
61 | #define S5P_CIGCTRL_CSC_ITU601_709 (1 << 5) | ||
62 | #define S5P_CIGCTRL_INVPOLHSYNC (1 << 4) | ||
63 | #define S5P_CIGCTRL_SELCAM_MIPI (1 << 3) | ||
64 | #define S5P_CIGCTRL_INVPOLFIELD (1 << 1) | ||
65 | #define S5P_CIGCTRL_INTERLACE (1 << 0) | ||
66 | |||
67 | /* Window offset 2 */ | ||
68 | #define S5P_CIWDOFST2 0x14 | ||
69 | #define S5P_CIWDOFST2_HOROFF_MASK (0xfff << 16) | ||
70 | #define S5P_CIWDOFST2_VEROFF_MASK (0xfff << 0) | ||
71 | #define S5P_CIWDOFST2_HOROFF(x) ((x) << 16) | ||
72 | #define S5P_CIWDOFST2_VEROFF(x) ((x) << 0) | ||
73 | |||
74 | /* Output DMA Y/Cb/Cr plane start addresses */ | ||
75 | #define S5P_CIOYSA(n) (0x18 + (n) * 4) | ||
76 | #define S5P_CIOCBSA(n) (0x28 + (n) * 4) | ||
77 | #define S5P_CIOCRSA(n) (0x38 + (n) * 4) | ||
78 | |||
79 | /* Target image format */ | ||
80 | #define S5P_CITRGFMT 0x48 | ||
81 | #define S5P_CITRGFMT_INROT90 (1 << 31) | ||
82 | #define S5P_CITRGFMT_YCBCR420 (0 << 29) | ||
83 | #define S5P_CITRGFMT_YCBCR422 (1 << 29) | ||
84 | #define S5P_CITRGFMT_YCBCR422_1P (2 << 29) | ||
85 | #define S5P_CITRGFMT_RGB (3 << 29) | ||
86 | #define S5P_CITRGFMT_FMT_MASK (3 << 29) | ||
87 | #define S5P_CITRGFMT_HSIZE_MASK (0xfff << 16) | ||
88 | #define S5P_CITRGFMT_FLIP_SHIFT (14) | ||
89 | #define S5P_CITRGFMT_FLIP_NORMAL (0 << 14) | ||
90 | #define S5P_CITRGFMT_FLIP_X_MIRROR (1 << 14) | ||
91 | #define S5P_CITRGFMT_FLIP_Y_MIRROR (2 << 14) | ||
92 | #define S5P_CITRGFMT_FLIP_180 (3 << 14) | ||
93 | #define S5P_CITRGFMT_FLIP_MASK (3 << 14) | ||
94 | #define S5P_CITRGFMT_OUTROT90 (1 << 13) | ||
95 | #define S5P_CITRGFMT_VSIZE_MASK (0xfff << 0) | ||
96 | #define S5P_CITRGFMT_HSIZE(x) ((x) << 16) | ||
97 | #define S5P_CITRGFMT_VSIZE(x) ((x) << 0) | ||
98 | |||
99 | /* Output DMA control */ | ||
100 | #define S5P_CIOCTRL 0x4c | ||
101 | #define S5P_CIOCTRL_ORDER422_MASK (3 << 0) | ||
102 | #define S5P_CIOCTRL_ORDER422_CRYCBY (0 << 0) | ||
103 | #define S5P_CIOCTRL_ORDER422_CBYCRY (1 << 0) | ||
104 | #define S5P_CIOCTRL_ORDER422_YCRYCB (2 << 0) | ||
105 | #define S5P_CIOCTRL_ORDER422_YCBYCR (3 << 0) | ||
106 | #define S5P_CIOCTRL_LASTIRQ_ENABLE (1 << 2) | ||
107 | #define S5P_CIOCTRL_YCBCR_3PLANE (0 << 3) | ||
108 | #define S5P_CIOCTRL_YCBCR_2PLANE (1 << 3) | ||
109 | #define S5P_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) | ||
110 | #define S5P_CIOCTRL_ALPHA_OUT_MASK (0xff << 4) | ||
111 | #define S5P_CIOCTRL_RGB16FMT_MASK (3 << 16) | ||
112 | #define S5P_CIOCTRL_RGB565 (0 << 16) | ||
113 | #define S5P_CIOCTRL_ARGB1555 (1 << 16) | ||
114 | #define S5P_CIOCTRL_ARGB4444 (2 << 16) | ||
115 | #define S5P_CIOCTRL_ORDER2P_SHIFT (24) | ||
116 | #define S5P_CIOCTRL_ORDER2P_MASK (3 << 24) | ||
117 | #define S5P_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24) | ||
118 | |||
119 | /* Pre-scaler control 1 */ | ||
120 | #define S5P_CISCPRERATIO 0x50 | ||
121 | #define S5P_CISCPRERATIO_SHFACTOR(x) ((x) << 28) | ||
122 | #define S5P_CISCPRERATIO_HOR(x) ((x) << 16) | ||
123 | #define S5P_CISCPRERATIO_VER(x) ((x) << 0) | ||
124 | |||
125 | #define S5P_CISCPREDST 0x54 | ||
126 | #define S5P_CISCPREDST_WIDTH(x) ((x) << 16) | ||
127 | #define S5P_CISCPREDST_HEIGHT(x) ((x) << 0) | ||
128 | |||
129 | /* Main scaler control */ | ||
130 | #define S5P_CISCCTRL 0x58 | ||
131 | #define S5P_CISCCTRL_SCALERBYPASS (1 << 31) | ||
132 | #define S5P_CISCCTRL_SCALEUP_H (1 << 30) | ||
133 | #define S5P_CISCCTRL_SCALEUP_V (1 << 29) | ||
134 | #define S5P_CISCCTRL_CSCR2Y_WIDE (1 << 28) | ||
135 | #define S5P_CISCCTRL_CSCY2R_WIDE (1 << 27) | ||
136 | #define S5P_CISCCTRL_LCDPATHEN_FIFO (1 << 26) | ||
137 | #define S5P_CISCCTRL_INTERLACE (1 << 25) | ||
138 | #define S5P_CISCCTRL_SCALERSTART (1 << 15) | ||
139 | #define S5P_CISCCTRL_INRGB_FMT_RGB565 (0 << 13) | ||
140 | #define S5P_CISCCTRL_INRGB_FMT_RGB666 (1 << 13) | ||
141 | #define S5P_CISCCTRL_INRGB_FMT_RGB888 (2 << 13) | ||
142 | #define S5P_CISCCTRL_INRGB_FMT_MASK (3 << 13) | ||
143 | #define S5P_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11) | ||
144 | #define S5P_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) | ||
145 | #define S5P_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) | ||
146 | #define S5P_CISCCTRL_OUTRGB_FMT_MASK (3 << 11) | ||
147 | #define S5P_CISCCTRL_RGB_EXT (1 << 10) | ||
148 | #define S5P_CISCCTRL_ONE2ONE (1 << 9) | ||
149 | #define S5P_CISCCTRL_MHRATIO(x) ((x) << 16) | ||
150 | #define S5P_CISCCTRL_MVRATIO(x) ((x) << 0) | ||
151 | #define S5P_CISCCTRL_MHRATIO_MASK (0x1ff << 16) | ||
152 | #define S5P_CISCCTRL_MVRATIO_MASK (0x1ff << 0) | ||
153 | #define S5P_CISCCTRL_MHRATIO_EXT(x) (((x) >> 6) << 16) | ||
154 | #define S5P_CISCCTRL_MVRATIO_EXT(x) (((x) >> 6) << 0) | ||
155 | |||
156 | /* Target area */ | ||
157 | #define S5P_CITAREA 0x5c | ||
158 | #define S5P_CITAREA_MASK 0x0fffffff | ||
159 | |||
160 | /* General status */ | ||
161 | #define S5P_CISTATUS 0x64 | ||
162 | #define S5P_CISTATUS_OVFIY (1 << 31) | ||
163 | #define S5P_CISTATUS_OVFICB (1 << 30) | ||
164 | #define S5P_CISTATUS_OVFICR (1 << 29) | ||
165 | #define S5P_CISTATUS_VSYNC (1 << 28) | ||
166 | #define S5P_CISTATUS_FRAMECNT_MASK (3 << 26) | ||
167 | #define S5P_CISTATUS_FRAMECNT_SHIFT 26 | ||
168 | #define S5P_CISTATUS_WINOFF_EN (1 << 25) | ||
169 | #define S5P_CISTATUS_IMGCPT_EN (1 << 22) | ||
170 | #define S5P_CISTATUS_IMGCPT_SCEN (1 << 21) | ||
171 | #define S5P_CISTATUS_VSYNC_A (1 << 20) | ||
172 | #define S5P_CISTATUS_VSYNC_B (1 << 19) | ||
173 | #define S5P_CISTATUS_OVRLB (1 << 18) | ||
174 | #define S5P_CISTATUS_FRAME_END (1 << 17) | ||
175 | #define S5P_CISTATUS_LASTCAPT_END (1 << 16) | ||
176 | #define S5P_CISTATUS_VVALID_A (1 << 15) | ||
177 | #define S5P_CISTATUS_VVALID_B (1 << 14) | ||
178 | |||
179 | /* Indexes to the last and the currently processed buffer. */ | ||
180 | #define S5P_CISTATUS2 0x68 | ||
181 | |||
182 | /* Image capture control */ | ||
183 | #define S5P_CIIMGCPT 0xc0 | ||
184 | #define S5P_CIIMGCPT_IMGCPTEN (1 << 31) | ||
185 | #define S5P_CIIMGCPT_IMGCPTEN_SC (1 << 30) | ||
186 | #define S5P_CIIMGCPT_CPT_FREN_ENABLE (1 << 25) | ||
187 | #define S5P_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) | ||
188 | |||
189 | /* Frame capture sequence */ | ||
190 | #define S5P_CICPTSEQ 0xc4 | ||
191 | |||
192 | /* Image effect */ | ||
193 | #define S5P_CIIMGEFF 0xd0 | ||
194 | #define S5P_CIIMGEFF_IE_ENABLE (1 << 30) | ||
195 | #define S5P_CIIMGEFF_IE_SC_BEFORE (0 << 29) | ||
196 | #define S5P_CIIMGEFF_IE_SC_AFTER (1 << 29) | ||
197 | #define S5P_CIIMGEFF_FIN_BYPASS (0 << 26) | ||
198 | #define S5P_CIIMGEFF_FIN_ARBITRARY (1 << 26) | ||
199 | #define S5P_CIIMGEFF_FIN_NEGATIVE (2 << 26) | ||
200 | #define S5P_CIIMGEFF_FIN_ARTFREEZE (3 << 26) | ||
201 | #define S5P_CIIMGEFF_FIN_EMBOSSING (4 << 26) | ||
202 | #define S5P_CIIMGEFF_FIN_SILHOUETTE (5 << 26) | ||
203 | #define S5P_CIIMGEFF_FIN_MASK (7 << 26) | ||
204 | #define S5P_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0)) | ||
205 | #define S5P_CIIMGEFF_PAT_CB(x) ((x) << 13) | ||
206 | #define S5P_CIIMGEFF_PAT_CR(x) ((x) << 0) | ||
207 | |||
208 | /* Input DMA Y/Cb/Cr plane start address 0/1 */ | ||
209 | #define S5P_CIIYSA(n) (0xd4 + (n) * 0x70) | ||
210 | #define S5P_CIICBSA(n) (0xd8 + (n) * 0x70) | ||
211 | #define S5P_CIICRSA(n) (0xdc + (n) * 0x70) | ||
212 | |||
213 | /* Real input DMA image size */ | ||
214 | #define S5P_CIREAL_ISIZE 0xf8 | ||
215 | #define S5P_CIREAL_ISIZE_AUTOLOAD_EN (1 << 31) | ||
216 | #define S5P_CIREAL_ISIZE_ADDR_CH_DIS (1 << 30) | ||
217 | #define S5P_CIREAL_ISIZE_HEIGHT(x) ((x) << 16) | ||
218 | #define S5P_CIREAL_ISIZE_WIDTH(x) ((x) << 0) | ||
219 | |||
220 | |||
221 | /* Input DMA control */ | ||
222 | #define S5P_MSCTRL 0xfc | ||
223 | #define S5P_MSCTRL_IN_BURST_COUNT_MASK (0xF << 24) | ||
224 | #define S5P_MSCTRL_2P_IN_ORDER_MASK (3 << 16) | ||
225 | #define S5P_MSCTRL_2P_IN_ORDER_SHIFT 16 | ||
226 | #define S5P_MSCTRL_C_INT_IN_3PLANE (0 << 15) | ||
227 | #define S5P_MSCTRL_C_INT_IN_2PLANE (1 << 15) | ||
228 | #define S5P_MSCTRL_C_INT_IN_MASK (1 << 15) | ||
229 | #define S5P_MSCTRL_FLIP_SHIFT 13 | ||
230 | #define S5P_MSCTRL_FLIP_MASK (3 << 13) | ||
231 | #define S5P_MSCTRL_FLIP_NORMAL (0 << 13) | ||
232 | #define S5P_MSCTRL_FLIP_X_MIRROR (1 << 13) | ||
233 | #define S5P_MSCTRL_FLIP_Y_MIRROR (2 << 13) | ||
234 | #define S5P_MSCTRL_FLIP_180 (3 << 13) | ||
235 | #define S5P_MSCTRL_FIFO_CTRL_FULL (1 << 12) | ||
236 | #define S5P_MSCTRL_ORDER422_SHIFT 4 | ||
237 | #define S5P_MSCTRL_ORDER422_YCBYCR (0 << 4) | ||
238 | #define S5P_MSCTRL_ORDER422_CBYCRY (1 << 4) | ||
239 | #define S5P_MSCTRL_ORDER422_YCRYCB (2 << 4) | ||
240 | #define S5P_MSCTRL_ORDER422_CRYCBY (3 << 4) | ||
241 | #define S5P_MSCTRL_ORDER422_MASK (3 << 4) | ||
242 | #define S5P_MSCTRL_INPUT_EXTCAM (0 << 3) | ||
243 | #define S5P_MSCTRL_INPUT_MEMORY (1 << 3) | ||
244 | #define S5P_MSCTRL_INPUT_MASK (1 << 3) | ||
245 | #define S5P_MSCTRL_INFORMAT_YCBCR420 (0 << 1) | ||
246 | #define S5P_MSCTRL_INFORMAT_YCBCR422 (1 << 1) | ||
247 | #define S5P_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1) | ||
248 | #define S5P_MSCTRL_INFORMAT_RGB (3 << 1) | ||
249 | #define S5P_MSCTRL_INFORMAT_MASK (3 << 1) | ||
250 | #define S5P_MSCTRL_ENVID (1 << 0) | ||
251 | #define S5P_MSCTRL_IN_BURST_COUNT(x) ((x) << 24) | ||
252 | |||
253 | /* Output DMA Y/Cb/Cr offset */ | ||
254 | #define S5P_CIOYOFF 0x168 | ||
255 | #define S5P_CIOCBOFF 0x16c | ||
256 | #define S5P_CIOCROFF 0x170 | ||
257 | |||
258 | /* Input DMA Y/Cb/Cr offset */ | ||
259 | #define S5P_CIIYOFF 0x174 | ||
260 | #define S5P_CIICBOFF 0x178 | ||
261 | #define S5P_CIICROFF 0x17c | ||
262 | |||
263 | #define S5P_CIO_OFFS_VER(x) ((x) << 16) | ||
264 | #define S5P_CIO_OFFS_HOR(x) ((x) << 0) | ||
265 | |||
266 | /* Input DMA original image size */ | ||
267 | #define S5P_ORGISIZE 0x180 | ||
268 | |||
269 | /* Output DMA original image size */ | ||
270 | #define S5P_ORGOSIZE 0x184 | ||
271 | |||
272 | #define S5P_ORIG_SIZE_VER(x) ((x) << 16) | ||
273 | #define S5P_ORIG_SIZE_HOR(x) ((x) << 0) | ||
274 | |||
275 | /* Real output DMA image size (extension register) */ | ||
276 | #define S5P_CIEXTEN 0x188 | ||
277 | #define S5P_CIEXTEN_MHRATIO_EXT(x) (((x) & 0x3f) << 10) | ||
278 | #define S5P_CIEXTEN_MVRATIO_EXT(x) ((x) & 0x3f) | ||
279 | #define S5P_CIEXTEN_MHRATIO_EXT_MASK (0x3f << 10) | ||
280 | #define S5P_CIEXTEN_MVRATIO_EXT_MASK 0x3f | ||
281 | |||
282 | #define S5P_CIDMAPARAM 0x18c | ||
283 | #define S5P_CIDMAPARAM_R_LINEAR (0 << 29) | ||
284 | #define S5P_CIDMAPARAM_R_64X32 (3 << 29) | ||
285 | #define S5P_CIDMAPARAM_W_LINEAR (0 << 13) | ||
286 | #define S5P_CIDMAPARAM_W_64X32 (3 << 13) | ||
287 | #define S5P_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13)) | ||
288 | |||
289 | /* MIPI CSI image format */ | ||
290 | #define S5P_CSIIMGFMT 0x194 | ||
291 | #define S5P_CSIIMGFMT_YCBCR422_8BIT 0x1e | ||
292 | #define S5P_CSIIMGFMT_RAW8 0x2a | ||
293 | #define S5P_CSIIMGFMT_RAW10 0x2b | ||
294 | #define S5P_CSIIMGFMT_RAW12 0x2c | ||
295 | /* User defined formats. x = 0...16. */ | ||
296 | #define S5P_CSIIMGFMT_USER(x) (0x30 + x - 1) | ||
297 | |||
298 | /* Output frame buffer sequence mask */ | ||
299 | #define S5P_CIFCNTSEQ 0x1FC | ||
300 | |||
301 | #endif /* REGS_FIMC_H_ */ | ||