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authorHartmut Hackmann <hartmut.hackmann@t-online.de>2005-07-07 20:57:40 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-07-07 21:23:54 -0400
commitecb60deb9d5bbcbab6c87ee5fde6f8368197fcac (patch)
treee8de9fd8fefbcc89e56821d58e39fe64729f43ee /drivers/media/dvb/frontends/tda1004x.c
parentbbf24cec93b5966bdbd4f25be7a8a2d8716570db (diff)
[PATCH] dvb: frontend: tda1004x update
o added config options for IF frequency and AGC o support DSP boot from on board eeprom o added pll sleep call Signed-off-by: Hartmut Hackmann <hartmut.hackmann@t-online.de> Signed-off-by: Johannes Stezenbach <js@linuxtv.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/media/dvb/frontends/tda1004x.c')
-rw-r--r--drivers/media/dvb/frontends/tda1004x.c193
1 files changed, 97 insertions, 96 deletions
diff --git a/drivers/media/dvb/frontends/tda1004x.c b/drivers/media/dvb/frontends/tda1004x.c
index 0beb370792a..8428c04914e 100644
--- a/drivers/media/dvb/frontends/tda1004x.c
+++ b/drivers/media/dvb/frontends/tda1004x.c
@@ -49,10 +49,8 @@ struct tda1004x_state {
49 /* private demod data */ 49 /* private demod data */
50 u8 initialised; 50 u8 initialised;
51 enum tda1004x_demod demod_type; 51 enum tda1004x_demod demod_type;
52 u8 fw_version;
53}; 52};
54 53
55
56static int debug; 54static int debug;
57#define dprintk(args...) \ 55#define dprintk(args...) \
58 do { \ 56 do { \
@@ -315,20 +313,35 @@ static int tda1004x_do_upload(struct tda1004x_state *state,
315 memcpy(buf + 1, mem + pos, tx_size); 313 memcpy(buf + 1, mem + pos, tx_size);
316 fw_msg.len = tx_size + 1; 314 fw_msg.len = tx_size + 1;
317 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) { 315 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
318 printk("tda1004x: Error during firmware upload\n"); 316 printk(KERN_ERR "tda1004x: Error during firmware upload\n");
319 return -EIO; 317 return -EIO;
320 } 318 }
321 pos += tx_size; 319 pos += tx_size;
322 320
323 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos); 321 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
324 } 322 }
323 // give the DSP a chance to settle 03/10/05 Hac
324 msleep(100);
325 325
326 return 0; 326 return 0;
327} 327}
328 328
329static int tda1004x_check_upload_ok(struct tda1004x_state *state, u8 dspVersion) 329static int tda1004x_check_upload_ok(struct tda1004x_state *state)
330{ 330{
331 u8 data1, data2; 331 u8 data1, data2;
332 unsigned long timeout;
333
334 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
335 timeout = jiffies + 2 * HZ;
336 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
337 if (time_after(jiffies, timeout)) {
338 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
339 break;
340 }
341 msleep(1);
342 }
343 } else
344 msleep(100);
332 345
333 // check upload was OK 346 // check upload was OK
334 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP 347 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
@@ -336,9 +349,11 @@ static int tda1004x_check_upload_ok(struct tda1004x_state *state, u8 dspVersion)
336 349
337 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1); 350 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
338 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2); 351 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
339 if ((data1 != 0x67) || (data2 != dspVersion)) 352 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2a) {
353 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
340 return -EIO; 354 return -EIO;
341 355 }
356 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
342 return 0; 357 return 0;
343} 358}
344 359
@@ -349,14 +364,14 @@ static int tda10045_fwupload(struct dvb_frontend* fe)
349 const struct firmware *fw; 364 const struct firmware *fw;
350 365
351 /* don't re-upload unless necessary */ 366 /* don't re-upload unless necessary */
352 if (tda1004x_check_upload_ok(state, 0x2c) == 0) 367 if (tda1004x_check_upload_ok(state) == 0)
353 return 0; 368 return 0;
354 369
355 /* request the firmware, this will block until someone uploads it */ 370 /* request the firmware, this will block until someone uploads it */
356 printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE); 371 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
357 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); 372 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
358 if (ret) { 373 if (ret) {
359 printk("tda1004x: no firmware upload (timeout or file not found?)\n"); 374 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
360 return ret; 375 return ret;
361 } 376 }
362 377
@@ -372,93 +387,81 @@ static int tda10045_fwupload(struct dvb_frontend* fe)
372 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); 387 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
373 if (ret) 388 if (ret)
374 return ret; 389 return ret;
375 printk("tda1004x: firmware upload complete\n"); 390 printk(KERN_INFO "tda1004x: firmware upload complete\n");
376 391
377 /* wait for DSP to initialise */ 392 /* wait for DSP to initialise */
378 /* DSPREADY doesn't seem to work on the TDA10045H */ 393 /* DSPREADY doesn't seem to work on the TDA10045H */
379 msleep(100); 394 msleep(100);
380 395
381 return tda1004x_check_upload_ok(state, 0x2c); 396 return tda1004x_check_upload_ok(state);
382} 397}
383 398
384static int tda10046_get_fw_version(struct tda1004x_state *state, 399static void tda10046_init_plls(struct dvb_frontend* fe)
385 const struct firmware *fw)
386{ 400{
387 const unsigned char pattern[] = { 0x67, 0x00, 0x50, 0x62, 0x5e, 0x18, 0x67 }; 401 struct tda1004x_state* state = fe->demodulator_priv;
388 unsigned int i;
389
390 /* area guessed from firmware v20, v21 and v25 */
391 for (i = 0x660; i < 0x700; i++) {
392 if (!memcmp(&fw->data[i], pattern, sizeof(pattern))) {
393 state->fw_version = fw->data[i + sizeof(pattern)];
394 printk(KERN_INFO "tda1004x: using firmware v%02x\n",
395 state->fw_version);
396 return 0;
397 }
398 }
399 402
400 return -EINVAL; 403 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
404 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10
405 if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
406 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
407 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
408 } else {
409 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
410 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
411 }
412 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
413 switch (state->config->if_freq) {
414 case TDA10046_FREQ_3617:
415 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
416 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
417 break;
418 case TDA10046_FREQ_3613:
419 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
420 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13);
421 break;
422 }
423 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
401} 424}
402 425
403static int tda10046_fwupload(struct dvb_frontend* fe) 426static int tda10046_fwupload(struct dvb_frontend* fe)
404{ 427{
405 struct tda1004x_state* state = fe->demodulator_priv; 428 struct tda1004x_state* state = fe->demodulator_priv;
406 unsigned long timeout;
407 int ret; 429 int ret;
408 const struct firmware *fw; 430 const struct firmware *fw;
409 431
410 /* reset + wake up chip */ 432 /* reset + wake up chip */
411 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0); 433 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
412 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); 434 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
413 msleep(100); 435 /* let the clocks recover from sleep */
436 msleep(5);
414 437
415 /* don't re-upload unless necessary */ 438 /* don't re-upload unless necessary */
416 if (tda1004x_check_upload_ok(state, state->fw_version) == 0) 439 if (tda1004x_check_upload_ok(state) == 0)
417 return 0; 440 return 0;
418 441
419 /* request the firmware, this will block until someone uploads it */
420 printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10046_DEFAULT_FIRMWARE);
421 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
422 if (ret) {
423 printk("tda1004x: no firmware upload (timeout or file not found?)\n");
424 return ret;
425 }
426
427 if (fw->size < 24478) { /* size of firmware v20, which is the smallest of v20, v21 and v25 */
428 printk("tda1004x: firmware file seems to be too small (%d bytes)\n", fw->size);
429 return -EINVAL;
430 }
431
432 ret = tda10046_get_fw_version(state, fw);
433 if (ret < 0) {
434 printk("tda1004x: unable to find firmware version\n");
435 return ret;
436 }
437
438 /* set parameters */ 442 /* set parameters */
439 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); 443 tda10046_init_plls(fe);
440 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, state->config->n_i2c); 444
441 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); 445 if (state->config->request_firmware != NULL) {
442 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); 446 /* request the firmware, this will block until someone uploads it */
443 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); 447 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
444 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST 448 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
445 449 if (ret) {
446 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN); 450 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
447 if (ret) 451 return ret;
448 return ret;
449 printk("tda1004x: firmware upload complete\n");
450
451 /* wait for DSP to initialise */
452 timeout = jiffies + HZ;
453 while (!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
454 if (time_after(jiffies, timeout)) {
455 printk("tda1004x: DSP failed to initialised.\n");
456 return -EIO;
457 } 452 }
458 msleep(1); 453 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
454 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
455 if (ret)
456 return ret;
457 } else {
458 /* boot from firmware eeprom */
459 /* Hac Note: we might need to do some GPIO Magic here */
460 printk(KERN_INFO "tda1004x: booting from eeprom\n");
461 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
462 msleep(300);
459 } 463 }
460 464 return tda1004x_check_upload_ok(state);
461 return tda1004x_check_upload_ok(state, state->fw_version);
462} 465}
463 466
464static int tda1004x_encode_fec(int fec) 467static int tda1004x_encode_fec(int fec)
@@ -560,12 +563,10 @@ static int tda10046_init(struct dvb_frontend* fe)
560 563
561 if (tda10046_fwupload(fe)) { 564 if (tda10046_fwupload(fe)) {
562 printk("tda1004x: firmware upload failed\n"); 565 printk("tda1004x: firmware upload failed\n");
563 return -EIO; 566 return -EIO;
564 } 567 }
565 568
566 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0); // wake up the chip 569 // Init the tuner PLL
567
568 // Init the PLL
569 if (state->config->pll_init) { 570 if (state->config->pll_init) {
570 tda1004x_enable_tuner_i2c(state); 571 tda1004x_enable_tuner_i2c(state);
571 state->config->pll_init(fe); 572 state->config->pll_init(fe);
@@ -574,32 +575,34 @@ static int tda10046_init(struct dvb_frontend* fe)
574 575
575 // tda setup 576 // tda setup
576 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer 577 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
577 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0x40); 578 tda1004x_write_byteI(state, TDA1004X_AUTO, 7); // select HP stream
578 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream 579 tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer
579 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer 580
580 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10 581 tda10046_init_plls(fe);
581 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, state->config->n_i2c); // PLL P = N = 0 582 switch (state->config->agc_config) {
582 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99 583 case TDA10046_AGC_DEFAULT:
583 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221 584 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
584 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // } 585 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
585 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0); // AGC setup 586 break;
586 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities 587 case TDA10046_AGC_IFO_AUTO_NEG:
588 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
589 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
590 break;
591 }
592 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
587 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } 593 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
588 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values 594 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
589 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } 595 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
590 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } 596 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
591 tda1004x_write_mask(state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
592 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1 597 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
593 tda1004x_write_mask(state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm 598 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
594 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config 599 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
595 tda1004x_write_mask(state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config 600 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
596 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN 601 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
602
597 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup 603 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
598 tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config 604 tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
599 tda1004x_write_mask(state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select 605 tda1004x_write_byteI(state, TDA10046H_GPIO_SELECT, 8); // GPIO select
600 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
601
602 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
603 606
604 state->initialised = 1; 607 state->initialised = 1;
605 return 0; 608 return 0;
@@ -629,9 +632,6 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
629 state->config->pll_set(fe, fe_params); 632 state->config->pll_set(fe, fe_params);
630 tda1004x_disable_tuner_i2c(state); 633 tda1004x_disable_tuner_i2c(state);
631 634
632 if (state->demod_type == TDA1004X_DEMOD_TDA10046)
633 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 4);
634
635 // Hardcoded to use auto as much as possible on the TDA10045 as it 635 // Hardcoded to use auto as much as possible on the TDA10045 as it
636 // is very unreliable if AUTO mode is _not_ used. 636 // is very unreliable if AUTO mode is _not_ used.
637 if (state->demod_type == TDA1004X_DEMOD_TDA10045) { 637 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
@@ -1090,6 +1090,8 @@ static int tda1004x_sleep(struct dvb_frontend* fe)
1090 1090
1091 case TDA1004X_DEMOD_TDA10046: 1091 case TDA1004X_DEMOD_TDA10046:
1092 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); 1092 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1093 if (state->config->pll_sleep != NULL)
1094 state->config->pll_sleep(fe);
1093 break; 1095 break;
1094 } 1096 }
1095 state->initialised = 0; 1097 state->initialised = 0;
@@ -1216,7 +1218,6 @@ struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1216 memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops)); 1218 memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1217 state->initialised = 0; 1219 state->initialised = 0;
1218 state->demod_type = TDA1004X_DEMOD_TDA10046; 1220 state->demod_type = TDA1004X_DEMOD_TDA10046;
1219 state->fw_version = 0x20; /* dummy default value */
1220 1221
1221 /* check if the demod is there */ 1222 /* check if the demod is there */
1222 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) { 1223 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {