diff options
author | Oliver Endriss <o.endriss@gmx.de> | 2011-07-03 17:24:07 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2011-07-27 16:55:45 -0400 |
commit | 4f1f31078745b7af73e1a3a718004807cb1b7846 (patch) | |
tree | e30cef24957f4e8e2abc3412a9e09d8e39db4901 /drivers/media/dvb/ddbridge/ddbridge-regs.h | |
parent | ccad04578fcbe2678084af0986ac010ab84a023d (diff) |
[media] ddbridge: Codingstyle fixes
Codingstyle fixes
Signed-off-by: Oliver Endriss <o.endriss@gmx.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/ddbridge/ddbridge-regs.h')
-rw-r--r-- | drivers/media/dvb/ddbridge/ddbridge-regs.h | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/drivers/media/dvb/ddbridge/ddbridge-regs.h b/drivers/media/dvb/ddbridge/ddbridge-regs.h index 0130073af62..a3ccb318b50 100644 --- a/drivers/media/dvb/ddbridge/ddbridge-regs.h +++ b/drivers/media/dvb/ddbridge/ddbridge-regs.h | |||
@@ -21,26 +21,26 @@ | |||
21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html | 21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html |
22 | */ | 22 | */ |
23 | 23 | ||
24 | // $Id: DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred $ | 24 | /* DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred */ |
25 | 25 | ||
26 | // Register Definitions | 26 | /* Register Definitions */ |
27 | 27 | ||
28 | #define CUR_REGISTERMAP_VERSION 0x10000 | 28 | #define CUR_REGISTERMAP_VERSION 0x10000 |
29 | 29 | ||
30 | #define HARDWARE_VERSION 0x00 | 30 | #define HARDWARE_VERSION 0x00 |
31 | #define REGISTERMAP_VERSION 0x04 | 31 | #define REGISTERMAP_VERSION 0x04 |
32 | 32 | ||
33 | // -------------------------------------------------------------------------- | 33 | /* ------------------------------------------------------------------------- */ |
34 | // SPI Controller | 34 | /* SPI Controller */ |
35 | 35 | ||
36 | #define SPI_CONTROL 0x10 | 36 | #define SPI_CONTROL 0x10 |
37 | #define SPI_DATA 0x14 | 37 | #define SPI_DATA 0x14 |
38 | 38 | ||
39 | // -------------------------------------------------------------------------- | 39 | /* ------------------------------------------------------------------------- */ |
40 | 40 | ||
41 | // Interrupt controller | 41 | /* Interrupt controller */ |
42 | // How many MSI's are available depends on HW (Min 2 max 8) | 42 | /* How many MSI's are available depends on HW (Min 2 max 8) */ |
43 | // How many are usable also depends on Host platform | 43 | /* How many are usable also depends on Host platform */ |
44 | 44 | ||
45 | #define INTERRUPT_BASE (0x40) | 45 | #define INTERRUPT_BASE (0x40) |
46 | 46 | ||
@@ -81,15 +81,15 @@ | |||
81 | #define INTMASK_TSOUTPUT3 (0x00040000) | 81 | #define INTMASK_TSOUTPUT3 (0x00040000) |
82 | #define INTMASK_TSOUTPUT4 (0x00080000) | 82 | #define INTMASK_TSOUTPUT4 (0x00080000) |
83 | 83 | ||
84 | // -------------------------------------------------------------------------- | 84 | /* ------------------------------------------------------------------------- */ |
85 | // I2C Master Controller | 85 | /* I2C Master Controller */ |
86 | 86 | ||
87 | #define I2C_BASE (0x80) // Byte offset | 87 | #define I2C_BASE (0x80) /* Byte offset */ |
88 | 88 | ||
89 | #define I2C_COMMAND (0x00) | 89 | #define I2C_COMMAND (0x00) |
90 | #define I2C_TIMING (0x04) | 90 | #define I2C_TIMING (0x04) |
91 | #define I2C_TASKLENGTH (0x08) // High read, low write | 91 | #define I2C_TASKLENGTH (0x08) /* High read, low write */ |
92 | #define I2C_TASKADDRESS (0x0C) // High read, low write | 92 | #define I2C_TASKADDRESS (0x0C) /* High read, low write */ |
93 | 93 | ||
94 | #define I2C_MONITOR (0x1C) | 94 | #define I2C_MONITOR (0x1C) |
95 | 95 | ||
@@ -100,7 +100,7 @@ | |||
100 | 100 | ||
101 | #define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) | 101 | #define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) |
102 | 102 | ||
103 | #define I2C_TASKMEM_BASE (0x1000) // Byte offset | 103 | #define I2C_TASKMEM_BASE (0x1000) /* Byte offset */ |
104 | #define I2C_TASKMEM_SIZE (0x1000) | 104 | #define I2C_TASKMEM_SIZE (0x1000) |
105 | 105 | ||
106 | #define I2C_SPEED_400 (0x04030404) | 106 | #define I2C_SPEED_400 (0x04030404) |
@@ -111,27 +111,27 @@ | |||
111 | #define I2C_SPEED_50 (0x27262727) | 111 | #define I2C_SPEED_50 (0x27262727) |
112 | 112 | ||
113 | 113 | ||
114 | // -------------------------------------------------------------------------- | 114 | /* ------------------------------------------------------------------------- */ |
115 | // DMA Controller | 115 | /* DMA Controller */ |
116 | 116 | ||
117 | #define DMA_BASE_WRITE (0x100) | 117 | #define DMA_BASE_WRITE (0x100) |
118 | #define DMA_BASE_READ (0x140) | 118 | #define DMA_BASE_READ (0x140) |
119 | 119 | ||
120 | #define DMA_CONTROL (0x00) // 64 | 120 | #define DMA_CONTROL (0x00) /* 64 */ |
121 | #define DMA_ERROR (0x04) // 65 ( only read instance ) | 121 | #define DMA_ERROR (0x04) /* 65 ( only read instance ) */ |
122 | 122 | ||
123 | #define DMA_DIAG_CONTROL (0x1C) // 71 | 123 | #define DMA_DIAG_CONTROL (0x1C) /* 71 */ |
124 | #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) // 72 | 124 | #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) /* 72 */ |
125 | #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) // 73 | 125 | #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) /* 73 */ |
126 | #define DMA_DIAG_TIMECOUNTER_LOW (0x28) // 74 | 126 | #define DMA_DIAG_TIMECOUNTER_LOW (0x28) /* 74 */ |
127 | #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) // 75 | 127 | #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) /* 75 */ |
128 | #define DMA_DIAG_RECHECKCOUNTER (0x30) // 76 ( Split completions on read ) | 128 | #define DMA_DIAG_RECHECKCOUNTER (0x30) /* 76 ( Split completions on read ) */ |
129 | #define DMA_DIAG_WAITTIMEOUTINIT (0x34) // 77 | 129 | #define DMA_DIAG_WAITTIMEOUTINIT (0x34) /* 77 */ |
130 | #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) // 78 | 130 | #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) /* 78 */ |
131 | #define DMA_DIAG_WAITCOUNTER (0x3C) // 79 | 131 | #define DMA_DIAG_WAITCOUNTER (0x3C) /* 79 */ |
132 | 132 | ||
133 | // -------------------------------------------------------------------------- | 133 | /* ------------------------------------------------------------------------- */ |
134 | // DMA Buffer | 134 | /* DMA Buffer */ |
135 | 135 | ||
136 | #define TS_INPUT_BASE (0x200) | 136 | #define TS_INPUT_BASE (0x200) |
137 | #define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00) | 137 | #define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00) |