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authorSteven Toth <stoth@hauppauge.com>2008-05-01 04:48:14 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-05-14 01:56:38 -0400
commit85d220d03b70180b9958b29d43e99c7135f00654 (patch)
tree01e5968adc0fbb2939cad7b1091a4c00b3eb1200 /drivers/media/common/tuners/mxl5005s.h
parent3935c25484bc632b12c447e19c4eacbf5de5f7ae (diff)
V4L/DVB (7867): mxl5005s: Cleanup #4
Cleanup #4 Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/common/tuners/mxl5005s.h')
-rw-r--r--drivers/media/common/tuners/mxl5005s.h291
1 files changed, 33 insertions, 258 deletions
diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h
index df49826816b..1c4d9da8e1f 100644
--- a/drivers/media/common/tuners/mxl5005s.h
+++ b/drivers/media/common/tuners/mxl5005s.h
@@ -26,273 +26,48 @@
26#ifndef __MXL5005S_H 26#ifndef __MXL5005S_H
27#define __MXL5005S_H 27#define __MXL5005S_H
28 28
29/* 29/* IF frequency */
30 * The following context is source code provided by MaxLinear. 30enum IF_FREQ_HZ
31 * MaxLinear source code - Common.h 31{
32 */ 32 IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz
33 33 IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz
34typedef void *HANDLE; /* Pointer to memory location */ 34 IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz
35 35 IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz
36#define TUNER_REGS_NUM 104 36 IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz
37#define INITCTRL_NUM 40 37 IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz
38 38 IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz
39#ifdef _MXL_PRODUCTION
40#define CHCTRL_NUM 39
41#else
42#define CHCTRL_NUM 36
43#endif
44
45#define MXLCTRL_NUM 189
46#define MASTER_CONTROL_ADDR 9
47
48/* Enumeration of AGC Mode */
49typedef enum
50{
51 MXL_DUAL_AGC = 0,
52 MXL_SINGLE_AGC
53} AGC_Mode;
54
55/* Enumeration of Master Control Register State */
56typedef enum
57{
58 MC_LOAD_START = 1,
59 MC_POWER_DOWN,
60 MC_SYNTH_RESET,
61 MC_SEQ_OFF
62} Master_Control_State;
63
64/* Enumeration of MXL5005 Tuner Mode */
65typedef enum
66{
67 MXL_ANALOG_MODE = 0,
68 MXL_DIGITAL_MODE
69} Tuner_Mode;
70
71/* Enumeration of MXL5005 Tuner IF Mode */
72typedef enum
73{
74 MXL_ZERO_IF = 0,
75 MXL_LOW_IF
76} Tuner_IF_Mode;
77
78/* Enumeration of MXL5005 Tuner Clock Out Mode */
79typedef enum
80{
81 MXL_CLOCK_OUT_DISABLE = 0,
82 MXL_CLOCK_OUT_ENABLE
83} Tuner_Clock_Out;
84
85/* Enumeration of MXL5005 Tuner Div Out Mode */
86typedef enum
87{
88 MXL_DIV_OUT_1 = 0,
89 MXL_DIV_OUT_4
90
91} Tuner_Div_Out;
92
93/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */
94typedef enum
95{
96 MXL_CAP_SEL_DISABLE = 0,
97 MXL_CAP_SEL_ENABLE
98
99} Tuner_Cap_Select;
100
101/* Enumeration of MXL5005 Tuner RSSI Mode */
102typedef enum
103{
104 MXL_RSSI_DISABLE = 0,
105 MXL_RSSI_ENABLE
106
107} Tuner_RSSI;
108
109/* Enumeration of MXL5005 Tuner Modulation Type */
110typedef enum
111{
112 MXL_DEFAULT_MODULATION = 0,
113 MXL_DVBT,
114 MXL_ATSC,
115 MXL_QAM,
116 MXL_ANALOG_CABLE,
117 MXL_ANALOG_OTA
118} Tuner_Modu_Type;
119
120/* Enumeration of MXL5005 Tuner Tracking Filter Type */
121typedef enum
122{
123 MXL_TF_DEFAULT = 0,
124 MXL_TF_OFF,
125 MXL_TF_C,
126 MXL_TF_C_H,
127 MXL_TF_D,
128 MXL_TF_D_L,
129 MXL_TF_E,
130 MXL_TF_F,
131 MXL_TF_E_2,
132 MXL_TF_E_NA,
133 MXL_TF_G
134} Tuner_TF_Type;
135
136/* MXL5005 Tuner Register Struct */
137typedef struct _TunerReg_struct
138{
139 u16 Reg_Num; /* Tuner Register Address */
140 u16 Reg_Val; /* Current sofware programmed value waiting to be writen */
141} TunerReg_struct;
142
143typedef enum
144{
145 /* Initialization Control Names */
146 DN_IQTN_AMP_CUT = 1, /* 1 */
147 BB_MODE, /* 2 */
148 BB_BUF, /* 3 */
149 BB_BUF_OA, /* 4 */
150 BB_ALPF_BANDSELECT, /* 5 */
151 BB_IQSWAP, /* 6 */
152 BB_DLPF_BANDSEL, /* 7 */
153 RFSYN_CHP_GAIN, /* 8 */
154 RFSYN_EN_CHP_HIGAIN, /* 9 */
155 AGC_IF, /* 10 */
156 AGC_RF, /* 11 */
157 IF_DIVVAL, /* 12 */
158 IF_VCO_BIAS, /* 13 */
159 CHCAL_INT_MOD_IF, /* 14 */
160 CHCAL_FRAC_MOD_IF, /* 15 */
161 DRV_RES_SEL, /* 16 */
162 I_DRIVER, /* 17 */
163 EN_AAF, /* 18 */
164 EN_3P, /* 19 */
165 EN_AUX_3P, /* 20 */
166 SEL_AAF_BAND, /* 21 */
167 SEQ_ENCLK16_CLK_OUT, /* 22 */
168 SEQ_SEL4_16B, /* 23 */
169 XTAL_CAPSELECT, /* 24 */
170 IF_SEL_DBL, /* 25 */
171 RFSYN_R_DIV, /* 26 */
172 SEQ_EXTSYNTHCALIF, /* 27 */
173 SEQ_EXTDCCAL, /* 28 */
174 AGC_EN_RSSI, /* 29 */
175 RFA_ENCLKRFAGC, /* 30 */
176 RFA_RSSI_REFH, /* 31 */
177 RFA_RSSI_REF, /* 32 */
178 RFA_RSSI_REFL, /* 33 */
179 RFA_FLR, /* 34 */
180 RFA_CEIL, /* 35 */
181 SEQ_EXTIQFSMPULSE, /* 36 */
182 OVERRIDE_1, /* 37 */
183 BB_INITSTATE_DLPF_TUNE, /* 38 */
184 TG_R_DIV, /* 39 */
185 EN_CHP_LIN_B, /* 40 */
186
187 /* Channel Change Control Names */
188 DN_POLY = 51, /* 51 */
189 DN_RFGAIN, /* 52 */
190 DN_CAP_RFLPF, /* 53 */
191 DN_EN_VHFUHFBAR, /* 54 */
192 DN_GAIN_ADJUST, /* 55 */
193 DN_IQTNBUF_AMP, /* 56 */
194 DN_IQTNGNBFBIAS_BST, /* 57 */
195 RFSYN_EN_OUTMUX, /* 58 */
196 RFSYN_SEL_VCO_OUT, /* 59 */
197 RFSYN_SEL_VCO_HI, /* 60 */
198 RFSYN_SEL_DIVM, /* 61 */
199 RFSYN_RF_DIV_BIAS, /* 62 */
200 DN_SEL_FREQ, /* 63 */
201 RFSYN_VCO_BIAS, /* 64 */
202 CHCAL_INT_MOD_RF, /* 65 */
203 CHCAL_FRAC_MOD_RF, /* 66 */
204 RFSYN_LPF_R, /* 67 */
205 CHCAL_EN_INT_RF, /* 68 */
206 TG_LO_DIVVAL, /* 69 */
207 TG_LO_SELVAL, /* 70 */
208 TG_DIV_VAL, /* 71 */
209 TG_VCO_BIAS, /* 72 */
210 SEQ_EXTPOWERUP, /* 73 */
211 OVERRIDE_2, /* 74 */
212 OVERRIDE_3, /* 75 */
213 OVERRIDE_4, /* 76 */
214 SEQ_FSM_PULSE, /* 77 */
215 GPIO_4B, /* 78 */
216 GPIO_3B, /* 79 */
217 GPIO_4, /* 80 */
218 GPIO_3, /* 81 */
219 GPIO_1B, /* 82 */
220 DAC_A_ENABLE, /* 83 */
221 DAC_B_ENABLE, /* 84 */
222 DAC_DIN_A, /* 85 */
223 DAC_DIN_B, /* 86 */
224#ifdef _MXL_PRODUCTION
225 RFSYN_EN_DIV, /* 87 */
226 RFSYN_DIVM, /* 88 */
227 DN_BYPASS_AGC_I2C /* 89 */
228#endif
229} MXL5005_ControlName;
230
231/* End of common.h */
232
233/*
234 * The following context is source code provided by MaxLinear.
235 * MaxLinear source code - Common_MXL.h (?)
236 */
237
238/* Constants */
239#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
240#define MXL5005S_LATCH_BYTE 0xfe
241
242/* Register address, MSB, and LSB */
243#define MXL5005S_BB_IQSWAP_ADDR 59
244#define MXL5005S_BB_IQSWAP_MSB 0
245#define MXL5005S_BB_IQSWAP_LSB 0
246
247#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
248#define MXL5005S_BB_DLPF_BANDSEL_MSB 4
249#define MXL5005S_BB_DLPF_BANDSEL_LSB 3
250
251/* Standard modes */
252enum
253{
254 MXL5005S_STANDARD_DVBT,
255 MXL5005S_STANDARD_ATSC,
256}; 39};
257#define MXL5005S_STANDARD_MODE_NUM 2
258 40
259/* Bandwidth modes */ 41/* Crystal frequency */
260enum 42enum CRYSTAL_FREQ_HZ
261{ 43{
262 MXL5005S_BANDWIDTH_6MHZ = 6000000, 44 CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz
263 MXL5005S_BANDWIDTH_7MHZ = 7000000, 45 CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz
264 MXL5005S_BANDWIDTH_8MHZ = 8000000, 46 CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz
47 CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz
265}; 48};
266#define MXL5005S_BANDWIDTH_MODE_NUM 3
267 49
268/* Top modes */ 50struct mxl5005s_config
269enum
270{ 51{
271 MXL5005S_TOP_5P5 = 55, 52 u8 i2c_address;
272 MXL5005S_TOP_7P2 = 72,
273 MXL5005S_TOP_9P2 = 92,
274 MXL5005S_TOP_11P0 = 110,
275 MXL5005S_TOP_12P9 = 129,
276 MXL5005S_TOP_14P7 = 147,
277 MXL5005S_TOP_16P8 = 168,
278 MXL5005S_TOP_19P4 = 194,
279 MXL5005S_TOP_21P2 = 212,
280 MXL5005S_TOP_23P2 = 232,
281 MXL5005S_TOP_25P2 = 252,
282 MXL5005S_TOP_27P1 = 271,
283 MXL5005S_TOP_29P2 = 292,
284 MXL5005S_TOP_31P7 = 317,
285 MXL5005S_TOP_34P9 = 349,
286};
287 53
288/* IF output load */ 54 /* Stuff I don't know what to do with */
289enum 55 u8 AgcMasterByte;
290{
291 MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200,
292 MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300,
293}; 56};
294 57
295/* End of common_mxl.h (?) */ 58#if defined(CONFIG_DVB_TUNER_MXL5005S) || (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE))
59extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
60 struct i2c_adapter *i2c,
61 struct mxl5005s_config *config);
62#else
63static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
64 struct i2c_adapter *i2c,
65 struct mxl5005s_config *config);
66{
67 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
68 return NULL;
69}
70#endif /* CONFIG_DVB_TUNER_MXL5005S */
296 71
297#endif /* __MXL5005S_H */ 72#endif /* __MXL5005S_H */
298 73
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