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authorHiroshi DOYU <hdoyu@nvidia.com>2012-05-10 03:45:32 -0400
committerJoerg Roedel <joerg.roedel@amd.com>2012-05-11 05:42:05 -0400
commit774dfc9bb7f2ab1950a790a8f13eca3d5c580033 (patch)
treec93680af050fcef7f5aff981ecfd3cf60abaf570 /drivers/iommu/tegra-gart.c
parent7cffae421e3cd29410ef4d75f2244655fdde3b60 (diff)
iommu/tegra: gart: Fix register offset correctly
DT passes the exact GART register ranges without any overlapping with MC register ranges. GART register offset needs to be adjusted by one passed by DT correctly. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'drivers/iommu/tegra-gart.c')
-rw-r--r--drivers/iommu/tegra-gart.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c
index 40533bba625..0c0a3779221 100644
--- a/drivers/iommu/tegra-gart.c
+++ b/drivers/iommu/tegra-gart.c
@@ -36,9 +36,10 @@
36/* bitmap of the page sizes currently supported */ 36/* bitmap of the page sizes currently supported */
37#define GART_IOMMU_PGSIZES (SZ_4K) 37#define GART_IOMMU_PGSIZES (SZ_4K)
38 38
39#define GART_CONFIG 0x24 39#define GART_REG_BASE 0x24
40#define GART_ENTRY_ADDR 0x28 40#define GART_CONFIG (0x24 - GART_REG_BASE)
41#define GART_ENTRY_DATA 0x2c 41#define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
42#define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
42#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31) 43#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31)
43 44
44#define GART_PAGE_SHIFT 12 45#define GART_PAGE_SHIFT 12