iommu/vt-d: Convert IR set_affinity function to remap_ops

The function to set interrupt affinity with interrupt
remapping enabled is Intel specific too. So move it to the
irq_remap_ops too.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

1 files changed, 54 insertions, 0 deletions

diff --git a/drivers/iommu/intel_intr_remapping.c b/drivers/iommu/intel_intr_remapping.c
index f495eba4b6a..25372c1f3c8 100644
--- a/drivers/iommu/intel_intr_remapping.c
+++ b/drivers/iommu/intel_intr_remapping.c
@@ -901,6 +901,59 @@ static int intel_setup_ioapic_entry(int irq,
         return 0;
 }
 
+/*
+ * Migrate the IO-APIC irq in the presence of intr-remapping.
+ *
+ * For both level and edge triggered, irq migration is a simple atomic
+ * update(of vector and cpu destination) of IRTE and flush the hardware cache.
+ *
+ * For level triggered, we eliminate the io-apic RTE modification (with the
+ * updated vector information), by using a virtual vector (io-apic pin number).
+ * Real vector that is used for interrupting cpu will be coming from
+ * the interrupt-remapping table entry.
+ *
+ * As the migration is a simple atomic update of IRTE, the same mechanism
+ * is used to migrate MSI irq's in the presence of interrupt-remapping.
+ */
+static int
+intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
+                          bool force)
+{
+        struct irq_cfg *cfg = data->chip_data;
+        unsigned int dest, irq = data->irq;
+        struct irte irte;
+
+        if (!cpumask_intersects(mask, cpu_online_mask))
+                return -EINVAL;
+
+        if (get_irte(irq, &irte))
+                return -EBUSY;
+
+        if (assign_irq_vector(irq, cfg, mask))
+                return -EBUSY;
+
+        dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
+
+        irte.vector = cfg->vector;
+        irte.dest_id = IRTE_DEST(dest);
+
+        /*
+         * Atomically updates the IRTE with the new destination, vector
+         * and flushes the interrupt entry cache.
+         */
+        modify_irte(irq, &irte);
+
+        /*
+         * After this point, all the interrupts will start arriving
+         * at the new destination. So, time to cleanup the previous
+         * vector allocation.
+         */
+        if (cfg->move_in_progress)
+                send_cleanup_vector(cfg);
+
+        cpumask_copy(data->affinity, mask);
+        return 0;
+}
 
 struct irq_remap_ops intel_irq_remap_ops = {
         .supported              = intel_intr_remapping_supported,
@@ -910,4 +963,5 @@ struct irq_remap_ops intel_irq_remap_ops = {
         .hardware_reenable      = reenable_intr_remapping,
         .enable_faulting        = enable_drhd_fault_handling,
         .setup_ioapic_entry     = intel_setup_ioapic_entry,
+        .set_affinity           = intel_ioapic_set_affinity,
 };