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authorRalph Campbell <ralph.campbell@qlogic.com>2010-05-06 20:03:19 -0400
committerRoland Dreier <rolandd@cisco.com>2010-05-24 01:14:25 -0400
commitf6d60848baf9f4015c76c665791875ed623cd5b7 (patch)
tree7079f308086c79f535550be9bfa3c86accdf5557 /drivers/infiniband/hw/ipath
parentf931551bafe1f10ded7f5282e2aa162c267a2e5d (diff)
IB/ipath: Remove support for QLogic PCIe QLE devices
The ib_qib driver is taking over support for QLogic PCIe QLE devices, so remove support for them from ib_ipath. The ib_ipath driver now supports only the obsolete QLogic Hyper-Transport IB host channel adapter (model QHT7140). Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/ipath')
-rw-r--r--drivers/infiniband/hw/ipath/Kconfig8
-rw-r--r--drivers/infiniband/hw/ipath/Makefile6
-rw-r--r--drivers/infiniband/hw/ipath/ipath_7220.h57
-rw-r--r--drivers/infiniband/hw/ipath/ipath_driver.c28
-rw-r--r--drivers/infiniband/hw/ipath/ipath_iba6120.c1862
-rw-r--r--drivers/infiniband/hw/ipath/ipath_iba7220.c2631
-rw-r--r--drivers/infiniband/hw/ipath/ipath_kernel.h2
-rw-r--r--drivers/infiniband/hw/ipath/ipath_sd7220.c1462
-rw-r--r--drivers/infiniband/hw/ipath/ipath_sd7220_img.c1082
9 files changed, 7 insertions, 7131 deletions
diff --git a/drivers/infiniband/hw/ipath/Kconfig b/drivers/infiniband/hw/ipath/Kconfig
index 3c7968f25ec..1d9bb115cbf 100644
--- a/drivers/infiniband/hw/ipath/Kconfig
+++ b/drivers/infiniband/hw/ipath/Kconfig
@@ -1,9 +1,11 @@
1config INFINIBAND_IPATH 1config INFINIBAND_IPATH
2 tristate "QLogic InfiniPath Driver" 2 tristate "QLogic HTX HCA support"
3 depends on 64BIT && NET 3 depends on 64BIT && NET && HT_IRQ
4 ---help--- 4 ---help---
5 This is a driver for QLogic InfiniPath host channel adapters, 5 This is a driver for the obsolete QLogic Hyper-Transport
6 IB host channel adapter (model QHT7140),
6 including InfiniBand verbs support. This driver allows these 7 including InfiniBand verbs support. This driver allows these
7 devices to be used with both kernel upper level protocols such 8 devices to be used with both kernel upper level protocols such
8 as IP-over-InfiniBand as well as with userspace applications 9 as IP-over-InfiniBand as well as with userspace applications
9 (in conjunction with InfiniBand userspace access). 10 (in conjunction with InfiniBand userspace access).
11 For QLogic PCIe QLE based cards, use the QIB driver instead.
diff --git a/drivers/infiniband/hw/ipath/Makefile b/drivers/infiniband/hw/ipath/Makefile
index bf945006198..fa3df82681d 100644
--- a/drivers/infiniband/hw/ipath/Makefile
+++ b/drivers/infiniband/hw/ipath/Makefile
@@ -29,13 +29,9 @@ ib_ipath-y := \
29 ipath_user_pages.o \ 29 ipath_user_pages.o \
30 ipath_user_sdma.o \ 30 ipath_user_sdma.o \
31 ipath_verbs_mcast.o \ 31 ipath_verbs_mcast.o \
32 ipath_verbs.o \ 32 ipath_verbs.o
33 ipath_iba7220.o \
34 ipath_sd7220.o \
35 ipath_sd7220_img.o
36 33
37ib_ipath-$(CONFIG_HT_IRQ) += ipath_iba6110.o 34ib_ipath-$(CONFIG_HT_IRQ) += ipath_iba6110.o
38ib_ipath-$(CONFIG_PCI_MSI) += ipath_iba6120.o
39 35
40ib_ipath-$(CONFIG_X86_64) += ipath_wc_x86_64.o 36ib_ipath-$(CONFIG_X86_64) += ipath_wc_x86_64.o
41ib_ipath-$(CONFIG_PPC64) += ipath_wc_ppc64.o 37ib_ipath-$(CONFIG_PPC64) += ipath_wc_ppc64.o
diff --git a/drivers/infiniband/hw/ipath/ipath_7220.h b/drivers/infiniband/hw/ipath/ipath_7220.h
deleted file mode 100644
index 74fa5cc5131..00000000000
--- a/drivers/infiniband/hw/ipath/ipath_7220.h
+++ /dev/null
@@ -1,57 +0,0 @@
1#ifndef _IPATH_7220_H
2#define _IPATH_7220_H
3/*
4 * Copyright (c) 2007 QLogic Corporation. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35/*
36 * This header file provides the declarations and common definitions
37 * for (mostly) manipulation of the SerDes blocks within the IBA7220.
38 * the functions declared should only be called from within other
39 * 7220-related files such as ipath_iba7220.c or ipath_sd7220.c.
40 */
41int ipath_sd7220_presets(struct ipath_devdata *dd);
42int ipath_sd7220_init(struct ipath_devdata *dd, int was_reset);
43int ipath_sd7220_prog_ld(struct ipath_devdata *dd, int sdnum, u8 *img,
44 int len, int offset);
45int ipath_sd7220_prog_vfy(struct ipath_devdata *dd, int sdnum, const u8 *img,
46 int len, int offset);
47/*
48 * Below used for sdnum parameter, selecting one of the two sections
49 * used for PCIe, or the single SerDes used for IB, which is the
50 * only one currently used
51 */
52#define IB_7220_SERDES 2
53
54int ipath_sd7220_ib_load(struct ipath_devdata *dd);
55int ipath_sd7220_ib_vfy(struct ipath_devdata *dd);
56
57#endif /* _IPATH_7220_H */
diff --git a/drivers/infiniband/hw/ipath/ipath_driver.c b/drivers/infiniband/hw/ipath/ipath_driver.c
index 6302626d17f..21337468c65 100644
--- a/drivers/infiniband/hw/ipath/ipath_driver.c
+++ b/drivers/infiniband/hw/ipath/ipath_driver.c
@@ -132,18 +132,13 @@ static int __devinit ipath_init_one(struct pci_dev *,
132 132
133/* Only needed for registration, nothing else needs this info */ 133/* Only needed for registration, nothing else needs this info */
134#define PCI_VENDOR_ID_PATHSCALE 0x1fc1 134#define PCI_VENDOR_ID_PATHSCALE 0x1fc1
135#define PCI_VENDOR_ID_QLOGIC 0x1077
136#define PCI_DEVICE_ID_INFINIPATH_HT 0xd 135#define PCI_DEVICE_ID_INFINIPATH_HT 0xd
137#define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
138#define PCI_DEVICE_ID_INFINIPATH_7220 0x7220
139 136
140/* Number of seconds before our card status check... */ 137/* Number of seconds before our card status check... */
141#define STATUS_TIMEOUT 60 138#define STATUS_TIMEOUT 60
142 139
143static const struct pci_device_id ipath_pci_tbl[] = { 140static const struct pci_device_id ipath_pci_tbl[] = {
144 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) }, 141 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
145 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
146 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_INFINIPATH_7220) },
147 { 0, } 142 { 0, }
148}; 143};
149 144
@@ -521,30 +516,9 @@ static int __devinit ipath_init_one(struct pci_dev *pdev,
521 /* setup the chip-specific functions, as early as possible. */ 516 /* setup the chip-specific functions, as early as possible. */
522 switch (ent->device) { 517 switch (ent->device) {
523 case PCI_DEVICE_ID_INFINIPATH_HT: 518 case PCI_DEVICE_ID_INFINIPATH_HT:
524#ifdef CONFIG_HT_IRQ
525 ipath_init_iba6110_funcs(dd); 519 ipath_init_iba6110_funcs(dd);
526 break; 520 break;
527#else 521
528 ipath_dev_err(dd, "QLogic HT device 0x%x cannot work if "
529 "CONFIG_HT_IRQ is not enabled\n", ent->device);
530 return -ENODEV;
531#endif
532 case PCI_DEVICE_ID_INFINIPATH_PE800:
533#ifdef CONFIG_PCI_MSI
534 ipath_init_iba6120_funcs(dd);
535 break;
536#else
537 ipath_dev_err(dd, "QLogic PCIE device 0x%x cannot work if "
538 "CONFIG_PCI_MSI is not enabled\n", ent->device);
539 return -ENODEV;
540#endif
541 case PCI_DEVICE_ID_INFINIPATH_7220:
542#ifndef CONFIG_PCI_MSI
543 ipath_dbg("CONFIG_PCI_MSI is not enabled, "
544 "using INTx for unit %u\n", dd->ipath_unit);
545#endif
546 ipath_init_iba7220_funcs(dd);
547 break;
548 default: 522 default:
549 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, " 523 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
550 "failing\n", ent->device); 524 "failing\n", ent->device);
diff --git a/drivers/infiniband/hw/ipath/ipath_iba6120.c b/drivers/infiniband/hw/ipath/ipath_iba6120.c
deleted file mode 100644
index 4b4a30b0dab..00000000000
--- a/drivers/infiniband/hw/ipath/ipath_iba6120.c
+++ /dev/null
@@ -1,1862 +0,0 @@
1/*
2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33/*
34 * This file contains all of the code that is specific to the
35 * InfiniPath PCIe chip.
36 */
37
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <rdma/ib_verbs.h>
42
43#include "ipath_kernel.h"
44#include "ipath_registers.h"
45
46static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
47
48/*
49 * This file contains all the chip-specific register information and
50 * access functions for the QLogic InfiniPath PCI-Express chip.
51 *
52 * This lists the InfiniPath registers, in the actual chip layout.
53 * This structure should never be directly accessed.
54 */
55struct _infinipath_do_not_use_kernel_regs {
56 unsigned long long Revision;
57 unsigned long long Control;
58 unsigned long long PageAlign;
59 unsigned long long PortCnt;
60 unsigned long long DebugPortSelect;
61 unsigned long long Reserved0;
62 unsigned long long SendRegBase;
63 unsigned long long UserRegBase;
64 unsigned long long CounterRegBase;
65 unsigned long long Scratch;
66 unsigned long long Reserved1;
67 unsigned long long Reserved2;
68 unsigned long long IntBlocked;
69 unsigned long long IntMask;
70 unsigned long long IntStatus;
71 unsigned long long IntClear;
72 unsigned long long ErrorMask;
73 unsigned long long ErrorStatus;
74 unsigned long long ErrorClear;
75 unsigned long long HwErrMask;
76 unsigned long long HwErrStatus;
77 unsigned long long HwErrClear;
78 unsigned long long HwDiagCtrl;
79 unsigned long long MDIO;
80 unsigned long long IBCStatus;
81 unsigned long long IBCCtrl;
82 unsigned long long ExtStatus;
83 unsigned long long ExtCtrl;
84 unsigned long long GPIOOut;
85 unsigned long long GPIOMask;
86 unsigned long long GPIOStatus;
87 unsigned long long GPIOClear;
88 unsigned long long RcvCtrl;
89 unsigned long long RcvBTHQP;
90 unsigned long long RcvHdrSize;
91 unsigned long long RcvHdrCnt;
92 unsigned long long RcvHdrEntSize;
93 unsigned long long RcvTIDBase;
94 unsigned long long RcvTIDCnt;
95 unsigned long long RcvEgrBase;
96 unsigned long long RcvEgrCnt;
97 unsigned long long RcvBufBase;
98 unsigned long long RcvBufSize;
99 unsigned long long RxIntMemBase;
100 unsigned long long RxIntMemSize;
101 unsigned long long RcvPartitionKey;
102 unsigned long long Reserved3;
103 unsigned long long RcvPktLEDCnt;
104 unsigned long long Reserved4[8];
105 unsigned long long SendCtrl;
106 unsigned long long SendPIOBufBase;
107 unsigned long long SendPIOSize;
108 unsigned long long SendPIOBufCnt;
109 unsigned long long SendPIOAvailAddr;
110 unsigned long long TxIntMemBase;
111 unsigned long long TxIntMemSize;
112 unsigned long long Reserved5;
113 unsigned long long PCIeRBufTestReg0;
114 unsigned long long PCIeRBufTestReg1;
115 unsigned long long Reserved51[6];
116 unsigned long long SendBufferError;
117 unsigned long long SendBufferErrorCONT1;
118 unsigned long long Reserved6SBE[6];
119 unsigned long long RcvHdrAddr0;
120 unsigned long long RcvHdrAddr1;
121 unsigned long long RcvHdrAddr2;
122 unsigned long long RcvHdrAddr3;
123 unsigned long long RcvHdrAddr4;
124 unsigned long long Reserved7RHA[11];
125 unsigned long long RcvHdrTailAddr0;
126 unsigned long long RcvHdrTailAddr1;
127 unsigned long long RcvHdrTailAddr2;
128 unsigned long long RcvHdrTailAddr3;
129 unsigned long long RcvHdrTailAddr4;
130 unsigned long long Reserved8RHTA[11];
131 unsigned long long Reserved9SW[8];
132 unsigned long long SerdesConfig0;
133 unsigned long long SerdesConfig1;
134 unsigned long long SerdesStatus;
135 unsigned long long XGXSConfig;
136 unsigned long long IBPLLCfg;
137 unsigned long long Reserved10SW2[3];
138 unsigned long long PCIEQ0SerdesConfig0;
139 unsigned long long PCIEQ0SerdesConfig1;
140 unsigned long long PCIEQ0SerdesStatus;
141 unsigned long long Reserved11;
142 unsigned long long PCIEQ1SerdesConfig0;
143 unsigned long long PCIEQ1SerdesConfig1;
144 unsigned long long PCIEQ1SerdesStatus;
145 unsigned long long Reserved12;
146};
147
148struct _infinipath_do_not_use_counters {
149 __u64 LBIntCnt;
150 __u64 LBFlowStallCnt;
151 __u64 Reserved1;
152 __u64 TxUnsupVLErrCnt;
153 __u64 TxDataPktCnt;
154 __u64 TxFlowPktCnt;
155 __u64 TxDwordCnt;
156 __u64 TxLenErrCnt;
157 __u64 TxMaxMinLenErrCnt;
158 __u64 TxUnderrunCnt;
159 __u64 TxFlowStallCnt;
160 __u64 TxDroppedPktCnt;
161 __u64 RxDroppedPktCnt;
162 __u64 RxDataPktCnt;
163 __u64 RxFlowPktCnt;
164 __u64 RxDwordCnt;
165 __u64 RxLenErrCnt;
166 __u64 RxMaxMinLenErrCnt;
167 __u64 RxICRCErrCnt;
168 __u64 RxVCRCErrCnt;
169 __u64 RxFlowCtrlErrCnt;
170 __u64 RxBadFormatCnt;
171 __u64 RxLinkProblemCnt;
172 __u64 RxEBPCnt;
173 __u64 RxLPCRCErrCnt;
174 __u64 RxBufOvflCnt;
175 __u64 RxTIDFullErrCnt;
176 __u64 RxTIDValidErrCnt;
177 __u64 RxPKeyMismatchCnt;
178 __u64 RxP0HdrEgrOvflCnt;
179 __u64 RxP1HdrEgrOvflCnt;
180 __u64 RxP2HdrEgrOvflCnt;
181 __u64 RxP3HdrEgrOvflCnt;
182 __u64 RxP4HdrEgrOvflCnt;
183 __u64 RxP5HdrEgrOvflCnt;
184 __u64 RxP6HdrEgrOvflCnt;
185 __u64 RxP7HdrEgrOvflCnt;
186 __u64 RxP8HdrEgrOvflCnt;
187 __u64 Reserved6;
188 __u64 Reserved7;
189 __u64 IBStatusChangeCnt;
190 __u64 IBLinkErrRecoveryCnt;
191 __u64 IBLinkDownedCnt;
192 __u64 IBSymbolErrCnt;
193};
194
195#define IPATH_KREG_OFFSET(field) (offsetof( \
196 struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
197#define IPATH_CREG_OFFSET(field) (offsetof( \
198 struct _infinipath_do_not_use_counters, field) / sizeof(u64))
199
200static const struct ipath_kregs ipath_pe_kregs = {
201 .kr_control = IPATH_KREG_OFFSET(Control),
202 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
203 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
204 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
205 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
206 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
207 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
208 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
209 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
210 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
211 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
212 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
213 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
214 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
215 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
216 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
217 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
218 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
219 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
220 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
221 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
222 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
223 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
224 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
225 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
226 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
227 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
228 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
229 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
230 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
231 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
232 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
233 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
234 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
235 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
236 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
237 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
238 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
239 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
240 .kr_revision = IPATH_KREG_OFFSET(Revision),
241 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
242 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
243 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
244 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
245 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
246 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
247 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
248 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
249 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
250 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
251 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
252 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
253 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
254 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
255 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
256 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
257
258 /*
259 * These should not be used directly via ipath_write_kreg64(),
260 * use them with ipath_write_kreg64_port(),
261 */
262 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
263 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
264
265 /* The rcvpktled register controls one of the debug port signals, so
266 * a packet activity LED can be connected to it. */
267 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
268 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
269 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
270 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
271 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
272 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
273 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
274 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
275 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
276};
277
278static const struct ipath_cregs ipath_pe_cregs = {
279 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
280 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
281 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
282 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
283 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
284 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
285 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
286 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
287 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
288 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
289 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
290 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
291 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
292 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
293 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
294 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
295 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
296 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
297 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
298 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
299 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
300 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
301 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
302 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
303 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
304 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
305 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
306 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
307 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
308 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
309 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
310 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
311 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
312};
313
314/* kr_control bits */
315#define INFINIPATH_C_RESET 1U
316
317/* kr_intstatus, kr_intclear, kr_intmask bits */
318#define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
319#define INFINIPATH_I_RCVURG_SHIFT 0
320#define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
321#define INFINIPATH_I_RCVAVAIL_SHIFT 12
322
323/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
324#define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
325#define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
326#define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
327#define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
328#define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
329#define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
330#define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
331#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
332#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
333#define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
334#define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
335#define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
336
337#define IBA6120_IBCS_LINKTRAININGSTATE_MASK 0xf
338#define IBA6120_IBCS_LINKSTATE_SHIFT 4
339
340/* kr_extstatus bits */
341#define INFINIPATH_EXTS_FREQSEL 0x2
342#define INFINIPATH_EXTS_SERDESSEL 0x4
343#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
344#define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
345
346/* kr_xgxsconfig bits */
347#define INFINIPATH_XGXS_RESET 0x5ULL
348
349#define _IPATH_GPIO_SDA_NUM 1
350#define _IPATH_GPIO_SCL_NUM 0
351
352#define IPATH_GPIO_SDA (1ULL << \
353 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
354#define IPATH_GPIO_SCL (1ULL << \
355 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
356
357#define INFINIPATH_RT_BUFSIZE_MASK 0xe0000000ULL
358#define INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid) \
359 ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
360#define INFINIPATH_RT_BUFSIZE(tid) (1 << INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid))
361#define INFINIPATH_RT_IS_VALID(tid) \
362 (((tid) & INFINIPATH_RT_BUFSIZE_MASK) && \
363 ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) != INFINIPATH_RT_BUFSIZE_MASK)))
364#define INFINIPATH_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
365#define INFINIPATH_RT_ADDR_SHIFT 10
366
367#define INFINIPATH_R_INTRAVAIL_SHIFT 16
368#define INFINIPATH_R_TAILUPD_SHIFT 31
369
370/* 6120 specific hardware errors... */
371static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
372 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
373 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
374 /*
375 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
376 * parity or memory parity error failures, because most likely we
377 * won't be able to talk to the core of the chip. Nonetheless, we
378 * might see them, if they are in parts of the PCIe core that aren't
379 * essential.
380 */
381 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
382 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
383 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
384 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
385 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
386 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
387 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
388};
389
390#define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
391 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
392 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
393#define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
394 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
395
396static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
397 u32, unsigned long);
398
399/*
400 * On platforms using this chip, and not having ordered WC stores, we
401 * can get TXE parity errors due to speculative reads to the PIO buffers,
402 * and this, due to a chip bug can result in (many) false parity error
403 * reports. So it's a debug print on those, and an info print on systems
404 * where the speculative reads don't occur.
405 */
406static void ipath_pe_txe_recover(struct ipath_devdata *dd)
407{
408 if (ipath_unordered_wc())
409 ipath_dbg("Recovering from TXE PIO parity error\n");
410 else {
411 ++ipath_stats.sps_txeparity;
412 dev_info(&dd->pcidev->dev,
413 "Recovering from TXE PIO parity error\n");
414 }
415}
416
417
418/**
419 * ipath_pe_handle_hwerrors - display hardware errors.
420 * @dd: the infinipath device
421 * @msg: the output buffer
422 * @msgl: the size of the output buffer
423 *
424 * Use same msg buffer as regular errors to avoid excessive stack
425 * use. Most hardware errors are catastrophic, but for right now,
426 * we'll print them and continue. We reuse the same message buffer as
427 * ipath_handle_errors() to avoid excessive stack usage.
428 */
429static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
430 size_t msgl)
431{
432 ipath_err_t hwerrs;
433 u32 bits, ctrl;
434 int isfatal = 0;
435 char bitsmsg[64];
436 int log_idx;
437
438 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
439 if (!hwerrs) {
440 /*
441 * better than printing cofusing messages
442 * This seems to be related to clearing the crc error, or
443 * the pll error during init.
444 */
445 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
446 return;
447 } else if (hwerrs == ~0ULL) {
448 ipath_dev_err(dd, "Read of hardware error status failed "
449 "(all bits set); ignoring\n");
450 return;
451 }
452 ipath_stats.sps_hwerrs++;
453
454 /* Always clear the error status register, except MEMBISTFAIL,
455 * regardless of whether we continue or stop using the chip.
456 * We want that set so we know it failed, even across driver reload.
457 * We'll still ignore it in the hwerrmask. We do this partly for
458 * diagnostics, but also for support */
459 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
460 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
461
462 hwerrs &= dd->ipath_hwerrmask;
463
464 /* We log some errors to EEPROM, check if we have any of those. */
465 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
466 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
467 ipath_inc_eeprom_err(dd, log_idx, 1);
468
469 /*
470 * make sure we get this much out, unless told to be quiet,
471 * or it's occurred within the last 5 seconds
472 */
473 if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
474 RXE_EAGER_PARITY)) ||
475 (ipath_debug & __IPATH_VERBDBG))
476 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
477 "(cleared)\n", (unsigned long long) hwerrs);
478 dd->ipath_lasthwerror |= hwerrs;
479
480 if (hwerrs & ~dd->ipath_hwe_bitsextant)
481 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
482 "%llx set\n", (unsigned long long)
483 (hwerrs & ~dd->ipath_hwe_bitsextant));
484
485 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
486 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
487 /*
488 * parity errors in send memory are recoverable,
489 * just cancel the send (if indicated in * sendbuffererror),
490 * count the occurrence, unfreeze (if no other handled
491 * hardware error bits are set), and continue. They can
492 * occur if a processor speculative read is done to the PIO
493 * buffer while we are sending a packet, for example.
494 */
495 if (hwerrs & TXE_PIO_PARITY) {
496 ipath_pe_txe_recover(dd);
497 hwerrs &= ~TXE_PIO_PARITY;
498 }
499 if (!hwerrs) {
500 static u32 freeze_cnt;
501
502 freeze_cnt++;
503 ipath_dbg("Clearing freezemode on ignored or recovered "
504 "hardware error (%u)\n", freeze_cnt);
505 ipath_clear_freeze(dd);
506 }
507 }
508
509 *msg = '\0';
510
511 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
512 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
513 msgl);
514 /* ignore from now on, so disable until driver reloaded */
515 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
516 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
517 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
518 dd->ipath_hwerrmask);
519 }
520
521 ipath_format_hwerrors(hwerrs,
522 ipath_6120_hwerror_msgs,
523 sizeof(ipath_6120_hwerror_msgs)/
524 sizeof(ipath_6120_hwerror_msgs[0]),
525 msg, msgl);
526
527 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
528 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
529 bits = (u32) ((hwerrs >>
530 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
531 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
532 snprintf(bitsmsg, sizeof bitsmsg,
533 "[PCIe Mem Parity Errs %x] ", bits);
534 strlcat(msg, bitsmsg, msgl);
535 }
536
537#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
538 INFINIPATH_HWE_COREPLL_RFSLIP )
539
540 if (hwerrs & _IPATH_PLL_FAIL) {
541 snprintf(bitsmsg, sizeof bitsmsg,
542 "[PLL failed (%llx), InfiniPath hardware unusable]",
543 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
544 strlcat(msg, bitsmsg, msgl);
545 /* ignore from now on, so disable until driver reloaded */
546 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
547 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
548 dd->ipath_hwerrmask);
549 }
550
551 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
552 /*
553 * If it occurs, it is left masked since the external
554 * interface is unused
555 */
556 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
557 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
558 dd->ipath_hwerrmask);
559 }
560
561 if (hwerrs) {
562 /*
563 * if any set that we aren't ignoring; only
564 * make the complaint once, in case it's stuck
565 * or recurring, and we get here multiple
566 * times.
567 */
568 ipath_dev_err(dd, "%s hardware error\n", msg);
569 if (dd->ipath_flags & IPATH_INITTED) {
570 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
571 ipath_setup_pe_setextled(dd,
572 INFINIPATH_IBCS_L_STATE_DOWN,
573 INFINIPATH_IBCS_LT_STATE_DISABLED);
574 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
575 "mode), no longer usable, SN %.16s\n",
576 dd->ipath_serial);
577 isfatal = 1;
578 }
579 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
580 /* mark as having had error */
581 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
582 /*
583 * mark as not usable, at a minimum until driver
584 * is reloaded, probably until reboot, since no
585 * other reset is possible.
586 */
587 dd->ipath_flags &= ~IPATH_INITTED;
588 } else
589 *msg = 0; /* recovered from all of them */
590
591 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg && msg) {
592 /*
593 * for /sys status file ; if no trailing brace is copied,
594 * we'll know it was truncated.
595 */
596 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
597 "{%s}", msg);
598 }
599}
600
601/**
602 * ipath_pe_boardname - fill in the board name
603 * @dd: the infinipath device
604 * @name: the output buffer
605 * @namelen: the size of the output buffer
606 *
607 * info is based on the board revision register
608 */
609static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
610 size_t namelen)
611{
612 char *n = NULL;
613 u8 boardrev = dd->ipath_boardrev;
614 int ret;
615
616 switch (boardrev) {
617 case 0:
618 n = "InfiniPath_Emulation";
619 break;
620 case 1:
621 n = "InfiniPath_QLE7140-Bringup";
622 break;
623 case 2:
624 n = "InfiniPath_QLE7140";
625 break;
626 case 3:
627 n = "InfiniPath_QMI7140";
628 break;
629 case 4:
630 n = "InfiniPath_QEM7140";
631 break;
632 case 5:
633 n = "InfiniPath_QMH7140";
634 break;
635 case 6:
636 n = "InfiniPath_QLE7142";
637 break;
638 default:
639 ipath_dev_err(dd,
640 "Don't yet know about board with ID %u\n",
641 boardrev);
642 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
643 boardrev);
644 break;
645 }
646 if (n)
647 snprintf(name, namelen, "%s", n);
648
649 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
650 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
651 dd->ipath_majrev, dd->ipath_minrev);
652 ret = 1;
653 } else {
654 ret = 0;
655 if (dd->ipath_minrev >= 2)
656 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
657 }
658
659 /*
660 * set here, not in ipath_init_*_funcs because we have to do
661 * it after we can read chip registers.
662 */
663 dd->ipath_ureg_align =
664 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
665
666 return ret;
667}
668
669/**
670 * ipath_pe_init_hwerrors - enable hardware errors
671 * @dd: the infinipath device
672 *
673 * now that we have finished initializing everything that might reasonably
674 * cause a hardware error, and cleared those errors bits as they occur,
675 * we can enable hardware errors in the mask (potentially enabling
676 * freeze mode), and enable hardware errors as errors (along with
677 * everything else) in errormask
678 */
679static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
680{
681 ipath_err_t val;
682 u64 extsval;
683
684 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
685
686 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
687 ipath_dev_err(dd, "MemBIST did not complete!\n");
688 if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
689 ipath_dbg("MemBIST corrected\n");
690
691 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
692
693 if (!dd->ipath_boardrev) // no PLL for Emulator
694 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
695
696 if (dd->ipath_minrev < 2) {
697 /* workaround bug 9460 in internal interface bus parity
698 * checking. Fixed (HW bug 9490) in Rev2.
699 */
700 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
701 }
702 dd->ipath_hwerrmask = val;
703}
704
705/**
706 * ipath_pe_bringup_serdes - bring up the serdes
707 * @dd: the infinipath device
708 */
709static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
710{
711 u64 val, config1, prev_val;
712 int ret = 0;
713
714 ipath_dbg("Trying to bringup serdes\n");
715
716 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
717 INFINIPATH_HWE_SERDESPLLFAILED) {
718 ipath_dbg("At start, serdes PLL failed bit set "
719 "in hwerrstatus, clearing and continuing\n");
720 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
721 INFINIPATH_HWE_SERDESPLLFAILED);
722 }
723
724 dd->ibdeltainprog = 1;
725 dd->ibsymsnap =
726 ipath_read_creg32(dd, dd->ipath_cregs->cr_ibsymbolerrcnt);
727 dd->iblnkerrsnap =
728 ipath_read_creg32(dd, dd->ipath_cregs->cr_iblinkerrrecovcnt);
729
730 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
731 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
732
733 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
734 "xgxsconfig %llx\n", (unsigned long long) val,
735 (unsigned long long) config1, (unsigned long long)
736 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
737
738 /*
739 * Force reset on, also set rxdetect enable. Must do before reading
740 * serdesstatus at least for simulation, or some of the bits in
741 * serdes status will come back as undefined and cause simulation
742 * failures
743 */
744 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
745 | INFINIPATH_SERDC0_L1PWR_DN;
746 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
747 /* be sure chip saw it */
748 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
749 udelay(5); /* need pll reset set at least for a bit */
750 /*
751 * after PLL is reset, set the per-lane Resets and TxIdle and
752 * clear the PLL reset and rxdetect (to get falling edge).
753 * Leave L1PWR bits set (permanently)
754 */
755 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
756 | INFINIPATH_SERDC0_L1PWR_DN);
757 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
758 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
759 "and txidle (%llx)\n", (unsigned long long) val);
760 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
761 /* be sure chip saw it */
762 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
763 /* need PLL reset clear for at least 11 usec before lane
764 * resets cleared; give it a few more to be sure */
765 udelay(15);
766 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
767
768 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
769 "(writing %llx)\n", (unsigned long long) val);
770 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
771 /* be sure chip saw it */
772 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
773
774 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
775 prev_val = val;
776 if (val & INFINIPATH_XGXS_RESET)
777 val &= ~INFINIPATH_XGXS_RESET;
778 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
779 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
780 /* need to compensate for Tx inversion in partner */
781 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
782 INFINIPATH_XGXS_RX_POL_SHIFT);
783 val |= dd->ipath_rx_pol_inv <<
784 INFINIPATH_XGXS_RX_POL_SHIFT;
785 }
786 if (val != prev_val)
787 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
788
789 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
790
791 /* clear current and de-emphasis bits */
792 config1 &= ~0x0ffffffff00ULL;
793 /* set current to 20ma */
794 config1 |= 0x00000000000ULL;
795 /* set de-emphasis to -5.68dB */
796 config1 |= 0x0cccc000000ULL;
797 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
798
799 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
800 "config1=%llx, sstatus=%llx xgxs=%llx\n",
801 (unsigned long long) val, (unsigned long long) config1,
802 (unsigned long long)
803 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
804 (unsigned long long)
805 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
806
807 return ret;
808}
809
810/**
811 * ipath_pe_quiet_serdes - set serdes to txidle
812 * @dd: the infinipath device
813 * Called when driver is being unloaded
814 */
815static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
816{
817 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
818
819 if (dd->ibsymdelta || dd->iblnkerrdelta ||
820 dd->ibdeltainprog) {
821 u64 diagc;
822 /* enable counter writes */
823 diagc = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwdiagctrl);
824 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwdiagctrl,
825 diagc | INFINIPATH_DC_COUNTERWREN);
826
827 if (dd->ibsymdelta || dd->ibdeltainprog) {
828 val = ipath_read_creg32(dd,
829 dd->ipath_cregs->cr_ibsymbolerrcnt);
830 if (dd->ibdeltainprog)
831 val -= val - dd->ibsymsnap;
832 val -= dd->ibsymdelta;
833 ipath_write_creg(dd,
834 dd->ipath_cregs->cr_ibsymbolerrcnt, val);
835 }
836 if (dd->iblnkerrdelta || dd->ibdeltainprog) {
837 val = ipath_read_creg32(dd,
838 dd->ipath_cregs->cr_iblinkerrrecovcnt);
839 if (dd->ibdeltainprog)
840 val -= val - dd->iblnkerrsnap;
841 val -= dd->iblnkerrdelta;
842 ipath_write_creg(dd,
843 dd->ipath_cregs->cr_iblinkerrrecovcnt, val);
844 }
845
846 /* and disable counter writes */
847 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwdiagctrl, diagc);
848 }
849 val |= INFINIPATH_SERDC0_TXIDLE;
850 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
851 (unsigned long long) val);
852 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
853}
854
855static int ipath_pe_intconfig(struct ipath_devdata *dd)
856{
857 u32 chiprev;
858
859 /*
860 * If the chip supports added error indication via GPIO pins,
861 * enable interrupts on those bits so the interrupt routine
862 * can count the events. Also set flag so interrupt routine
863 * can know they are expected.
864 */
865 chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
866 if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
867 /* Rev2+ reports extra errors via internal GPIO pins */
868 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
869 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
870 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
871 dd->ipath_gpio_mask);
872 }
873 return 0;
874}
875
876/**
877 * ipath_setup_pe_setextled - set the state of the two external LEDs
878 * @dd: the infinipath device
879 * @lst: the L state
880 * @ltst: the LT state
881
882 * These LEDs indicate the physical and logical state of IB link.
883 * For this chip (at least with recommended board pinouts), LED1
884 * is Yellow (logical state) and LED2 is Green (physical state),
885 *
886 * Note: We try to match the Mellanox HCA LED behavior as best
887 * we can. Green indicates physical link state is OK (something is
888 * plugged in, and we can train).
889 * Amber indicates the link is logically up (ACTIVE).
890 * Mellanox further blinks the amber LED to indicate data packet
891 * activity, but we have no hardware support for that, so it would
892 * require waking up every 10-20 msecs and checking the counters
893 * on the chip, and then turning the LED off if appropriate. That's
894 * visible overhead, so not something we will do.
895 *
896 */
897static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
898 u64 ltst)
899{
900 u64 extctl;
901 unsigned long flags = 0;
902
903 /* the diags use the LED to indicate diag info, so we leave
904 * the external LED alone when the diags are running */
905 if (ipath_diag_inuse)
906 return;
907
908 /* Allow override of LED display for, e.g. Locating system in rack */
909 if (dd->ipath_led_override) {
910 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
911 ? INFINIPATH_IBCS_LT_STATE_LINKUP
912 : INFINIPATH_IBCS_LT_STATE_DISABLED;
913 lst = (dd->ipath_led_override & IPATH_LED_LOG)
914 ? INFINIPATH_IBCS_L_STATE_ACTIVE
915 : INFINIPATH_IBCS_L_STATE_DOWN;
916 }
917
918 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
919 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
920 INFINIPATH_EXTC_LED2PRIPORT_ON);
921
922 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
923 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
924 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
925 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
926 dd->ipath_extctrl = extctl;
927 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
928 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
929}
930
931/**
932 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
933 * @dd: the infinipath device
934 *
935 * This is called during driver unload.
936 * We do the pci_disable_msi here, not in generic code, because it
937 * isn't used for the HT chips. If we do end up needing pci_enable_msi
938 * at some point in the future for HT, we'll move the call back
939 * into the main init_one code.
940 */
941static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
942{
943 dd->ipath_msi_lo = 0; /* just in case unload fails */
944 pci_disable_msi(dd->pcidev);
945}
946
947static void ipath_6120_pcie_params(struct ipath_devdata *dd)
948{
949 u16 linkstat, speed;
950 int pos;
951
952 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP);
953 if (!pos) {
954 ipath_dev_err(dd, "Can't find PCI Express capability!\n");
955 goto bail;
956 }
957
958 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
959 &linkstat);
960 /*
961 * speed is bits 0-4, linkwidth is bits 4-8
962 * no defines for them in headers
963 */
964 speed = linkstat & 0xf;
965 linkstat >>= 4;
966 linkstat &= 0x1f;
967 dd->ipath_lbus_width = linkstat;
968
969 switch (speed) {
970 case 1:
971 dd->ipath_lbus_speed = 2500; /* Gen1, 2.5GHz */
972 break;
973 case 2:
974 dd->ipath_lbus_speed = 5000; /* Gen1, 5GHz */
975 break;
976 default: /* not defined, assume gen1 */
977 dd->ipath_lbus_speed = 2500;
978 break;
979 }
980
981 if (linkstat < 8)
982 ipath_dev_err(dd,
983 "PCIe width %u (x8 HCA), performance reduced\n",
984 linkstat);
985 else
986 ipath_cdbg(VERBOSE, "PCIe speed %u width %u (x8 HCA)\n",
987 dd->ipath_lbus_speed, linkstat);
988
989 if (speed != 1)
990 ipath_dev_err(dd,
991 "PCIe linkspeed %u is incorrect; "
992 "should be 1 (2500)!\n", speed);
993bail:
994 /* fill in string, even on errors */
995 snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
996 "PCIe,%uMHz,x%u\n",
997 dd->ipath_lbus_speed,
998 dd->ipath_lbus_width);
999
1000 return;
1001}
1002
1003/**
1004 * ipath_setup_pe_config - setup PCIe config related stuff
1005 * @dd: the infinipath device
1006 * @pdev: the PCI device
1007 *
1008 * The pci_enable_msi() call will fail on systems with MSI quirks
1009 * such as those with AMD8131, even if the device of interest is not
1010 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
1011 * late in 2.6.16).
1012 * All that can be done is to edit the kernel source to remove the quirk
1013 * check until that is fixed.
1014 * We do not need to call enable_msi() for our HyperTransport chip,
1015 * even though it uses MSI, and we want to avoid the quirk warning, so
1016 * So we call enable_msi only for PCIe. If we do end up needing
1017 * pci_enable_msi at some point in the future for HT, we'll move the
1018 * call back into the main init_one code.
1019 * We save the msi lo and hi values, so we can restore them after
1020 * chip reset (the kernel PCI infrastructure doesn't yet handle that
1021 * correctly).
1022 */
1023static int ipath_setup_pe_config(struct ipath_devdata *dd,
1024 struct pci_dev *pdev)
1025{
1026 int pos, ret;
1027
1028 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
1029 ret = pci_enable_msi(dd->pcidev);
1030 if (ret)
1031 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1032 "interrupts may not work\n", ret);
1033 /* continue even if it fails, we may still be OK... */
1034 dd->ipath_irq = pdev->irq;
1035
1036 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1037 u16 control;
1038 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1039 &dd->ipath_msi_lo);
1040 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1041 &dd->ipath_msi_hi);
1042 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1043 &control);
1044 /* now save the data (vector) info */
1045 pci_read_config_word(dd->pcidev,
1046 pos + ((control & PCI_MSI_FLAGS_64BIT)
1047 ? 12 : 8),
1048 &dd->ipath_msi_data);
1049 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
1050 "0x%x, control=0x%x\n", dd->ipath_msi_data,
1051 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1052 control);
1053 /* we save the cachelinesize also, although it doesn't
1054 * really matter */
1055 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1056 &dd->ipath_pci_cacheline);
1057 } else
1058 ipath_dev_err(dd, "Can't find MSI capability, "
1059 "can't save MSI settings for reset\n");
1060
1061 ipath_6120_pcie_params(dd);
1062
1063 dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1064 dd->ipath_link_speed_supported = IPATH_IB_SDR;
1065 dd->ipath_link_width_enabled = IB_WIDTH_4X;
1066 dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1067 /* these can't change for this chip, so set once */
1068 dd->ipath_link_width_active = dd->ipath_link_width_enabled;
1069 dd->ipath_link_speed_active = dd->ipath_link_speed_enabled;
1070 return 0;
1071}
1072
1073static void ipath_init_pe_variables(struct ipath_devdata *dd)
1074{
1075 /*
1076 * setup the register offsets, since they are different for each
1077 * chip
1078 */
1079 dd->ipath_kregs = &ipath_pe_kregs;
1080 dd->ipath_cregs = &ipath_pe_cregs;
1081
1082 /*
1083 * bits for selecting i2c direction and values,
1084 * used for I2C serial flash
1085 */
1086 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1087 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1088 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1089 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1090
1091 /*
1092 * Fill in data for field-values that change in newer chips.
1093 * We dynamically specify only the mask for LINKTRAININGSTATE
1094 * and only the shift for LINKSTATE, as they are the only ones
1095 * that change. Also precalculate the 3 link states of interest
1096 * and the combined mask.
1097 */
1098 dd->ibcs_ls_shift = IBA6120_IBCS_LINKSTATE_SHIFT;
1099 dd->ibcs_lts_mask = IBA6120_IBCS_LINKTRAININGSTATE_MASK;
1100 dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1101 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1102 dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1103 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1104 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1105 dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1106 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1107 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1108 dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1109 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1110 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1111
1112 /*
1113 * Fill in data for ibcc field-values that change in newer chips.
1114 * We dynamically specify only the mask for LINKINITCMD
1115 * and only the shift for LINKCMD and MAXPKTLEN, as they are
1116 * the only ones that change.
1117 */
1118 dd->ibcc_lic_mask = INFINIPATH_IBCC_LINKINITCMD_MASK;
1119 dd->ibcc_lc_shift = INFINIPATH_IBCC_LINKCMD_SHIFT;
1120 dd->ibcc_mpl_shift = INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1121
1122 /* Fill in shifts for RcvCtrl. */
1123 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1124 dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1125 dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1126 dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */
1127
1128 /* variables for sanity checking interrupt and errors */
1129 dd->ipath_hwe_bitsextant =
1130 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1131 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1132 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1133 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1134 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
1135 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
1136 INFINIPATH_HWE_PCIE1PLLFAILED |
1137 INFINIPATH_HWE_PCIE0PLLFAILED |
1138 INFINIPATH_HWE_PCIEPOISONEDTLP |
1139 INFINIPATH_HWE_PCIECPLTIMEOUT |
1140 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
1141 INFINIPATH_HWE_PCIEBUSPARITYXADM |
1142 INFINIPATH_HWE_PCIEBUSPARITYRADM |
1143 INFINIPATH_HWE_MEMBISTFAILED |
1144 INFINIPATH_HWE_COREPLL_FBSLIP |
1145 INFINIPATH_HWE_COREPLL_RFSLIP |
1146 INFINIPATH_HWE_SERDESPLLFAILED |
1147 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1148 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1149 dd->ipath_i_bitsextant =
1150 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1151 (INFINIPATH_I_RCVAVAIL_MASK <<
1152 INFINIPATH_I_RCVAVAIL_SHIFT) |
1153 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1154 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1155 dd->ipath_e_bitsextant =
1156 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1157 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1158 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1159 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1160 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1161 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1162 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1163 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1164 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1165 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1166 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1167 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1168 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1169 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1170 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1171 INFINIPATH_E_HARDWARE;
1172
1173 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1174 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1175 dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1176 dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1177
1178 /*
1179 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1180 * 2 is Some Misc, 3 is reserved for future.
1181 */
1182 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1183 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1184 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1185
1186 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
1187 if (ipath_unordered_wc())
1188 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
1189
1190 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1191 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1192 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1193
1194 dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1195 dd->delay_mult = 2; /* SDR, 4X, can't change */
1196}
1197
1198/* setup the MSI stuff again after a reset. I'd like to just call
1199 * pci_enable_msi() and request_irq() again, but when I do that,
1200 * the MSI enable bit doesn't get set in the command word, and
1201 * we switch to to a different interrupt vector, which is confusing,
1202 * so I instead just do it all inline. Perhaps somehow can tie this
1203 * into the PCIe hotplug support at some point
1204 * Note, because I'm doing it all here, I don't call pci_disable_msi()
1205 * or free_irq() at the start of ipath_setup_pe_reset().
1206 */
1207static int ipath_reinit_msi(struct ipath_devdata *dd)
1208{
1209 int pos;
1210 u16 control;
1211 int ret;
1212
1213 if (!dd->ipath_msi_lo) {
1214 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1215 "initial setup failed?\n");
1216 ret = 0;
1217 goto bail;
1218 }
1219
1220 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1221 ipath_dev_err(dd, "Can't find MSI capability, "
1222 "can't restore MSI settings\n");
1223 ret = 0;
1224 goto bail;
1225 }
1226 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1227 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1228 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1229 dd->ipath_msi_lo);
1230 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1231 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1232 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1233 dd->ipath_msi_hi);
1234 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1235 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1236 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1237 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1238 control, control | PCI_MSI_FLAGS_ENABLE);
1239 control |= PCI_MSI_FLAGS_ENABLE;
1240 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1241 control);
1242 }
1243 /* now rewrite the data (vector) info */
1244 pci_write_config_word(dd->pcidev, pos +
1245 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1246 dd->ipath_msi_data);
1247 /* we restore the cachelinesize also, although it doesn't really
1248 * matter */
1249 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1250 dd->ipath_pci_cacheline);
1251 /* and now set the pci master bit again */
1252 pci_set_master(dd->pcidev);
1253 ret = 1;
1254
1255bail:
1256 return ret;
1257}
1258
1259/* This routine sleeps, so it can only be called from user context, not
1260 * from interrupt context. If we need interrupt context, we can split
1261 * it into two routines.
1262*/
1263static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1264{
1265 u64 val;
1266 int i;
1267 int ret;
1268 u16 cmdval;
1269
1270 pci_read_config_word(dd->pcidev, PCI_COMMAND, &cmdval);
1271
1272 /* Use ERROR so it shows up in logs, etc. */
1273 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1274 /* keep chip from being accessed in a few places */
1275 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1276 val = dd->ipath_control | INFINIPATH_C_RESET;
1277 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1278 mb();
1279
1280 for (i = 1; i <= 5; i++) {
1281 int r;
1282 /* allow MBIST, etc. to complete; longer on each retry.
1283 * We sometimes get machine checks from bus timeout if no
1284 * response, so for now, make it *really* long.
1285 */
1286 msleep(1000 + (1 + i) * 2000);
1287 if ((r =
1288 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1289 dd->ipath_pcibar0)))
1290 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1291 r);
1292 if ((r =
1293 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1294 dd->ipath_pcibar1)))
1295 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1296 r);
1297 /* now re-enable memory access */
1298 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmdval);
1299 if ((r = pci_enable_device(dd->pcidev)))
1300 ipath_dev_err(dd, "pci_enable_device failed after "
1301 "reset: %d\n", r);
1302 /*
1303 * whether it fully enabled or not, mark as present,
1304 * again (but not INITTED)
1305 */
1306 dd->ipath_flags |= IPATH_PRESENT;
1307 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1308 if (val == dd->ipath_revision) {
1309 ipath_cdbg(VERBOSE, "Got matching revision "
1310 "register %llx on try %d\n",
1311 (unsigned long long) val, i);
1312 ret = ipath_reinit_msi(dd);
1313 goto bail;
1314 }
1315 /* Probably getting -1 back */
1316 ipath_dbg("Didn't get expected revision register, "
1317 "got %llx, try %d\n", (unsigned long long) val,
1318 i + 1);
1319 }
1320 ret = 0; /* failed */
1321
1322bail:
1323 if (ret)
1324 ipath_6120_pcie_params(dd);
1325 return ret;
1326}
1327
1328/**
1329 * ipath_pe_put_tid - write a TID in chip
1330 * @dd: the infinipath device
1331 * @tidptr: pointer to the expected TID (in chip) to update
1332 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1333 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1334 *
1335 * This exists as a separate routine to allow for special locking etc.
1336 * It's used for both the full cleanup on exit, as well as the normal
1337 * setup and teardown.
1338 */
1339static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1340 u32 type, unsigned long pa)
1341{
1342 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1343 unsigned long flags = 0; /* keep gcc quiet */
1344 int tidx;
1345 spinlock_t *tidlockp;
1346
1347 if (!dd->ipath_kregbase)
1348 return;
1349
1350 if (pa != dd->ipath_tidinvalid) {
1351 if (pa & ((1U << 11) - 1)) {
1352 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1353 "not 2KB aligned!\n", pa);
1354 return;
1355 }
1356 pa >>= 11;
1357 /* paranoia check */
1358 if (pa & ~INFINIPATH_RT_ADDR_MASK)
1359 ipath_dev_err(dd,
1360 "BUG: Physical page address 0x%lx "
1361 "has bits set in 31-29\n", pa);
1362
1363 if (type == RCVHQ_RCV_TYPE_EAGER)
1364 pa |= dd->ipath_tidtemplate;
1365 else /* for now, always full 4KB page */
1366 pa |= 2 << 29;
1367 }
1368
1369 /*
1370 * Workaround chip bug 9437 by writing the scratch register
1371 * before and after the TID, and with an io write barrier.
1372 * We use a spinlock around the writes, so they can't intermix
1373 * with other TID (eager or expected) writes (the chip bug
1374 * is triggered by back to back TID writes). Unfortunately, this
1375 * call can be done from interrupt level for the port 0 eager TIDs,
1376 * so we have to use irqsave locks.
1377 */
1378 /*
1379 * Assumes tidptr always > ipath_egrtidbase
1380 * if type == RCVHQ_RCV_TYPE_EAGER.
1381 */
1382 tidx = tidptr - dd->ipath_egrtidbase;
1383
1384 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->ipath_rcvegrcnt)
1385 ? &dd->ipath_kernel_tid_lock : &dd->ipath_user_tid_lock;
1386 spin_lock_irqsave(tidlockp, flags);
1387 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1388 writel(pa, tidp32);
1389 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1390 mmiowb();
1391 spin_unlock_irqrestore(tidlockp, flags);
1392}
1393
1394/**
1395 * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1396 * @dd: the infinipath device
1397 * @tidptr: pointer to the expected TID (in chip) to update
1398 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1399 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1400 *
1401 * This exists as a separate routine to allow for selection of the
1402 * appropriate "flavor". The static calls in cleanup just use the
1403 * revision-agnostic form, as they are not performance critical.
1404 */
1405static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1406 u32 type, unsigned long pa)
1407{
1408 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1409 u32 tidx;
1410
1411 if (!dd->ipath_kregbase)
1412 return;
1413
1414 if (pa != dd->ipath_tidinvalid) {
1415 if (pa & ((1U << 11) - 1)) {
1416 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1417 "not 2KB aligned!\n", pa);
1418 return;
1419 }
1420 pa >>= 11;
1421 /* paranoia check */
1422 if (pa & ~INFINIPATH_RT_ADDR_MASK)
1423 ipath_dev_err(dd,
1424 "BUG: Physical page address 0x%lx "
1425 "has bits set in 31-29\n", pa);
1426
1427 if (type == RCVHQ_RCV_TYPE_EAGER)
1428 pa |= dd->ipath_tidtemplate;
1429 else /* for now, always full 4KB page */
1430 pa |= 2 << 29;
1431 }
1432 tidx = tidptr - dd->ipath_egrtidbase;
1433 writel(pa, tidp32);
1434 mmiowb();
1435}
1436
1437
1438/**
1439 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1440 * @dd: the infinipath device
1441 * @port: the port
1442 *
1443 * clear all TID entries for a port, expected and eager.
1444 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
1445 * not 64, but they are still on 64 bit boundaries, so tidbase
1446 * is declared as u64 * for the pointer math, even though we write 32 bits
1447 */
1448static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1449{
1450 u64 __iomem *tidbase;
1451 unsigned long tidinv;
1452 int i;
1453
1454 if (!dd->ipath_kregbase)
1455 return;
1456
1457 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1458
1459 tidinv = dd->ipath_tidinvalid;
1460 tidbase = (u64 __iomem *)
1461 ((char __iomem *)(dd->ipath_kregbase) +
1462 dd->ipath_rcvtidbase +
1463 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1464
1465 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1466 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1467 tidinv);
1468
1469 tidbase = (u64 __iomem *)
1470 ((char __iomem *)(dd->ipath_kregbase) +
1471 dd->ipath_rcvegrbase +
1472 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1473
1474 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1475 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1476 tidinv);
1477}
1478
1479/**
1480 * ipath_pe_tidtemplate - setup constants for TID updates
1481 * @dd: the infinipath device
1482 *
1483 * We setup stuff that we use a lot, to avoid calculating each time
1484 */
1485static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1486{
1487 u32 egrsize = dd->ipath_rcvegrbufsize;
1488
1489 /* For now, we always allocate 4KB buffers (at init) so we can
1490 * receive max size packets. We may want a module parameter to
1491 * specify 2KB or 4KB and/or make be per port instead of per device
1492 * for those who want to reduce memory footprint. Note that the
1493 * ipath_rcvhdrentsize size must be large enough to hold the largest
1494 * IB header (currently 96 bytes) that we expect to handle (plus of
1495 * course the 2 dwords of RHF).
1496 */
1497 if (egrsize == 2048)
1498 dd->ipath_tidtemplate = 1U << 29;
1499 else if (egrsize == 4096)
1500 dd->ipath_tidtemplate = 2U << 29;
1501 else {
1502 egrsize = 4096;
1503 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1504 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1505 egrsize);
1506 dd->ipath_tidtemplate = 2U << 29;
1507 }
1508 dd->ipath_tidinvalid = 0;
1509}
1510
1511static int ipath_pe_early_init(struct ipath_devdata *dd)
1512{
1513 dd->ipath_flags |= IPATH_4BYTE_TID;
1514 if (ipath_unordered_wc())
1515 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
1516
1517 /*
1518 * For openfabrics, we need to be able to handle an IB header of
1519 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1520 * made them the same size as the PIO buffers. This chip does not
1521 * handle arbitrary size buffers, so we need the header large enough
1522 * to handle largest IB header, but still have room for a 2KB MTU
1523 * standard IB packet.
1524 */
1525 dd->ipath_rcvhdrentsize = 24;
1526 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1527 dd->ipath_rhf_offset = 0;
1528 dd->ipath_egrtidbase = (u64 __iomem *)
1529 ((char __iomem *) dd->ipath_kregbase + dd->ipath_rcvegrbase);
1530
1531 dd->ipath_rcvegrbufsize = ipath_mtu4096 ? 4096 : 2048;
1532 /*
1533 * the min() check here is currently a nop, but it may not always
1534 * be, depending on just how we do ipath_rcvegrbufsize
1535 */
1536 dd->ipath_ibmaxlen = min(ipath_mtu4096 ? dd->ipath_piosize4k :
1537 dd->ipath_piosize2k,
1538 dd->ipath_rcvegrbufsize +
1539 (dd->ipath_rcvhdrentsize << 2));
1540 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1541
1542 /*
1543 * We can request a receive interrupt for 1 or
1544 * more packets from current offset. For now, we set this
1545 * up for a single packet.
1546 */
1547 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1548
1549 ipath_get_eeprom_info(dd);
1550
1551 return 0;
1552}
1553
1554int __attribute__((weak)) ipath_unordered_wc(void)
1555{
1556 return 0;
1557}
1558
1559/**
1560 * ipath_init_pe_get_base_info - set chip-specific flags for user code
1561 * @pd: the infinipath port
1562 * @kbase: ipath_base_info pointer
1563 *
1564 * We set the PCIE flag because the lower bandwidth on PCIe vs
1565 * HyperTransport can affect some user packet algorithms.
1566 */
1567static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1568{
1569 struct ipath_base_info *kinfo = kbase;
1570 struct ipath_devdata *dd;
1571
1572 if (ipath_unordered_wc()) {
1573 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1574 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1575 }
1576 else
1577 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1578
1579 if (pd == NULL)
1580 goto done;
1581
1582 dd = pd->port_dd;
1583
1584done:
1585 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1586 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
1587 return 0;
1588}
1589
1590static void ipath_pe_free_irq(struct ipath_devdata *dd)
1591{
1592 free_irq(dd->ipath_irq, dd);
1593 dd->ipath_irq = 0;
1594}
1595
1596
1597static struct ipath_message_header *
1598ipath_pe_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1599{
1600 return (struct ipath_message_header *)
1601 &rhf_addr[sizeof(u64) / sizeof(u32)];
1602}
1603
1604static void ipath_pe_config_ports(struct ipath_devdata *dd, ushort cfgports)
1605{
1606 dd->ipath_portcnt =
1607 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1608 dd->ipath_p0_rcvegrcnt =
1609 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1610}
1611
1612static void ipath_pe_read_counters(struct ipath_devdata *dd,
1613 struct infinipath_counters *cntrs)
1614{
1615 cntrs->LBIntCnt =
1616 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1617 cntrs->LBFlowStallCnt =
1618 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1619 cntrs->TxSDmaDescCnt = 0;
1620 cntrs->TxUnsupVLErrCnt =
1621 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1622 cntrs->TxDataPktCnt =
1623 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1624 cntrs->TxFlowPktCnt =
1625 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1626 cntrs->TxDwordCnt =
1627 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1628 cntrs->TxLenErrCnt =
1629 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1630 cntrs->TxMaxMinLenErrCnt =
1631 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1632 cntrs->TxUnderrunCnt =
1633 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1634 cntrs->TxFlowStallCnt =
1635 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1636 cntrs->TxDroppedPktCnt =
1637 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1638 cntrs->RxDroppedPktCnt =
1639 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1640 cntrs->RxDataPktCnt =
1641 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1642 cntrs->RxFlowPktCnt =
1643 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1644 cntrs->RxDwordCnt =
1645 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1646 cntrs->RxLenErrCnt =
1647 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1648 cntrs->RxMaxMinLenErrCnt =
1649 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1650 cntrs->RxICRCErrCnt =
1651 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1652 cntrs->RxVCRCErrCnt =
1653 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1654 cntrs->RxFlowCtrlErrCnt =
1655 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1656 cntrs->RxBadFormatCnt =
1657 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1658 cntrs->RxLinkProblemCnt =
1659 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1660 cntrs->RxEBPCnt =
1661 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1662 cntrs->RxLPCRCErrCnt =
1663 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1664 cntrs->RxBufOvflCnt =
1665 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1666 cntrs->RxTIDFullErrCnt =
1667 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1668 cntrs->RxTIDValidErrCnt =
1669 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1670 cntrs->RxPKeyMismatchCnt =
1671 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1672 cntrs->RxP0HdrEgrOvflCnt =
1673 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1674 cntrs->RxP1HdrEgrOvflCnt =
1675 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1676 cntrs->RxP2HdrEgrOvflCnt =
1677 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1678 cntrs->RxP3HdrEgrOvflCnt =
1679 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1680 cntrs->RxP4HdrEgrOvflCnt =
1681 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1682 cntrs->RxP5HdrEgrOvflCnt = 0;
1683 cntrs->RxP6HdrEgrOvflCnt = 0;
1684 cntrs->RxP7HdrEgrOvflCnt = 0;
1685 cntrs->RxP8HdrEgrOvflCnt = 0;
1686 cntrs->RxP9HdrEgrOvflCnt = 0;
1687 cntrs->RxP10HdrEgrOvflCnt = 0;
1688 cntrs->RxP11HdrEgrOvflCnt = 0;
1689 cntrs->RxP12HdrEgrOvflCnt = 0;
1690 cntrs->RxP13HdrEgrOvflCnt = 0;
1691 cntrs->RxP14HdrEgrOvflCnt = 0;
1692 cntrs->RxP15HdrEgrOvflCnt = 0;
1693 cntrs->RxP16HdrEgrOvflCnt = 0;
1694 cntrs->IBStatusChangeCnt =
1695 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1696 cntrs->IBLinkErrRecoveryCnt =
1697 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1698 cntrs->IBLinkDownedCnt =
1699 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1700 cntrs->IBSymbolErrCnt =
1701 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1702 cntrs->RxVL15DroppedPktCnt = 0;
1703 cntrs->RxOtherLocalPhyErrCnt = 0;
1704 cntrs->PcieRetryBufDiagQwordCnt = 0;
1705 cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1706 cntrs->LocalLinkIntegrityErrCnt = dd->ipath_lli_errs;
1707 cntrs->RxVlErrCnt = 0;
1708 cntrs->RxDlidFltrCnt = 0;
1709}
1710
1711
1712/* no interrupt fallback for these chips */
1713static int ipath_pe_nointr_fallback(struct ipath_devdata *dd)
1714{
1715 return 0;
1716}
1717
1718
1719/*
1720 * reset the XGXS (between serdes and IBC). Slightly less intrusive
1721 * than resetting the IBC or external link state, and useful in some
1722 * cases to cause some retraining. To do this right, we reset IBC
1723 * as well.
1724 */
1725static void ipath_pe_xgxs_reset(struct ipath_devdata *dd)
1726{
1727 u64 val, prev_val;
1728
1729 prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1730 val = prev_val | INFINIPATH_XGXS_RESET;
1731 prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
1732 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1733 dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
1734 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1735 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1736 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
1737 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1738 dd->ipath_control);
1739}
1740
1741
1742static int ipath_pe_get_ib_cfg(struct ipath_devdata *dd, int which)
1743{
1744 int ret;
1745
1746 switch (which) {
1747 case IPATH_IB_CFG_LWID:
1748 ret = dd->ipath_link_width_active;
1749 break;
1750 case IPATH_IB_CFG_SPD:
1751 ret = dd->ipath_link_speed_active;
1752 break;
1753 case IPATH_IB_CFG_LWID_ENB:
1754 ret = dd->ipath_link_width_enabled;
1755 break;
1756 case IPATH_IB_CFG_SPD_ENB:
1757 ret = dd->ipath_link_speed_enabled;
1758 break;
1759 default:
1760 ret = -ENOTSUPP;
1761 break;
1762 }
1763 return ret;
1764}
1765
1766
1767/* we assume range checking is already done, if needed */
1768static int ipath_pe_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
1769{
1770 int ret = 0;
1771
1772 if (which == IPATH_IB_CFG_LWID_ENB)
1773 dd->ipath_link_width_enabled = val;
1774 else if (which == IPATH_IB_CFG_SPD_ENB)
1775 dd->ipath_link_speed_enabled = val;
1776 else
1777 ret = -ENOTSUPP;
1778 return ret;
1779}
1780
1781static void ipath_pe_config_jint(struct ipath_devdata *dd, u16 a, u16 b)
1782{
1783}
1784
1785
1786static int ipath_pe_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
1787{
1788 if (ibup) {
1789 if (dd->ibdeltainprog) {
1790 dd->ibdeltainprog = 0;
1791 dd->ibsymdelta +=
1792 ipath_read_creg32(dd,
1793 dd->ipath_cregs->cr_ibsymbolerrcnt) -
1794 dd->ibsymsnap;
1795 dd->iblnkerrdelta +=
1796 ipath_read_creg32(dd,
1797 dd->ipath_cregs->cr_iblinkerrrecovcnt) -
1798 dd->iblnkerrsnap;
1799 }
1800 } else {
1801 dd->ipath_lli_counter = 0;
1802 if (!dd->ibdeltainprog) {
1803 dd->ibdeltainprog = 1;
1804 dd->ibsymsnap =
1805 ipath_read_creg32(dd,
1806 dd->ipath_cregs->cr_ibsymbolerrcnt);
1807 dd->iblnkerrsnap =
1808 ipath_read_creg32(dd,
1809 dd->ipath_cregs->cr_iblinkerrrecovcnt);
1810 }
1811 }
1812
1813 ipath_setup_pe_setextled(dd, ipath_ib_linkstate(dd, ibcs),
1814 ipath_ib_linktrstate(dd, ibcs));
1815 return 0;
1816}
1817
1818
1819/**
1820 * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1821 * @dd: the infinipath device
1822 *
1823 * This is global, and is called directly at init to set up the
1824 * chip-specific function pointers for later use.
1825 */
1826void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1827{
1828 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1829 dd->ipath_f_bus = ipath_setup_pe_config;
1830 dd->ipath_f_reset = ipath_setup_pe_reset;
1831 dd->ipath_f_get_boardname = ipath_pe_boardname;
1832 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1833 dd->ipath_f_early_init = ipath_pe_early_init;
1834 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1835 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1836 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1837 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1838 /*
1839 * _f_put_tid may get changed after we read the chip revision,
1840 * but we start with the safe version for all revs
1841 */
1842 dd->ipath_f_put_tid = ipath_pe_put_tid;
1843 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1844 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1845 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1846 dd->ipath_f_free_irq = ipath_pe_free_irq;
1847 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1848 dd->ipath_f_intr_fallback = ipath_pe_nointr_fallback;
1849 dd->ipath_f_xgxs_reset = ipath_pe_xgxs_reset;
1850 dd->ipath_f_get_msgheader = ipath_pe_get_msgheader;
1851 dd->ipath_f_config_ports = ipath_pe_config_ports;
1852 dd->ipath_f_read_counters = ipath_pe_read_counters;
1853 dd->ipath_f_get_ib_cfg = ipath_pe_get_ib_cfg;
1854 dd->ipath_f_set_ib_cfg = ipath_pe_set_ib_cfg;
1855 dd->ipath_f_config_jint = ipath_pe_config_jint;
1856 dd->ipath_f_ib_updown = ipath_pe_ib_updown;
1857
1858
1859 /* initialize chip-specific variables */
1860 ipath_init_pe_variables(dd);
1861}
1862
diff --git a/drivers/infiniband/hw/ipath/ipath_iba7220.c b/drivers/infiniband/hw/ipath/ipath_iba7220.c
deleted file mode 100644
index 34b778ed97f..00000000000
--- a/drivers/infiniband/hw/ipath/ipath_iba7220.c
+++ /dev/null
@@ -1,2631 +0,0 @@
1/*
2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33/*
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7220 chip (except that specific to the SerDes)
36 */
37
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/sched.h>
41#include <linux/delay.h>
42#include <linux/io.h>
43#include <rdma/ib_verbs.h>
44
45#include "ipath_kernel.h"
46#include "ipath_registers.h"
47#include "ipath_7220.h"
48
49static void ipath_setup_7220_setextled(struct ipath_devdata *, u64, u64);
50
51static unsigned ipath_compat_ddr_negotiate = 1;
52
53module_param_named(compat_ddr_negotiate, ipath_compat_ddr_negotiate, uint,
54 S_IWUSR | S_IRUGO);
55MODULE_PARM_DESC(compat_ddr_negotiate,
56 "Attempt pre-IBTA 1.2 DDR speed negotiation");
57
58static unsigned ipath_sdma_fetch_arb = 1;
59module_param_named(fetch_arb, ipath_sdma_fetch_arb, uint, S_IRUGO);
60MODULE_PARM_DESC(fetch_arb, "IBA7220: change SDMA descriptor arbitration");
61
62/*
63 * This file contains almost all the chip-specific register information and
64 * access functions for the QLogic InfiniPath 7220 PCI-Express chip, with the
65 * exception of SerDes support, which in in ipath_sd7220.c.
66 *
67 * This lists the InfiniPath registers, in the actual chip layout.
68 * This structure should never be directly accessed.
69 */
70struct _infinipath_do_not_use_kernel_regs {
71 unsigned long long Revision;
72 unsigned long long Control;
73 unsigned long long PageAlign;
74 unsigned long long PortCnt;
75 unsigned long long DebugPortSelect;
76 unsigned long long DebugSigsIntSel; /* was Reserved0;*/
77 unsigned long long SendRegBase;
78 unsigned long long UserRegBase;
79 unsigned long long CounterRegBase;
80 unsigned long long Scratch;
81 unsigned long long EEPROMAddrCmd; /* was Reserved1; */
82 unsigned long long EEPROMData; /* was Reserved2; */
83 unsigned long long IntBlocked;
84 unsigned long long IntMask;
85 unsigned long long IntStatus;
86 unsigned long long IntClear;
87 unsigned long long ErrorMask;
88 unsigned long long ErrorStatus;
89 unsigned long long ErrorClear;
90 unsigned long long HwErrMask;
91 unsigned long long HwErrStatus;
92 unsigned long long HwErrClear;
93 unsigned long long HwDiagCtrl;
94 unsigned long long MDIO;
95 unsigned long long IBCStatus;
96 unsigned long long IBCCtrl;
97 unsigned long long ExtStatus;
98 unsigned long long ExtCtrl;
99 unsigned long long GPIOOut;
100 unsigned long long GPIOMask;
101 unsigned long long GPIOStatus;
102 unsigned long long GPIOClear;
103 unsigned long long RcvCtrl;
104 unsigned long long RcvBTHQP;
105 unsigned long long RcvHdrSize;
106 unsigned long long RcvHdrCnt;
107 unsigned long long RcvHdrEntSize;
108 unsigned long long RcvTIDBase;
109 unsigned long long RcvTIDCnt;
110 unsigned long long RcvEgrBase;
111 unsigned long long RcvEgrCnt;
112 unsigned long long RcvBufBase;
113 unsigned long long RcvBufSize;
114 unsigned long long RxIntMemBase;
115 unsigned long long RxIntMemSize;
116 unsigned long long RcvPartitionKey;
117 unsigned long long RcvQPMulticastPort;
118 unsigned long long RcvPktLEDCnt;
119 unsigned long long IBCDDRCtrl;
120 unsigned long long HRTBT_GUID;
121 unsigned long long IB_SDTEST_IF_TX;
122 unsigned long long IB_SDTEST_IF_RX;
123 unsigned long long IBCDDRCtrl2;
124 unsigned long long IBCDDRStatus;
125 unsigned long long JIntReload;
126 unsigned long long IBNCModeCtrl;
127 unsigned long long SendCtrl;
128 unsigned long long SendBufBase;
129 unsigned long long SendBufSize;
130 unsigned long long SendBufCnt;
131 unsigned long long SendAvailAddr;
132 unsigned long long TxIntMemBase;
133 unsigned long long TxIntMemSize;
134 unsigned long long SendDmaBase;
135 unsigned long long SendDmaLenGen;
136 unsigned long long SendDmaTail;
137 unsigned long long SendDmaHead;
138 unsigned long long SendDmaHeadAddr;
139 unsigned long long SendDmaBufMask0;
140 unsigned long long SendDmaBufMask1;
141 unsigned long long SendDmaBufMask2;
142 unsigned long long SendDmaStatus;
143 unsigned long long SendBufferError;
144 unsigned long long SendBufferErrorCONT1;
145 unsigned long long SendBufErr2; /* was Reserved6SBE[0/6] */
146 unsigned long long Reserved6L[2];
147 unsigned long long AvailUpdCount;
148 unsigned long long RcvHdrAddr0;
149 unsigned long long RcvHdrAddrs[16]; /* Why enumerate? */
150 unsigned long long Reserved7hdtl; /* Align next to 300 */
151 unsigned long long RcvHdrTailAddr0; /* 300, like others */
152 unsigned long long RcvHdrTailAddrs[16];
153 unsigned long long Reserved9SW[7]; /* was [8]; we have 17 ports */
154 unsigned long long IbsdEpbAccCtl; /* IB Serdes EPB access control */
155 unsigned long long IbsdEpbTransReg; /* IB Serdes EPB Transaction */
156 unsigned long long Reserved10sds; /* was SerdesStatus on */
157 unsigned long long XGXSConfig;
158 unsigned long long IBSerDesCtrl; /* Was IBPLLCfg on Monty */
159 unsigned long long EEPCtlStat; /* for "boot" EEPROM/FLASH */
160 unsigned long long EEPAddrCmd;
161 unsigned long long EEPData;
162 unsigned long long PcieEpbAccCtl;
163 unsigned long long PcieEpbTransCtl;
164 unsigned long long EfuseCtl; /* E-Fuse control */
165 unsigned long long EfuseData[4];
166 unsigned long long ProcMon;
167 /* this chip moves following two from previous 200, 208 */
168 unsigned long long PCIeRBufTestReg0;
169 unsigned long long PCIeRBufTestReg1;
170 /* added for this chip */
171 unsigned long long PCIeRBufTestReg2;
172 unsigned long long PCIeRBufTestReg3;
173 /* added for this chip, debug only */
174 unsigned long long SPC_JTAG_ACCESS_REG;
175 unsigned long long LAControlReg;
176 unsigned long long GPIODebugSelReg;
177 unsigned long long DebugPortValueReg;
178 /* added for this chip, DMA */
179 unsigned long long SendDmaBufUsed[3];
180 unsigned long long SendDmaReqTagUsed;
181 /*
182 * added for this chip, EFUSE: note that these program 64-bit
183 * words 2 and 3 */
184 unsigned long long efuse_pgm_data[2];
185 unsigned long long Reserved11LAalign[10]; /* Skip 4B0..4F8 */
186 /* we have 30 regs for DDS and RXEQ in IB SERDES */
187 unsigned long long SerDesDDSRXEQ[30];
188 unsigned long long Reserved12LAalign[2]; /* Skip 5F0, 5F8 */
189 /* added for LA debug support */
190 unsigned long long LAMemory[32];
191};
192
193struct _infinipath_do_not_use_counters {
194 __u64 LBIntCnt;
195 __u64 LBFlowStallCnt;
196 __u64 TxSDmaDescCnt; /* was Reserved1 */
197 __u64 TxUnsupVLErrCnt;
198 __u64 TxDataPktCnt;
199 __u64 TxFlowPktCnt;
200 __u64 TxDwordCnt;
201 __u64 TxLenErrCnt;
202 __u64 TxMaxMinLenErrCnt;
203 __u64 TxUnderrunCnt;
204 __u64 TxFlowStallCnt;
205 __u64 TxDroppedPktCnt;
206 __u64 RxDroppedPktCnt;
207 __u64 RxDataPktCnt;
208 __u64 RxFlowPktCnt;
209 __u64 RxDwordCnt;
210 __u64 RxLenErrCnt;
211 __u64 RxMaxMinLenErrCnt;
212 __u64 RxICRCErrCnt;
213 __u64 RxVCRCErrCnt;
214 __u64 RxFlowCtrlErrCnt;
215 __u64 RxBadFormatCnt;
216 __u64 RxLinkProblemCnt;
217 __u64 RxEBPCnt;
218 __u64 RxLPCRCErrCnt;
219 __u64 RxBufOvflCnt;
220 __u64 RxTIDFullErrCnt;
221 __u64 RxTIDValidErrCnt;
222 __u64 RxPKeyMismatchCnt;
223 __u64 RxP0HdrEgrOvflCnt;
224 __u64 RxP1HdrEgrOvflCnt;
225 __u64 RxP2HdrEgrOvflCnt;
226 __u64 RxP3HdrEgrOvflCnt;
227 __u64 RxP4HdrEgrOvflCnt;
228 __u64 RxP5HdrEgrOvflCnt;
229 __u64 RxP6HdrEgrOvflCnt;
230 __u64 RxP7HdrEgrOvflCnt;
231 __u64 RxP8HdrEgrOvflCnt;
232 __u64 RxP9HdrEgrOvflCnt; /* was Reserved6 */
233 __u64 RxP10HdrEgrOvflCnt; /* was Reserved7 */
234 __u64 RxP11HdrEgrOvflCnt; /* new for IBA7220 */
235 __u64 RxP12HdrEgrOvflCnt; /* new for IBA7220 */
236 __u64 RxP13HdrEgrOvflCnt; /* new for IBA7220 */
237 __u64 RxP14HdrEgrOvflCnt; /* new for IBA7220 */
238 __u64 RxP15HdrEgrOvflCnt; /* new for IBA7220 */
239 __u64 RxP16HdrEgrOvflCnt; /* new for IBA7220 */
240 __u64 IBStatusChangeCnt;
241 __u64 IBLinkErrRecoveryCnt;
242 __u64 IBLinkDownedCnt;
243 __u64 IBSymbolErrCnt;
244 /* The following are new for IBA7220 */
245 __u64 RxVL15DroppedPktCnt;
246 __u64 RxOtherLocalPhyErrCnt;
247 __u64 PcieRetryBufDiagQwordCnt;
248 __u64 ExcessBufferOvflCnt;
249 __u64 LocalLinkIntegrityErrCnt;
250 __u64 RxVlErrCnt;
251 __u64 RxDlidFltrCnt;
252 __u64 Reserved8[7];
253 __u64 PSStat;
254 __u64 PSStart;
255 __u64 PSInterval;
256 __u64 PSRcvDataCount;
257 __u64 PSRcvPktsCount;
258 __u64 PSXmitDataCount;
259 __u64 PSXmitPktsCount;
260 __u64 PSXmitWaitCount;
261};
262
263#define IPATH_KREG_OFFSET(field) (offsetof( \
264 struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
265#define IPATH_CREG_OFFSET(field) (offsetof( \
266 struct _infinipath_do_not_use_counters, field) / sizeof(u64))
267
268static const struct ipath_kregs ipath_7220_kregs = {
269 .kr_control = IPATH_KREG_OFFSET(Control),
270 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
271 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
272 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
273 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
274 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
275 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
276 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
277 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
278 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
279 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
280 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
281 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
282 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
283 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
284 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
285 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
286 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
287 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
288 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
289 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
290 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
291 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
292 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
293 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
294 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
295 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
296 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
297 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
298 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
299 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
300 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
301 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
302 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
303 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
304 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
305 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
306 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
307 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
308 .kr_revision = IPATH_KREG_OFFSET(Revision),
309 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
310 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
311 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
312 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendAvailAddr),
313 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendBufBase),
314 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendBufCnt),
315 .kr_sendpiosize = IPATH_KREG_OFFSET(SendBufSize),
316 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
317 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
318 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
319 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
320
321 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
322
323 /* send dma related regs */
324 .kr_senddmabase = IPATH_KREG_OFFSET(SendDmaBase),
325 .kr_senddmalengen = IPATH_KREG_OFFSET(SendDmaLenGen),
326 .kr_senddmatail = IPATH_KREG_OFFSET(SendDmaTail),
327 .kr_senddmahead = IPATH_KREG_OFFSET(SendDmaHead),
328 .kr_senddmaheadaddr = IPATH_KREG_OFFSET(SendDmaHeadAddr),
329 .kr_senddmabufmask0 = IPATH_KREG_OFFSET(SendDmaBufMask0),
330 .kr_senddmabufmask1 = IPATH_KREG_OFFSET(SendDmaBufMask1),
331 .kr_senddmabufmask2 = IPATH_KREG_OFFSET(SendDmaBufMask2),
332 .kr_senddmastatus = IPATH_KREG_OFFSET(SendDmaStatus),
333
334 /* SerDes related regs */
335 .kr_ibserdesctrl = IPATH_KREG_OFFSET(IBSerDesCtrl),
336 .kr_ib_epbacc = IPATH_KREG_OFFSET(IbsdEpbAccCtl),
337 .kr_ib_epbtrans = IPATH_KREG_OFFSET(IbsdEpbTransReg),
338 .kr_pcie_epbacc = IPATH_KREG_OFFSET(PcieEpbAccCtl),
339 .kr_pcie_epbtrans = IPATH_KREG_OFFSET(PcieEpbTransCtl),
340 .kr_ib_ddsrxeq = IPATH_KREG_OFFSET(SerDesDDSRXEQ),
341
342 /*
343 * These should not be used directly via ipath_read_kreg64(),
344 * use them with ipath_read_kreg64_port()
345 */
346 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
347 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
348
349 /*
350 * The rcvpktled register controls one of the debug port signals, so
351 * a packet activity LED can be connected to it.
352 */
353 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
354 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
355 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
356
357 .kr_hrtbt_guid = IPATH_KREG_OFFSET(HRTBT_GUID),
358 .kr_ibcddrctrl = IPATH_KREG_OFFSET(IBCDDRCtrl),
359 .kr_ibcddrstatus = IPATH_KREG_OFFSET(IBCDDRStatus),
360 .kr_jintreload = IPATH_KREG_OFFSET(JIntReload)
361};
362
363static const struct ipath_cregs ipath_7220_cregs = {
364 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
365 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
366 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
367 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
368 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
369 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
370 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
371 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
372 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
373 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
374 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
375 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
376 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
377 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
378 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
379 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
380 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
381 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
382 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
383 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
384 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
385 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
386 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
387 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
388 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
389 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
390 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
391 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
392 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
393 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
394 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
395 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
396 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt),
397 .cr_vl15droppedpktcnt = IPATH_CREG_OFFSET(RxVL15DroppedPktCnt),
398 .cr_rxotherlocalphyerrcnt =
399 IPATH_CREG_OFFSET(RxOtherLocalPhyErrCnt),
400 .cr_excessbufferovflcnt = IPATH_CREG_OFFSET(ExcessBufferOvflCnt),
401 .cr_locallinkintegrityerrcnt =
402 IPATH_CREG_OFFSET(LocalLinkIntegrityErrCnt),
403 .cr_rxvlerrcnt = IPATH_CREG_OFFSET(RxVlErrCnt),
404 .cr_rxdlidfltrcnt = IPATH_CREG_OFFSET(RxDlidFltrCnt),
405 .cr_psstat = IPATH_CREG_OFFSET(PSStat),
406 .cr_psstart = IPATH_CREG_OFFSET(PSStart),
407 .cr_psinterval = IPATH_CREG_OFFSET(PSInterval),
408 .cr_psrcvdatacount = IPATH_CREG_OFFSET(PSRcvDataCount),
409 .cr_psrcvpktscount = IPATH_CREG_OFFSET(PSRcvPktsCount),
410 .cr_psxmitdatacount = IPATH_CREG_OFFSET(PSXmitDataCount),
411 .cr_psxmitpktscount = IPATH_CREG_OFFSET(PSXmitPktsCount),
412 .cr_psxmitwaitcount = IPATH_CREG_OFFSET(PSXmitWaitCount),
413};
414
415/* kr_control bits */
416#define INFINIPATH_C_RESET (1U<<7)
417
418/* kr_intstatus, kr_intclear, kr_intmask bits */
419#define INFINIPATH_I_RCVURG_MASK ((1ULL<<17)-1)
420#define INFINIPATH_I_RCVURG_SHIFT 32
421#define INFINIPATH_I_RCVAVAIL_MASK ((1ULL<<17)-1)
422#define INFINIPATH_I_RCVAVAIL_SHIFT 0
423#define INFINIPATH_I_SERDESTRIMDONE (1ULL<<27)
424
425/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
426#define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x00000000000000ffULL
427#define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
428#define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
429#define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
430#define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
431#define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
432#define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
433#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
434#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
435#define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
436#define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
437#define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
438/* specific to this chip */
439#define INFINIPATH_HWE_PCIECPLDATAQUEUEERR 0x0000000000000040ULL
440#define INFINIPATH_HWE_PCIECPLHDRQUEUEERR 0x0000000000000080ULL
441#define INFINIPATH_HWE_SDMAMEMREADERR 0x0000000010000000ULL
442#define INFINIPATH_HWE_CLK_UC_PLLNOTLOCKED 0x2000000000000000ULL
443#define INFINIPATH_HWE_PCIESERDESQ0PCLKNOTDETECT 0x0100000000000000ULL
444#define INFINIPATH_HWE_PCIESERDESQ1PCLKNOTDETECT 0x0200000000000000ULL
445#define INFINIPATH_HWE_PCIESERDESQ2PCLKNOTDETECT 0x0400000000000000ULL
446#define INFINIPATH_HWE_PCIESERDESQ3PCLKNOTDETECT 0x0800000000000000ULL
447#define INFINIPATH_HWE_DDSRXEQMEMORYPARITYERR 0x0000008000000000ULL
448#define INFINIPATH_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
449#define INFINIPATH_HWE_PCIE_UC_OCT0MEMORYPARITYERR 0x0000001000000000ULL
450#define INFINIPATH_HWE_PCIE_UC_OCT1MEMORYPARITYERR 0x0000002000000000ULL
451
452#define IBA7220_IBCS_LINKTRAININGSTATE_MASK 0x1F
453#define IBA7220_IBCS_LINKSTATE_SHIFT 5
454#define IBA7220_IBCS_LINKSPEED_SHIFT 8
455#define IBA7220_IBCS_LINKWIDTH_SHIFT 9
456
457#define IBA7220_IBCC_LINKINITCMD_MASK 0x7ULL
458#define IBA7220_IBCC_LINKCMD_SHIFT 19
459#define IBA7220_IBCC_MAXPKTLEN_SHIFT 21
460
461/* kr_ibcddrctrl bits */
462#define IBA7220_IBC_DLIDLMC_MASK 0xFFFFFFFFUL
463#define IBA7220_IBC_DLIDLMC_SHIFT 32
464#define IBA7220_IBC_HRTBT_MASK 3
465#define IBA7220_IBC_HRTBT_SHIFT 16
466#define IBA7220_IBC_HRTBT_ENB 0x10000UL
467#define IBA7220_IBC_LANE_REV_SUPPORTED (1<<8)
468#define IBA7220_IBC_LREV_MASK 1
469#define IBA7220_IBC_LREV_SHIFT 8
470#define IBA7220_IBC_RXPOL_MASK 1
471#define IBA7220_IBC_RXPOL_SHIFT 7
472#define IBA7220_IBC_WIDTH_SHIFT 5
473#define IBA7220_IBC_WIDTH_MASK 0x3
474#define IBA7220_IBC_WIDTH_1X_ONLY (0<<IBA7220_IBC_WIDTH_SHIFT)
475#define IBA7220_IBC_WIDTH_4X_ONLY (1<<IBA7220_IBC_WIDTH_SHIFT)
476#define IBA7220_IBC_WIDTH_AUTONEG (2<<IBA7220_IBC_WIDTH_SHIFT)
477#define IBA7220_IBC_SPEED_AUTONEG (1<<1)
478#define IBA7220_IBC_SPEED_SDR (1<<2)
479#define IBA7220_IBC_SPEED_DDR (1<<3)
480#define IBA7220_IBC_SPEED_AUTONEG_MASK (0x7<<1)
481#define IBA7220_IBC_IBTA_1_2_MASK (1)
482
483/* kr_ibcddrstatus */
484/* link latency shift is 0, don't bother defining */
485#define IBA7220_DDRSTAT_LINKLAT_MASK 0x3ffffff
486
487/* kr_extstatus bits */
488#define INFINIPATH_EXTS_FREQSEL 0x2
489#define INFINIPATH_EXTS_SERDESSEL 0x4
490#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
491#define INFINIPATH_EXTS_MEMBIST_DISABLED 0x0000000000008000
492
493/* kr_xgxsconfig bits */
494#define INFINIPATH_XGXS_RESET 0x5ULL
495#define INFINIPATH_XGXS_FC_SAFE (1ULL<<63)
496
497/* kr_rcvpktledcnt */
498#define IBA7220_LEDBLINK_ON_SHIFT 32 /* 4ns period on after packet */
499#define IBA7220_LEDBLINK_OFF_SHIFT 0 /* 4ns period off before next on */
500
501#define _IPATH_GPIO_SDA_NUM 1
502#define _IPATH_GPIO_SCL_NUM 0
503
504#define IPATH_GPIO_SDA (1ULL << \
505 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
506#define IPATH_GPIO_SCL (1ULL << \
507 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
508
509#define IBA7220_R_INTRAVAIL_SHIFT 17
510#define IBA7220_R_TAILUPD_SHIFT 35
511#define IBA7220_R_PORTCFG_SHIFT 36
512
513#define INFINIPATH_JINT_PACKETSHIFT 16
514#define INFINIPATH_JINT_DEFAULT_IDLE_TICKS 0
515#define INFINIPATH_JINT_DEFAULT_MAX_PACKETS 0
516
517#define IBA7220_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
518
519/*
520 * the size bits give us 2^N, in KB units. 0 marks as invalid,
521 * and 7 is reserved. We currently use only 2KB and 4KB
522 */
523#define IBA7220_TID_SZ_SHIFT 37 /* shift to 3bit size selector */
524#define IBA7220_TID_SZ_2K (1UL<<IBA7220_TID_SZ_SHIFT) /* 2KB */
525#define IBA7220_TID_SZ_4K (2UL<<IBA7220_TID_SZ_SHIFT) /* 4KB */
526#define IBA7220_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
527
528#define IPATH_AUTONEG_TRIES 5 /* sequential retries to negotiate DDR */
529
530static char int_type[16] = "auto";
531module_param_string(interrupt_type, int_type, sizeof(int_type), 0444);
532MODULE_PARM_DESC(int_type, " interrupt_type=auto|force_msi|force_intx");
533
534/* packet rate matching delay; chip has support */
535static u8 rate_to_delay[2][2] = {
536 /* 1x, 4x */
537 { 8, 2 }, /* SDR */
538 { 4, 1 } /* DDR */
539};
540
541/* 7220 specific hardware errors... */
542static const struct ipath_hwerror_msgs ipath_7220_hwerror_msgs[] = {
543 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
544 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
545 /*
546 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
547 * parity or memory parity error failures, because most likely we
548 * won't be able to talk to the core of the chip. Nonetheless, we
549 * might see them, if they are in parts of the PCIe core that aren't
550 * essential.
551 */
552 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
553 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
554 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
555 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
556 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
557 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
558 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
559 INFINIPATH_HWE_MSG(PCIECPLDATAQUEUEERR, "PCIe cpl header queue"),
560 INFINIPATH_HWE_MSG(PCIECPLHDRQUEUEERR, "PCIe cpl data queue"),
561 INFINIPATH_HWE_MSG(SDMAMEMREADERR, "Send DMA memory read"),
562 INFINIPATH_HWE_MSG(CLK_UC_PLLNOTLOCKED, "uC PLL clock not locked"),
563 INFINIPATH_HWE_MSG(PCIESERDESQ0PCLKNOTDETECT,
564 "PCIe serdes Q0 no clock"),
565 INFINIPATH_HWE_MSG(PCIESERDESQ1PCLKNOTDETECT,
566 "PCIe serdes Q1 no clock"),
567 INFINIPATH_HWE_MSG(PCIESERDESQ2PCLKNOTDETECT,
568 "PCIe serdes Q2 no clock"),
569 INFINIPATH_HWE_MSG(PCIESERDESQ3PCLKNOTDETECT,
570 "PCIe serdes Q3 no clock"),
571 INFINIPATH_HWE_MSG(DDSRXEQMEMORYPARITYERR,
572 "DDS RXEQ memory parity"),
573 INFINIPATH_HWE_MSG(IB_UC_MEMORYPARITYERR, "IB uC memory parity"),
574 INFINIPATH_HWE_MSG(PCIE_UC_OCT0MEMORYPARITYERR,
575 "PCIe uC oct0 memory parity"),
576 INFINIPATH_HWE_MSG(PCIE_UC_OCT1MEMORYPARITYERR,
577 "PCIe uC oct1 memory parity"),
578};
579
580static void autoneg_work(struct work_struct *);
581
582/*
583 * the offset is different for different configured port numbers, since
584 * port0 is fixed in size, but others can vary. Make it a function to
585 * make the issue more obvious.
586*/
587static inline u32 port_egrtid_idx(struct ipath_devdata *dd, unsigned port)
588{
589 return port ? dd->ipath_p0_rcvegrcnt +
590 (port-1) * dd->ipath_rcvegrcnt : 0;
591}
592
593static void ipath_7220_txe_recover(struct ipath_devdata *dd)
594{
595 ++ipath_stats.sps_txeparity;
596
597 dev_info(&dd->pcidev->dev,
598 "Recovering from TXE PIO parity error\n");
599 ipath_disarm_senderrbufs(dd);
600}
601
602
603/**
604 * ipath_7220_handle_hwerrors - display hardware errors.
605 * @dd: the infinipath device
606 * @msg: the output buffer
607 * @msgl: the size of the output buffer
608 *
609 * Use same msg buffer as regular errors to avoid excessive stack
610 * use. Most hardware errors are catastrophic, but for right now,
611 * we'll print them and continue. We reuse the same message buffer as
612 * ipath_handle_errors() to avoid excessive stack usage.
613 */
614static void ipath_7220_handle_hwerrors(struct ipath_devdata *dd, char *msg,
615 size_t msgl)
616{
617 ipath_err_t hwerrs;
618 u32 bits, ctrl;
619 int isfatal = 0;
620 char bitsmsg[64];
621 int log_idx;
622
623 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
624 if (!hwerrs) {
625 /*
626 * better than printing cofusing messages
627 * This seems to be related to clearing the crc error, or
628 * the pll error during init.
629 */
630 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
631 goto bail;
632 } else if (hwerrs == ~0ULL) {
633 ipath_dev_err(dd, "Read of hardware error status failed "
634 "(all bits set); ignoring\n");
635 goto bail;
636 }
637 ipath_stats.sps_hwerrs++;
638
639 /*
640 * Always clear the error status register, except MEMBISTFAIL,
641 * regardless of whether we continue or stop using the chip.
642 * We want that set so we know it failed, even across driver reload.
643 * We'll still ignore it in the hwerrmask. We do this partly for
644 * diagnostics, but also for support.
645 */
646 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
647 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
648
649 hwerrs &= dd->ipath_hwerrmask;
650
651 /* We log some errors to EEPROM, check if we have any of those. */
652 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
653 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
654 ipath_inc_eeprom_err(dd, log_idx, 1);
655 /*
656 * Make sure we get this much out, unless told to be quiet,
657 * or it's occurred within the last 5 seconds.
658 */
659 if ((hwerrs & ~(dd->ipath_lasthwerror |
660 ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
661 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
662 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
663 (ipath_debug & __IPATH_VERBDBG))
664 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
665 "(cleared)\n", (unsigned long long) hwerrs);
666 dd->ipath_lasthwerror |= hwerrs;
667
668 if (hwerrs & ~dd->ipath_hwe_bitsextant)
669 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
670 "%llx set\n", (unsigned long long)
671 (hwerrs & ~dd->ipath_hwe_bitsextant));
672
673 if (hwerrs & INFINIPATH_HWE_IB_UC_MEMORYPARITYERR)
674 ipath_sd7220_clr_ibpar(dd);
675
676 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
677 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
678 /*
679 * Parity errors in send memory are recoverable by h/w
680 * just do housekeeping, exit freeze mode and continue.
681 */
682 if (hwerrs & ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
683 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
684 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
685 ipath_7220_txe_recover(dd);
686 hwerrs &= ~((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
687 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
688 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT);
689 }
690 if (hwerrs) {
691 /*
692 * If any set that we aren't ignoring only make the
693 * complaint once, in case it's stuck or recurring,
694 * and we get here multiple times
695 * Force link down, so switch knows, and
696 * LEDs are turned off.
697 */
698 if (dd->ipath_flags & IPATH_INITTED) {
699 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
700 ipath_setup_7220_setextled(dd,
701 INFINIPATH_IBCS_L_STATE_DOWN,
702 INFINIPATH_IBCS_LT_STATE_DISABLED);
703 ipath_dev_err(dd, "Fatal Hardware Error "
704 "(freeze mode), no longer"
705 " usable, SN %.16s\n",
706 dd->ipath_serial);
707 isfatal = 1;
708 }
709 /*
710 * Mark as having had an error for driver, and also
711 * for /sys and status word mapped to user programs.
712 * This marks unit as not usable, until reset.
713 */
714 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
715 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
716 dd->ipath_flags &= ~IPATH_INITTED;
717 } else {
718 ipath_dbg("Clearing freezemode on ignored or "
719 "recovered hardware error\n");
720 ipath_clear_freeze(dd);
721 }
722 }
723
724 *msg = '\0';
725
726 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
727 strlcat(msg, "[Memory BIST test failed, "
728 "InfiniPath hardware unusable]", msgl);
729 /* ignore from now on, so disable until driver reloaded */
730 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
731 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
732 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
733 dd->ipath_hwerrmask);
734 }
735
736 ipath_format_hwerrors(hwerrs,
737 ipath_7220_hwerror_msgs,
738 ARRAY_SIZE(ipath_7220_hwerror_msgs),
739 msg, msgl);
740
741 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
742 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
743 bits = (u32) ((hwerrs >>
744 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
745 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
746 snprintf(bitsmsg, sizeof bitsmsg,
747 "[PCIe Mem Parity Errs %x] ", bits);
748 strlcat(msg, bitsmsg, msgl);
749 }
750
751#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
752 INFINIPATH_HWE_COREPLL_RFSLIP)
753
754 if (hwerrs & _IPATH_PLL_FAIL) {
755 snprintf(bitsmsg, sizeof bitsmsg,
756 "[PLL failed (%llx), InfiniPath hardware unusable]",
757 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
758 strlcat(msg, bitsmsg, msgl);
759 /* ignore from now on, so disable until driver reloaded */
760 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
761 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
762 dd->ipath_hwerrmask);
763 }
764
765 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
766 /*
767 * If it occurs, it is left masked since the eternal
768 * interface is unused.
769 */
770 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
771 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
772 dd->ipath_hwerrmask);
773 }
774
775 ipath_dev_err(dd, "%s hardware error\n", msg);
776 /*
777 * For /sys status file. if no trailing } is copied, we'll
778 * know it was truncated.
779 */
780 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
781 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
782 "{%s}", msg);
783bail:;
784}
785
786/**
787 * ipath_7220_boardname - fill in the board name
788 * @dd: the infinipath device
789 * @name: the output buffer
790 * @namelen: the size of the output buffer
791 *
792 * info is based on the board revision register
793 */
794static int ipath_7220_boardname(struct ipath_devdata *dd, char *name,
795 size_t namelen)
796{
797 char *n = NULL;
798 u8 boardrev = dd->ipath_boardrev;
799 int ret;
800
801 if (boardrev == 15) {
802 /*
803 * Emulator sometimes comes up all-ones, rather than zero.
804 */
805 boardrev = 0;
806 dd->ipath_boardrev = boardrev;
807 }
808 switch (boardrev) {
809 case 0:
810 n = "InfiniPath_7220_Emulation";
811 break;
812 case 1:
813 n = "InfiniPath_QLE7240";
814 break;
815 case 2:
816 n = "InfiniPath_QLE7280";
817 break;
818 case 3:
819 n = "InfiniPath_QLE7242";
820 break;
821 case 4:
822 n = "InfiniPath_QEM7240";
823 break;
824 case 5:
825 n = "InfiniPath_QMI7240";
826 break;
827 case 6:
828 n = "InfiniPath_QMI7264";
829 break;
830 case 7:
831 n = "InfiniPath_QMH7240";
832 break;
833 case 8:
834 n = "InfiniPath_QME7240";
835 break;
836 case 9:
837 n = "InfiniPath_QLE7250";
838 break;
839 case 10:
840 n = "InfiniPath_QLE7290";
841 break;
842 case 11:
843 n = "InfiniPath_QEM7250";
844 break;
845 case 12:
846 n = "InfiniPath_QLE-Bringup";
847 break;
848 default:
849 ipath_dev_err(dd,
850 "Don't yet know about board with ID %u\n",
851 boardrev);
852 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
853 boardrev);
854 break;
855 }
856 if (n)
857 snprintf(name, namelen, "%s", n);
858
859 if (dd->ipath_majrev != 5 || !dd->ipath_minrev ||
860 dd->ipath_minrev > 2) {
861 ipath_dev_err(dd, "Unsupported InfiniPath hardware "
862 "revision %u.%u!\n",
863 dd->ipath_majrev, dd->ipath_minrev);
864 ret = 1;
865 } else if (dd->ipath_minrev == 1 &&
866 !(dd->ipath_flags & IPATH_INITTED)) {
867 /* Rev1 chips are prototype. Complain at init, but allow use */
868 ipath_dev_err(dd, "Unsupported hardware "
869 "revision %u.%u, Contact support@qlogic.com\n",
870 dd->ipath_majrev, dd->ipath_minrev);
871 ret = 0;
872 } else
873 ret = 0;
874
875 /*
876 * Set here not in ipath_init_*_funcs because we have to do
877 * it after we can read chip registers.
878 */
879 dd->ipath_ureg_align = 0x10000; /* 64KB alignment */
880
881 return ret;
882}
883
884/**
885 * ipath_7220_init_hwerrors - enable hardware errors
886 * @dd: the infinipath device
887 *
888 * now that we have finished initializing everything that might reasonably
889 * cause a hardware error, and cleared those errors bits as they occur,
890 * we can enable hardware errors in the mask (potentially enabling
891 * freeze mode), and enable hardware errors as errors (along with
892 * everything else) in errormask
893 */
894static void ipath_7220_init_hwerrors(struct ipath_devdata *dd)
895{
896 ipath_err_t val;
897 u64 extsval;
898
899 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
900
901 if (!(extsval & (INFINIPATH_EXTS_MEMBIST_ENDTEST |
902 INFINIPATH_EXTS_MEMBIST_DISABLED)))
903 ipath_dev_err(dd, "MemBIST did not complete!\n");
904 if (extsval & INFINIPATH_EXTS_MEMBIST_DISABLED)
905 dev_info(&dd->pcidev->dev, "MemBIST is disabled.\n");
906
907 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
908
909 if (!dd->ipath_boardrev) /* no PLL for Emulator */
910 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
911
912 if (dd->ipath_minrev == 1)
913 val &= ~(1ULL << 42); /* TXE LaunchFIFO Parity rev1 issue */
914
915 val &= ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR;
916 dd->ipath_hwerrmask = val;
917
918 /*
919 * special trigger "error" is for debugging purposes. It
920 * works around a processor/chipset problem. The error
921 * interrupt allows us to count occurrences, but we don't
922 * want to pay the overhead for normal use. Emulation only
923 */
924 if (!dd->ipath_boardrev)
925 dd->ipath_maskederrs = INFINIPATH_E_SENDSPECIALTRIGGER;
926}
927
928/*
929 * All detailed interaction with the SerDes has been moved to ipath_sd7220.c
930 *
931 * The portion of IBA7220-specific bringup_serdes() that actually deals with
932 * registers and memory within the SerDes itself is ipath_sd7220_init().
933 */
934
935/**
936 * ipath_7220_bringup_serdes - bring up the serdes
937 * @dd: the infinipath device
938 */
939static int ipath_7220_bringup_serdes(struct ipath_devdata *dd)
940{
941 int ret = 0;
942 u64 val, prev_val, guid;
943 int was_reset; /* Note whether uC was reset */
944
945 ipath_dbg("Trying to bringup serdes\n");
946
947 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
948 INFINIPATH_HWE_SERDESPLLFAILED) {
949 ipath_dbg("At start, serdes PLL failed bit set "
950 "in hwerrstatus, clearing and continuing\n");
951 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
952 INFINIPATH_HWE_SERDESPLLFAILED);
953 }
954
955 dd->ibdeltainprog = 1;
956 dd->ibsymsnap =
957 ipath_read_creg32(dd, dd->ipath_cregs->cr_ibsymbolerrcnt);
958 dd->iblnkerrsnap =
959 ipath_read_creg32(dd, dd->ipath_cregs->cr_iblinkerrrecovcnt);
960
961 if (!dd->ipath_ibcddrctrl) {
962 /* not on re-init after reset */
963 dd->ipath_ibcddrctrl =
964 ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcddrctrl);
965
966 if (dd->ipath_link_speed_enabled ==
967 (IPATH_IB_SDR | IPATH_IB_DDR))
968 dd->ipath_ibcddrctrl |=
969 IBA7220_IBC_SPEED_AUTONEG_MASK |
970 IBA7220_IBC_IBTA_1_2_MASK;
971 else
972 dd->ipath_ibcddrctrl |=
973 dd->ipath_link_speed_enabled == IPATH_IB_DDR
974 ? IBA7220_IBC_SPEED_DDR :
975 IBA7220_IBC_SPEED_SDR;
976 if ((dd->ipath_link_width_enabled & (IB_WIDTH_1X |
977 IB_WIDTH_4X)) == (IB_WIDTH_1X | IB_WIDTH_4X))
978 dd->ipath_ibcddrctrl |= IBA7220_IBC_WIDTH_AUTONEG;
979 else
980 dd->ipath_ibcddrctrl |=
981 dd->ipath_link_width_enabled == IB_WIDTH_4X
982 ? IBA7220_IBC_WIDTH_4X_ONLY :
983 IBA7220_IBC_WIDTH_1X_ONLY;
984
985 /* always enable these on driver reload, not sticky */
986 dd->ipath_ibcddrctrl |=
987 IBA7220_IBC_RXPOL_MASK << IBA7220_IBC_RXPOL_SHIFT;
988 dd->ipath_ibcddrctrl |=
989 IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
990 /*
991 * automatic lane reversal detection for receive
992 * doesn't work correctly in rev 1, so disable it
993 * on that rev, otherwise enable (disabling not
994 * sticky across reload for >rev1)
995 */
996 if (dd->ipath_minrev == 1)
997 dd->ipath_ibcddrctrl &=
998 ~IBA7220_IBC_LANE_REV_SUPPORTED;
999 else
1000 dd->ipath_ibcddrctrl |=
1001 IBA7220_IBC_LANE_REV_SUPPORTED;
1002 }
1003
1004 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
1005 dd->ipath_ibcddrctrl);
1006
1007 ipath_write_kreg(dd, IPATH_KREG_OFFSET(IBNCModeCtrl), 0Ull);
1008
1009 /* IBA7220 has SERDES MPU reset in D0 of what _was_ IBPLLCfg */
1010 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibserdesctrl);
1011 /* remember if uC was in Reset or not, for dactrim */
1012 was_reset = (val & 1);
1013 ipath_cdbg(VERBOSE, "IBReset %s xgxsconfig %llx\n",
1014 was_reset ? "Asserted" : "Negated", (unsigned long long)
1015 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1016
1017 if (dd->ipath_boardrev) {
1018 /*
1019 * Hardware is not emulator, and may have been reset. Init it.
1020 * Below will release reset, but needs to know if chip was
1021 * originally in reset, to only trim DACs on first time
1022 * after chip reset or powercycle (not driver reload)
1023 */
1024 ret = ipath_sd7220_init(dd, was_reset);
1025 }
1026
1027 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1028 prev_val = val;
1029 val |= INFINIPATH_XGXS_FC_SAFE;
1030 if (val != prev_val) {
1031 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1032 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1033 }
1034 if (val & INFINIPATH_XGXS_RESET)
1035 val &= ~INFINIPATH_XGXS_RESET;
1036 if (val != prev_val)
1037 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1038
1039 ipath_cdbg(VERBOSE, "done: xgxs=%llx from %llx\n",
1040 (unsigned long long)
1041 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig),
1042 (unsigned long long) prev_val);
1043
1044 guid = be64_to_cpu(dd->ipath_guid);
1045
1046 if (!guid) {
1047 /* have to have something, so use likely unique tsc */
1048 guid = get_cycles();
1049 ipath_dbg("No GUID for heartbeat, faking %llx\n",
1050 (unsigned long long)guid);
1051 } else
1052 ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n",
1053 (unsigned long long) guid);
1054 ipath_write_kreg(dd, dd->ipath_kregs->kr_hrtbt_guid, guid);
1055 return ret;
1056}
1057
1058static void ipath_7220_config_jint(struct ipath_devdata *dd,
1059 u16 idle_ticks, u16 max_packets)
1060{
1061
1062 /*
1063 * We can request a receive interrupt for 1 or more packets
1064 * from current offset.
1065 */
1066 if (idle_ticks == 0 || max_packets == 0)
1067 /* interrupt after one packet if no mitigation */
1068 dd->ipath_rhdrhead_intr_off =
1069 1ULL << IBA7220_HDRHEAD_PKTINT_SHIFT;
1070 else
1071 /* Turn off RcvHdrHead interrupts if using mitigation */
1072 dd->ipath_rhdrhead_intr_off = 0ULL;
1073
1074 /* refresh kernel RcvHdrHead registers... */
1075 ipath_write_ureg(dd, ur_rcvhdrhead,
1076 dd->ipath_rhdrhead_intr_off |
1077 dd->ipath_pd[0]->port_head, 0);
1078
1079 dd->ipath_jint_max_packets = max_packets;
1080 dd->ipath_jint_idle_ticks = idle_ticks;
1081 ipath_write_kreg(dd, dd->ipath_kregs->kr_jintreload,
1082 ((u64) max_packets << INFINIPATH_JINT_PACKETSHIFT) |
1083 idle_ticks);
1084}
1085
1086/**
1087 * ipath_7220_quiet_serdes - set serdes to txidle
1088 * @dd: the infinipath device
1089 * Called when driver is being unloaded
1090 */
1091static void ipath_7220_quiet_serdes(struct ipath_devdata *dd)
1092{
1093 u64 val;
1094 if (dd->ibsymdelta || dd->iblnkerrdelta ||
1095 dd->ibdeltainprog) {
1096 u64 diagc;
1097 /* enable counter writes */
1098 diagc = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwdiagctrl);
1099 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwdiagctrl,
1100 diagc | INFINIPATH_DC_COUNTERWREN);
1101
1102 if (dd->ibsymdelta || dd->ibdeltainprog) {
1103 val = ipath_read_creg32(dd,
1104 dd->ipath_cregs->cr_ibsymbolerrcnt);
1105 if (dd->ibdeltainprog)
1106 val -= val - dd->ibsymsnap;
1107 val -= dd->ibsymdelta;
1108 ipath_write_creg(dd,
1109 dd->ipath_cregs->cr_ibsymbolerrcnt, val);
1110 }
1111 if (dd->iblnkerrdelta || dd->ibdeltainprog) {
1112 val = ipath_read_creg32(dd,
1113 dd->ipath_cregs->cr_iblinkerrrecovcnt);
1114 if (dd->ibdeltainprog)
1115 val -= val - dd->iblnkerrsnap;
1116 val -= dd->iblnkerrdelta;
1117 ipath_write_creg(dd,
1118 dd->ipath_cregs->cr_iblinkerrrecovcnt, val);
1119 }
1120
1121 /* and disable counter writes */
1122 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwdiagctrl, diagc);
1123 }
1124
1125 dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
1126 wake_up(&dd->ipath_autoneg_wait);
1127 cancel_delayed_work(&dd->ipath_autoneg_work);
1128 flush_scheduled_work();
1129 ipath_shutdown_relock_poll(dd);
1130 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1131 val |= INFINIPATH_XGXS_RESET;
1132 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1133}
1134
1135static int ipath_7220_intconfig(struct ipath_devdata *dd)
1136{
1137 ipath_7220_config_jint(dd, dd->ipath_jint_idle_ticks,
1138 dd->ipath_jint_max_packets);
1139 return 0;
1140}
1141
1142/**
1143 * ipath_setup_7220_setextled - set the state of the two external LEDs
1144 * @dd: the infinipath device
1145 * @lst: the L state
1146 * @ltst: the LT state
1147 *
1148 * These LEDs indicate the physical and logical state of IB link.
1149 * For this chip (at least with recommended board pinouts), LED1
1150 * is Yellow (logical state) and LED2 is Green (physical state),
1151 *
1152 * Note: We try to match the Mellanox HCA LED behavior as best
1153 * we can. Green indicates physical link state is OK (something is
1154 * plugged in, and we can train).
1155 * Amber indicates the link is logically up (ACTIVE).
1156 * Mellanox further blinks the amber LED to indicate data packet
1157 * activity, but we have no hardware support for that, so it would
1158 * require waking up every 10-20 msecs and checking the counters
1159 * on the chip, and then turning the LED off if appropriate. That's
1160 * visible overhead, so not something we will do.
1161 *
1162 */
1163static void ipath_setup_7220_setextled(struct ipath_devdata *dd, u64 lst,
1164 u64 ltst)
1165{
1166 u64 extctl, ledblink = 0;
1167 unsigned long flags = 0;
1168
1169 /* the diags use the LED to indicate diag info, so we leave
1170 * the external LED alone when the diags are running */
1171 if (ipath_diag_inuse)
1172 return;
1173
1174 /* Allow override of LED display for, e.g. Locating system in rack */
1175 if (dd->ipath_led_override) {
1176 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1177 ? INFINIPATH_IBCS_LT_STATE_LINKUP
1178 : INFINIPATH_IBCS_LT_STATE_DISABLED;
1179 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1180 ? INFINIPATH_IBCS_L_STATE_ACTIVE
1181 : INFINIPATH_IBCS_L_STATE_DOWN;
1182 }
1183
1184 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1185 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1186 INFINIPATH_EXTC_LED2PRIPORT_ON);
1187 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP) {
1188 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1189 /*
1190 * counts are in chip clock (4ns) periods.
1191 * This is 1/16 sec (66.6ms) on,
1192 * 3/16 sec (187.5 ms) off, with packets rcvd
1193 */
1194 ledblink = ((66600*1000UL/4) << IBA7220_LEDBLINK_ON_SHIFT)
1195 | ((187500*1000UL/4) << IBA7220_LEDBLINK_OFF_SHIFT);
1196 }
1197 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1198 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1199 dd->ipath_extctrl = extctl;
1200 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1201 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1202
1203 if (ledblink) /* blink the LED on packet receive */
1204 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvpktledcnt,
1205 ledblink);
1206}
1207
1208/*
1209 * Similar to pci_intx(pdev, 1), except that we make sure
1210 * msi is off...
1211 */
1212static void ipath_enable_intx(struct pci_dev *pdev)
1213{
1214 u16 cw, new;
1215 int pos;
1216
1217 /* first, turn on INTx */
1218 pci_read_config_word(pdev, PCI_COMMAND, &cw);
1219 new = cw & ~PCI_COMMAND_INTX_DISABLE;
1220 if (new != cw)
1221 pci_write_config_word(pdev, PCI_COMMAND, new);
1222
1223 /* then turn off MSI */
1224 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1225 if (pos) {
1226 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
1227 new = cw & ~PCI_MSI_FLAGS_ENABLE;
1228 if (new != cw)
1229 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new);
1230 }
1231}
1232
1233static int ipath_msi_enabled(struct pci_dev *pdev)
1234{
1235 int pos, ret = 0;
1236
1237 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1238 if (pos) {
1239 u16 cw;
1240
1241 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
1242 ret = !!(cw & PCI_MSI_FLAGS_ENABLE);
1243 }
1244 return ret;
1245}
1246
1247/*
1248 * disable msi interrupt if enabled, and clear the flag.
1249 * flag is used primarily for the fallback to INTx, but
1250 * is also used in reinit after reset as a flag.
1251 */
1252static void ipath_7220_nomsi(struct ipath_devdata *dd)
1253{
1254 dd->ipath_msi_lo = 0;
1255
1256 if (ipath_msi_enabled(dd->pcidev)) {
1257 /*
1258 * free, but don't zero; later kernels require
1259 * it be freed before disable_msi, so the intx
1260 * setup has to request it again.
1261 */
1262 if (dd->ipath_irq)
1263 free_irq(dd->ipath_irq, dd);
1264 pci_disable_msi(dd->pcidev);
1265 }
1266}
1267
1268/*
1269 * ipath_setup_7220_cleanup - clean up any per-chip chip-specific stuff
1270 * @dd: the infinipath device
1271 *
1272 * Nothing but msi interrupt cleanup for now.
1273 *
1274 * This is called during driver unload.
1275 */
1276static void ipath_setup_7220_cleanup(struct ipath_devdata *dd)
1277{
1278 ipath_7220_nomsi(dd);
1279}
1280
1281
1282static void ipath_7220_pcie_params(struct ipath_devdata *dd, u32 boardrev)
1283{
1284 u16 linkstat, minwidth, speed;
1285 int pos;
1286
1287 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP);
1288 if (!pos) {
1289 ipath_dev_err(dd, "Can't find PCI Express capability!\n");
1290 goto bail;
1291 }
1292
1293 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
1294 &linkstat);
1295 /*
1296 * speed is bits 0-4, linkwidth is bits 4-8
1297 * no defines for them in headers
1298 */
1299 speed = linkstat & 0xf;
1300 linkstat >>= 4;
1301 linkstat &= 0x1f;
1302 dd->ipath_lbus_width = linkstat;
1303 switch (boardrev) {
1304 case 0:
1305 case 2:
1306 case 10:
1307 case 12:
1308 minwidth = 16; /* x16 capable boards */
1309 break;
1310 default:
1311 minwidth = 8; /* x8 capable boards */
1312 break;
1313 }
1314
1315 switch (speed) {
1316 case 1:
1317 dd->ipath_lbus_speed = 2500; /* Gen1, 2.5GHz */
1318 break;
1319 case 2:
1320 dd->ipath_lbus_speed = 5000; /* Gen1, 5GHz */
1321 break;
1322 default: /* not defined, assume gen1 */
1323 dd->ipath_lbus_speed = 2500;
1324 break;
1325 }
1326
1327 if (linkstat < minwidth)
1328 ipath_dev_err(dd,
1329 "PCIe width %u (x%u HCA), performance "
1330 "reduced\n", linkstat, minwidth);
1331 else
1332 ipath_cdbg(VERBOSE, "PCIe speed %u width %u (x%u HCA)\n",
1333 dd->ipath_lbus_speed, linkstat, minwidth);
1334
1335 if (speed != 1)
1336 ipath_dev_err(dd,
1337 "PCIe linkspeed %u is incorrect; "
1338 "should be 1 (2500)!\n", speed);
1339
1340bail:
1341 /* fill in string, even on errors */
1342 snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
1343 "PCIe,%uMHz,x%u\n",
1344 dd->ipath_lbus_speed,
1345 dd->ipath_lbus_width);
1346 return;
1347}
1348
1349
1350/**
1351 * ipath_setup_7220_config - setup PCIe config related stuff
1352 * @dd: the infinipath device
1353 * @pdev: the PCI device
1354 *
1355 * The pci_enable_msi() call will fail on systems with MSI quirks
1356 * such as those with AMD8131, even if the device of interest is not
1357 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
1358 * late in 2.6.16).
1359 * All that can be done is to edit the kernel source to remove the quirk
1360 * check until that is fixed.
1361 * We do not need to call enable_msi() for our HyperTransport chip,
1362 * even though it uses MSI, and we want to avoid the quirk warning, so
1363 * So we call enable_msi only for PCIe. If we do end up needing
1364 * pci_enable_msi at some point in the future for HT, we'll move the
1365 * call back into the main init_one code.
1366 * We save the msi lo and hi values, so we can restore them after
1367 * chip reset (the kernel PCI infrastructure doesn't yet handle that
1368 * correctly).
1369 */
1370static int ipath_setup_7220_config(struct ipath_devdata *dd,
1371 struct pci_dev *pdev)
1372{
1373 int pos, ret = -1;
1374 u32 boardrev;
1375
1376 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
1377
1378 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1379 if (!strcmp(int_type, "force_msi") || !strcmp(int_type, "auto"))
1380 ret = pci_enable_msi(pdev);
1381 if (ret) {
1382 if (!strcmp(int_type, "force_msi")) {
1383 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1384 "force_msi is on, so not continuing.\n",
1385 ret);
1386 return ret;
1387 }
1388
1389 ipath_enable_intx(pdev);
1390 if (!strcmp(int_type, "auto"))
1391 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1392 "falling back to INTx\n", ret);
1393 } else if (pos) {
1394 u16 control;
1395 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO,
1396 &dd->ipath_msi_lo);
1397 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI,
1398 &dd->ipath_msi_hi);
1399 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS,
1400 &control);
1401 /* now save the data (vector) info */
1402 pci_read_config_word(pdev,
1403 pos + ((control & PCI_MSI_FLAGS_64BIT)
1404 ? PCI_MSI_DATA_64 :
1405 PCI_MSI_DATA_32),
1406 &dd->ipath_msi_data);
1407 } else
1408 ipath_dev_err(dd, "Can't find MSI capability, "
1409 "can't save MSI settings for reset\n");
1410
1411 dd->ipath_irq = pdev->irq;
1412
1413 /*
1414 * We save the cachelinesize also, although it doesn't
1415 * really matter.
1416 */
1417 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1418 &dd->ipath_pci_cacheline);
1419
1420 /*
1421 * this function called early, ipath_boardrev not set yet. Can't
1422 * use ipath_read_kreg64() yet, too early in init, so use readq()
1423 */
1424 boardrev = (readq(&dd->ipath_kregbase[dd->ipath_kregs->kr_revision])
1425 >> INFINIPATH_R_BOARDID_SHIFT) & INFINIPATH_R_BOARDID_MASK;
1426
1427 ipath_7220_pcie_params(dd, boardrev);
1428
1429 dd->ipath_flags |= IPATH_NODMA_RTAIL | IPATH_HAS_SEND_DMA |
1430 IPATH_HAS_PBC_CNT | IPATH_HAS_THRESH_UPDATE;
1431 dd->ipath_pioupd_thresh = 4U; /* set default update threshold */
1432 return 0;
1433}
1434
1435static void ipath_init_7220_variables(struct ipath_devdata *dd)
1436{
1437 /*
1438 * setup the register offsets, since they are different for each
1439 * chip
1440 */
1441 dd->ipath_kregs = &ipath_7220_kregs;
1442 dd->ipath_cregs = &ipath_7220_cregs;
1443
1444 /*
1445 * bits for selecting i2c direction and values,
1446 * used for I2C serial flash
1447 */
1448 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1449 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1450 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1451 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1452
1453 /*
1454 * Fill in data for field-values that change in IBA7220.
1455 * We dynamically specify only the mask for LINKTRAININGSTATE
1456 * and only the shift for LINKSTATE, as they are the only ones
1457 * that change. Also precalculate the 3 link states of interest
1458 * and the combined mask.
1459 */
1460 dd->ibcs_ls_shift = IBA7220_IBCS_LINKSTATE_SHIFT;
1461 dd->ibcs_lts_mask = IBA7220_IBCS_LINKTRAININGSTATE_MASK;
1462 dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1463 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1464 dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1465 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1466 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1467 dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1468 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1469 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1470 dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1471 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1472 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1473
1474 /*
1475 * Fill in data for ibcc field-values that change in IBA7220.
1476 * We dynamically specify only the mask for LINKINITCMD
1477 * and only the shift for LINKCMD and MAXPKTLEN, as they are
1478 * the only ones that change.
1479 */
1480 dd->ibcc_lic_mask = IBA7220_IBCC_LINKINITCMD_MASK;
1481 dd->ibcc_lc_shift = IBA7220_IBCC_LINKCMD_SHIFT;
1482 dd->ibcc_mpl_shift = IBA7220_IBCC_MAXPKTLEN_SHIFT;
1483
1484 /* Fill in shifts for RcvCtrl. */
1485 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1486 dd->ipath_r_intravail_shift = IBA7220_R_INTRAVAIL_SHIFT;
1487 dd->ipath_r_tailupd_shift = IBA7220_R_TAILUPD_SHIFT;
1488 dd->ipath_r_portcfg_shift = IBA7220_R_PORTCFG_SHIFT;
1489
1490 /* variables for sanity checking interrupt and errors */
1491 dd->ipath_hwe_bitsextant =
1492 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1493 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1494 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1495 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1496 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
1497 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
1498 INFINIPATH_HWE_PCIE1PLLFAILED |
1499 INFINIPATH_HWE_PCIE0PLLFAILED |
1500 INFINIPATH_HWE_PCIEPOISONEDTLP |
1501 INFINIPATH_HWE_PCIECPLTIMEOUT |
1502 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
1503 INFINIPATH_HWE_PCIEBUSPARITYXADM |
1504 INFINIPATH_HWE_PCIEBUSPARITYRADM |
1505 INFINIPATH_HWE_MEMBISTFAILED |
1506 INFINIPATH_HWE_COREPLL_FBSLIP |
1507 INFINIPATH_HWE_COREPLL_RFSLIP |
1508 INFINIPATH_HWE_SERDESPLLFAILED |
1509 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1510 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR |
1511 INFINIPATH_HWE_PCIECPLDATAQUEUEERR |
1512 INFINIPATH_HWE_PCIECPLHDRQUEUEERR |
1513 INFINIPATH_HWE_SDMAMEMREADERR |
1514 INFINIPATH_HWE_CLK_UC_PLLNOTLOCKED |
1515 INFINIPATH_HWE_PCIESERDESQ0PCLKNOTDETECT |
1516 INFINIPATH_HWE_PCIESERDESQ1PCLKNOTDETECT |
1517 INFINIPATH_HWE_PCIESERDESQ2PCLKNOTDETECT |
1518 INFINIPATH_HWE_PCIESERDESQ3PCLKNOTDETECT |
1519 INFINIPATH_HWE_DDSRXEQMEMORYPARITYERR |
1520 INFINIPATH_HWE_IB_UC_MEMORYPARITYERR |
1521 INFINIPATH_HWE_PCIE_UC_OCT0MEMORYPARITYERR |
1522 INFINIPATH_HWE_PCIE_UC_OCT1MEMORYPARITYERR;
1523 dd->ipath_i_bitsextant =
1524 INFINIPATH_I_SDMAINT | INFINIPATH_I_SDMADISABLED |
1525 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1526 (INFINIPATH_I_RCVAVAIL_MASK <<
1527 INFINIPATH_I_RCVAVAIL_SHIFT) |
1528 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1529 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO |
1530 INFINIPATH_I_JINT | INFINIPATH_I_SERDESTRIMDONE;
1531 dd->ipath_e_bitsextant =
1532 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1533 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1534 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1535 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1536 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1537 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1538 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1539 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1540 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1541 INFINIPATH_E_SENDSPECIALTRIGGER |
1542 INFINIPATH_E_SDMADISABLED | INFINIPATH_E_SMINPKTLEN |
1543 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNDERRUN |
1544 INFINIPATH_E_SPKTLEN | INFINIPATH_E_SDROPPEDSMPPKT |
1545 INFINIPATH_E_SDROPPEDDATAPKT |
1546 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1547 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_SENDBUFMISUSE |
1548 INFINIPATH_E_SDMAGENMISMATCH | INFINIPATH_E_SDMAOUTOFBOUND |
1549 INFINIPATH_E_SDMATAILOUTOFBOUND | INFINIPATH_E_SDMABASE |
1550 INFINIPATH_E_SDMA1STDESC | INFINIPATH_E_SDMARPYTAG |
1551 INFINIPATH_E_SDMADWEN | INFINIPATH_E_SDMAMISSINGDW |
1552 INFINIPATH_E_SDMAUNEXPDATA |
1553 INFINIPATH_E_IBSTATUSCHANGED | INFINIPATH_E_INVALIDADDR |
1554 INFINIPATH_E_RESET | INFINIPATH_E_HARDWARE |
1555 INFINIPATH_E_SDMADESCADDRMISALIGN |
1556 INFINIPATH_E_INVALIDEEPCMD;
1557
1558 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1559 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1560 dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1561 dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1562 dd->ipath_flags |= IPATH_INTREG_64 | IPATH_HAS_MULT_IB_SPEED
1563 | IPATH_HAS_LINK_LATENCY;
1564
1565 /*
1566 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1567 * 2 is Some Misc, 3 is reserved for future.
1568 */
1569 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1570 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1571 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1572
1573 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1574 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1575 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1576
1577 dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1578
1579 ipath_linkrecovery = 0;
1580
1581 init_waitqueue_head(&dd->ipath_autoneg_wait);
1582 INIT_DELAYED_WORK(&dd->ipath_autoneg_work, autoneg_work);
1583
1584 dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1585 dd->ipath_link_speed_supported = IPATH_IB_SDR | IPATH_IB_DDR;
1586
1587 dd->ipath_link_width_enabled = dd->ipath_link_width_supported;
1588 dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1589 /*
1590 * set the initial values to reasonable default, will be set
1591 * for real when link is up.
1592 */
1593 dd->ipath_link_width_active = IB_WIDTH_4X;
1594 dd->ipath_link_speed_active = IPATH_IB_SDR;
1595 dd->delay_mult = rate_to_delay[0][1];
1596}
1597
1598
1599/*
1600 * Setup the MSI stuff again after a reset. I'd like to just call
1601 * pci_enable_msi() and request_irq() again, but when I do that,
1602 * the MSI enable bit doesn't get set in the command word, and
1603 * we switch to to a different interrupt vector, which is confusing,
1604 * so I instead just do it all inline. Perhaps somehow can tie this
1605 * into the PCIe hotplug support at some point
1606 * Note, because I'm doing it all here, I don't call pci_disable_msi()
1607 * or free_irq() at the start of ipath_setup_7220_reset().
1608 */
1609static int ipath_reinit_msi(struct ipath_devdata *dd)
1610{
1611 int ret = 0;
1612
1613 int pos;
1614 u16 control;
1615 if (!dd->ipath_msi_lo) /* Using intX, or init problem */
1616 goto bail;
1617
1618 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
1619 if (!pos) {
1620 ipath_dev_err(dd, "Can't find MSI capability, "
1621 "can't restore MSI settings\n");
1622 goto bail;
1623 }
1624 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1625 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1626 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1627 dd->ipath_msi_lo);
1628 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1629 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1630 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1631 dd->ipath_msi_hi);
1632 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1633 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1634 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1635 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1636 control, control | PCI_MSI_FLAGS_ENABLE);
1637 control |= PCI_MSI_FLAGS_ENABLE;
1638 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1639 control);
1640 }
1641 /* now rewrite the data (vector) info */
1642 pci_write_config_word(dd->pcidev, pos +
1643 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1644 dd->ipath_msi_data);
1645 ret = 1;
1646
1647bail:
1648 if (!ret) {
1649 ipath_dbg("Using INTx, MSI disabled or not configured\n");
1650 ipath_enable_intx(dd->pcidev);
1651 ret = 1;
1652 }
1653 /*
1654 * We restore the cachelinesize also, although it doesn't really
1655 * matter.
1656 */
1657 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1658 dd->ipath_pci_cacheline);
1659 /* and now set the pci master bit again */
1660 pci_set_master(dd->pcidev);
1661
1662 return ret;
1663}
1664
1665/*
1666 * This routine sleeps, so it can only be called from user context, not
1667 * from interrupt context. If we need interrupt context, we can split
1668 * it into two routines.
1669 */
1670static int ipath_setup_7220_reset(struct ipath_devdata *dd)
1671{
1672 u64 val;
1673 int i;
1674 int ret;
1675 u16 cmdval;
1676
1677 pci_read_config_word(dd->pcidev, PCI_COMMAND, &cmdval);
1678
1679 /* Use dev_err so it shows up in logs, etc. */
1680 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1681
1682 /* keep chip from being accessed in a few places */
1683 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_PRESENT);
1684 val = dd->ipath_control | INFINIPATH_C_RESET;
1685 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1686 mb();
1687
1688 for (i = 1; i <= 5; i++) {
1689 int r;
1690
1691 /*
1692 * Allow MBIST, etc. to complete; longer on each retry.
1693 * We sometimes get machine checks from bus timeout if no
1694 * response, so for now, make it *really* long.
1695 */
1696 msleep(1000 + (1 + i) * 2000);
1697 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1698 dd->ipath_pcibar0);
1699 if (r)
1700 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
1701 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1702 dd->ipath_pcibar1);
1703 if (r)
1704 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
1705 /* now re-enable memory access */
1706 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmdval);
1707 r = pci_enable_device(dd->pcidev);
1708 if (r)
1709 ipath_dev_err(dd, "pci_enable_device failed after "
1710 "reset: %d\n", r);
1711 /*
1712 * whether it fully enabled or not, mark as present,
1713 * again (but not INITTED)
1714 */
1715 dd->ipath_flags |= IPATH_PRESENT;
1716 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1717 if (val == dd->ipath_revision) {
1718 ipath_cdbg(VERBOSE, "Got matching revision "
1719 "register %llx on try %d\n",
1720 (unsigned long long) val, i);
1721 ret = ipath_reinit_msi(dd);
1722 goto bail;
1723 }
1724 /* Probably getting -1 back */
1725 ipath_dbg("Didn't get expected revision register, "
1726 "got %llx, try %d\n", (unsigned long long) val,
1727 i + 1);
1728 }
1729 ret = 0; /* failed */
1730
1731bail:
1732 if (ret)
1733 ipath_7220_pcie_params(dd, dd->ipath_boardrev);
1734
1735 return ret;
1736}
1737
1738/**
1739 * ipath_7220_put_tid - write a TID to the chip
1740 * @dd: the infinipath device
1741 * @tidptr: pointer to the expected TID (in chip) to update
1742 * @tidtype: 0 for eager, 1 for expected
1743 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1744 *
1745 * This exists as a separate routine to allow for selection of the
1746 * appropriate "flavor". The static calls in cleanup just use the
1747 * revision-agnostic form, as they are not performance critical.
1748 */
1749static void ipath_7220_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1750 u32 type, unsigned long pa)
1751{
1752 if (pa != dd->ipath_tidinvalid) {
1753 u64 chippa = pa >> IBA7220_TID_PA_SHIFT;
1754
1755 /* paranoia checks */
1756 if (pa != (chippa << IBA7220_TID_PA_SHIFT)) {
1757 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1758 "not 2KB aligned!\n", pa);
1759 return;
1760 }
1761 if (chippa >= (1UL << IBA7220_TID_SZ_SHIFT)) {
1762 ipath_dev_err(dd,
1763 "BUG: Physical page address 0x%lx "
1764 "larger than supported\n", pa);
1765 return;
1766 }
1767
1768 if (type == RCVHQ_RCV_TYPE_EAGER)
1769 chippa |= dd->ipath_tidtemplate;
1770 else /* for now, always full 4KB page */
1771 chippa |= IBA7220_TID_SZ_4K;
1772 writeq(chippa, tidptr);
1773 } else
1774 writeq(pa, tidptr);
1775 mmiowb();
1776}
1777
1778/**
1779 * ipath_7220_clear_tid - clear all TID entries for a port, expected and eager
1780 * @dd: the infinipath device
1781 * @port: the port
1782 *
1783 * clear all TID entries for a port, expected and eager.
1784 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
1785 * not 64, but they are still on 64 bit boundaries, so tidbase
1786 * is declared as u64 * for the pointer math, even though we write 32 bits
1787 */
1788static void ipath_7220_clear_tids(struct ipath_devdata *dd, unsigned port)
1789{
1790 u64 __iomem *tidbase;
1791 unsigned long tidinv;
1792 int i;
1793
1794 if (!dd->ipath_kregbase)
1795 return;
1796
1797 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1798
1799 tidinv = dd->ipath_tidinvalid;
1800 tidbase = (u64 __iomem *)
1801 ((char __iomem *)(dd->ipath_kregbase) +
1802 dd->ipath_rcvtidbase +
1803 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1804
1805 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1806 ipath_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1807 tidinv);
1808
1809 tidbase = (u64 __iomem *)
1810 ((char __iomem *)(dd->ipath_kregbase) +
1811 dd->ipath_rcvegrbase + port_egrtid_idx(dd, port)
1812 * sizeof(*tidbase));
1813
1814 for (i = port ? dd->ipath_rcvegrcnt : dd->ipath_p0_rcvegrcnt; i; i--)
1815 ipath_7220_put_tid(dd, &tidbase[i-1], RCVHQ_RCV_TYPE_EAGER,
1816 tidinv);
1817}
1818
1819/**
1820 * ipath_7220_tidtemplate - setup constants for TID updates
1821 * @dd: the infinipath device
1822 *
1823 * We setup stuff that we use a lot, to avoid calculating each time
1824 */
1825static void ipath_7220_tidtemplate(struct ipath_devdata *dd)
1826{
1827 /* For now, we always allocate 4KB buffers (at init) so we can
1828 * receive max size packets. We may want a module parameter to
1829 * specify 2KB or 4KB and/or make be per port instead of per device
1830 * for those who want to reduce memory footprint. Note that the
1831 * ipath_rcvhdrentsize size must be large enough to hold the largest
1832 * IB header (currently 96 bytes) that we expect to handle (plus of
1833 * course the 2 dwords of RHF).
1834 */
1835 if (dd->ipath_rcvegrbufsize == 2048)
1836 dd->ipath_tidtemplate = IBA7220_TID_SZ_2K;
1837 else if (dd->ipath_rcvegrbufsize == 4096)
1838 dd->ipath_tidtemplate = IBA7220_TID_SZ_4K;
1839 else {
1840 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1841 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1842 4096);
1843 dd->ipath_tidtemplate = IBA7220_TID_SZ_4K;
1844 }
1845 dd->ipath_tidinvalid = 0;
1846}
1847
1848static int ipath_7220_early_init(struct ipath_devdata *dd)
1849{
1850 u32 i, s;
1851
1852 if (strcmp(int_type, "auto") &&
1853 strcmp(int_type, "force_msi") &&
1854 strcmp(int_type, "force_intx")) {
1855 ipath_dev_err(dd, "Invalid interrupt_type: '%s', expecting "
1856 "auto, force_msi or force_intx\n", int_type);
1857 return -EINVAL;
1858 }
1859
1860 /*
1861 * Control[4] has been added to change the arbitration within
1862 * the SDMA engine between favoring data fetches over descriptor
1863 * fetches. ipath_sdma_fetch_arb==0 gives data fetches priority.
1864 */
1865 if (ipath_sdma_fetch_arb && (dd->ipath_minrev > 1))
1866 dd->ipath_control |= 1<<4;
1867
1868 dd->ipath_flags |= IPATH_4BYTE_TID;
1869
1870 /*
1871 * For openfabrics, we need to be able to handle an IB header of
1872 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1873 * made them the same size as the PIO buffers. This chip does not
1874 * handle arbitrary size buffers, so we need the header large enough
1875 * to handle largest IB header, but still have room for a 2KB MTU
1876 * standard IB packet.
1877 */
1878 dd->ipath_rcvhdrentsize = 24;
1879 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1880 dd->ipath_rhf_offset =
1881 dd->ipath_rcvhdrentsize - sizeof(u64) / sizeof(u32);
1882
1883 dd->ipath_rcvegrbufsize = ipath_mtu4096 ? 4096 : 2048;
1884 /*
1885 * the min() check here is currently a nop, but it may not always
1886 * be, depending on just how we do ipath_rcvegrbufsize
1887 */
1888 dd->ipath_ibmaxlen = min(ipath_mtu4096 ? dd->ipath_piosize4k :
1889 dd->ipath_piosize2k,
1890 dd->ipath_rcvegrbufsize +
1891 (dd->ipath_rcvhdrentsize << 2));
1892 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1893
1894 ipath_7220_config_jint(dd, INFINIPATH_JINT_DEFAULT_IDLE_TICKS,
1895 INFINIPATH_JINT_DEFAULT_MAX_PACKETS);
1896
1897 if (dd->ipath_boardrev) /* no eeprom on emulator */
1898 ipath_get_eeprom_info(dd);
1899
1900 /* start of code to check and print procmon */
1901 s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1902 s &= ~(1U<<31); /* clear done bit */
1903 s |= 1U<<14; /* clear counter (write 1 to clear) */
1904 ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1905 /* make sure clear_counter low long enough before start */
1906 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1907 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1908
1909 s &= ~(1U<<14); /* allow counter to count (before starting) */
1910 ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1911 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1912 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1913 s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1914
1915 s |= 1U<<15; /* start the counter */
1916 s &= ~(1U<<31); /* clear done bit */
1917 s &= ~0x7ffU; /* clear frequency bits */
1918 s |= 0xe29; /* set frequency bits, in case cleared */
1919 ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1920
1921 s = 0;
1922 for (i = 500; i > 0 && !(s&(1ULL<<31)); i--) {
1923 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1924 s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1925 }
1926 if (!(s&(1U<<31)))
1927 ipath_dev_err(dd, "ProcMon register not valid: 0x%x\n", s);
1928 else
1929 ipath_dbg("ProcMon=0x%x, count=0x%x\n", s, (s>>16)&0x1ff);
1930
1931 return 0;
1932}
1933
1934/**
1935 * ipath_init_7220_get_base_info - set chip-specific flags for user code
1936 * @pd: the infinipath port
1937 * @kbase: ipath_base_info pointer
1938 *
1939 * We set the PCIE flag because the lower bandwidth on PCIe vs
1940 * HyperTransport can affect some user packet algorithims.
1941 */
1942static int ipath_7220_get_base_info(struct ipath_portdata *pd, void *kbase)
1943{
1944 struct ipath_base_info *kinfo = kbase;
1945
1946 kinfo->spi_runtime_flags |=
1947 IPATH_RUNTIME_PCIE | IPATH_RUNTIME_NODMA_RTAIL |
1948 IPATH_RUNTIME_SDMA;
1949
1950 return 0;
1951}
1952
1953static void ipath_7220_free_irq(struct ipath_devdata *dd)
1954{
1955 free_irq(dd->ipath_irq, dd);
1956 dd->ipath_irq = 0;
1957}
1958
1959static struct ipath_message_header *
1960ipath_7220_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1961{
1962 u32 offset = ipath_hdrget_offset(rhf_addr);
1963
1964 return (struct ipath_message_header *)
1965 (rhf_addr - dd->ipath_rhf_offset + offset);
1966}
1967
1968static void ipath_7220_config_ports(struct ipath_devdata *dd, ushort cfgports)
1969{
1970 u32 nchipports;
1971
1972 nchipports = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1973 if (!cfgports) {
1974 int ncpus = num_online_cpus();
1975
1976 if (ncpus <= 4)
1977 dd->ipath_portcnt = 5;
1978 else if (ncpus <= 8)
1979 dd->ipath_portcnt = 9;
1980 if (dd->ipath_portcnt)
1981 ipath_dbg("Auto-configured for %u ports, %d cpus "
1982 "online\n", dd->ipath_portcnt, ncpus);
1983 } else if (cfgports <= nchipports)
1984 dd->ipath_portcnt = cfgports;
1985 if (!dd->ipath_portcnt) /* none of the above, set to max */
1986 dd->ipath_portcnt = nchipports;
1987 /*
1988 * chip can be configured for 5, 9, or 17 ports, and choice
1989 * affects number of eager TIDs per port (1K, 2K, 4K).
1990 */
1991 if (dd->ipath_portcnt > 9)
1992 dd->ipath_rcvctrl |= 2ULL << IBA7220_R_PORTCFG_SHIFT;
1993 else if (dd->ipath_portcnt > 5)
1994 dd->ipath_rcvctrl |= 1ULL << IBA7220_R_PORTCFG_SHIFT;
1995 /* else configure for default 5 receive ports */
1996 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1997 dd->ipath_rcvctrl);
1998 dd->ipath_p0_rcvegrcnt = 2048; /* always */
1999 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2000 dd->ipath_pioreserved = 3; /* kpiobufs used for PIO */
2001}
2002
2003
2004static int ipath_7220_get_ib_cfg(struct ipath_devdata *dd, int which)
2005{
2006 int lsb, ret = 0;
2007 u64 maskr; /* right-justified mask */
2008
2009 switch (which) {
2010 case IPATH_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2011 lsb = IBA7220_IBC_HRTBT_SHIFT;
2012 maskr = IBA7220_IBC_HRTBT_MASK;
2013 break;
2014
2015 case IPATH_IB_CFG_LWID_ENB: /* Get allowed Link-width */
2016 ret = dd->ipath_link_width_enabled;
2017 goto done;
2018
2019 case IPATH_IB_CFG_LWID: /* Get currently active Link-width */
2020 ret = dd->ipath_link_width_active;
2021 goto done;
2022
2023 case IPATH_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
2024 ret = dd->ipath_link_speed_enabled;
2025 goto done;
2026
2027 case IPATH_IB_CFG_SPD: /* Get current Link spd */
2028 ret = dd->ipath_link_speed_active;
2029 goto done;
2030
2031 case IPATH_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
2032 lsb = IBA7220_IBC_RXPOL_SHIFT;
2033 maskr = IBA7220_IBC_RXPOL_MASK;
2034 break;
2035
2036 case IPATH_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
2037 lsb = IBA7220_IBC_LREV_SHIFT;
2038 maskr = IBA7220_IBC_LREV_MASK;
2039 break;
2040
2041 case IPATH_IB_CFG_LINKLATENCY:
2042 ret = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcddrstatus)
2043 & IBA7220_DDRSTAT_LINKLAT_MASK;
2044 goto done;
2045
2046 default:
2047 ret = -ENOTSUPP;
2048 goto done;
2049 }
2050 ret = (int)((dd->ipath_ibcddrctrl >> lsb) & maskr);
2051done:
2052 return ret;
2053}
2054
2055static int ipath_7220_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
2056{
2057 int lsb, ret = 0, setforce = 0;
2058 u64 maskr; /* right-justified mask */
2059
2060 switch (which) {
2061 case IPATH_IB_CFG_LIDLMC:
2062 /*
2063 * Set LID and LMC. Combined to avoid possible hazard
2064 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
2065 */
2066 lsb = IBA7220_IBC_DLIDLMC_SHIFT;
2067 maskr = IBA7220_IBC_DLIDLMC_MASK;
2068 break;
2069
2070 case IPATH_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
2071 if (val & IPATH_IB_HRTBT_ON &&
2072 (dd->ipath_flags & IPATH_NO_HRTBT))
2073 goto bail;
2074 lsb = IBA7220_IBC_HRTBT_SHIFT;
2075 maskr = IBA7220_IBC_HRTBT_MASK;
2076 break;
2077
2078 case IPATH_IB_CFG_LWID_ENB: /* set allowed Link-width */
2079 /*
2080 * As with speed, only write the actual register if
2081 * the link is currently down, otherwise takes effect
2082 * on next link change.
2083 */
2084 dd->ipath_link_width_enabled = val;
2085 if ((dd->ipath_flags & (IPATH_LINKDOWN|IPATH_LINKINIT)) !=
2086 IPATH_LINKDOWN)
2087 goto bail;
2088 /*
2089 * We set the IPATH_IB_FORCE_NOTIFY bit so updown
2090 * will get called because we want update
2091 * link_width_active, and the change may not take
2092 * effect for some time (if we are in POLL), so this
2093 * flag will force the updown routine to be called
2094 * on the next ibstatuschange down interrupt, even
2095 * if it's not an down->up transition.
2096 */
2097 val--; /* convert from IB to chip */
2098 maskr = IBA7220_IBC_WIDTH_MASK;
2099 lsb = IBA7220_IBC_WIDTH_SHIFT;
2100 setforce = 1;
2101 dd->ipath_flags |= IPATH_IB_FORCE_NOTIFY;
2102 break;
2103
2104 case IPATH_IB_CFG_SPD_ENB: /* set allowed Link speeds */
2105 /*
2106 * If we turn off IB1.2, need to preset SerDes defaults,
2107 * but not right now. Set a flag for the next time
2108 * we command the link down. As with width, only write the
2109 * actual register if the link is currently down, otherwise
2110 * takes effect on next link change. Since setting is being
2111 * explictly requested (via MAD or sysfs), clear autoneg
2112 * failure status if speed autoneg is enabled.
2113 */
2114 dd->ipath_link_speed_enabled = val;
2115 if (dd->ipath_ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK &&
2116 !(val & (val - 1)))
2117 dd->ipath_presets_needed = 1;
2118 if ((dd->ipath_flags & (IPATH_LINKDOWN|IPATH_LINKINIT)) !=
2119 IPATH_LINKDOWN)
2120 goto bail;
2121 /*
2122 * We set the IPATH_IB_FORCE_NOTIFY bit so updown
2123 * will get called because we want update
2124 * link_speed_active, and the change may not take
2125 * effect for some time (if we are in POLL), so this
2126 * flag will force the updown routine to be called
2127 * on the next ibstatuschange down interrupt, even
2128 * if it's not an down->up transition. When setting
2129 * speed autoneg, clear AUTONEG_FAILED.
2130 */
2131 if (val == (IPATH_IB_SDR | IPATH_IB_DDR)) {
2132 val = IBA7220_IBC_SPEED_AUTONEG_MASK |
2133 IBA7220_IBC_IBTA_1_2_MASK;
2134 dd->ipath_flags &= ~IPATH_IB_AUTONEG_FAILED;
2135 } else
2136 val = val == IPATH_IB_DDR ? IBA7220_IBC_SPEED_DDR
2137 : IBA7220_IBC_SPEED_SDR;
2138 maskr = IBA7220_IBC_SPEED_AUTONEG_MASK |
2139 IBA7220_IBC_IBTA_1_2_MASK;
2140 lsb = 0; /* speed bits are low bits */
2141 setforce = 1;
2142 break;
2143
2144 case IPATH_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
2145 lsb = IBA7220_IBC_RXPOL_SHIFT;
2146 maskr = IBA7220_IBC_RXPOL_MASK;
2147 break;
2148
2149 case IPATH_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
2150 lsb = IBA7220_IBC_LREV_SHIFT;
2151 maskr = IBA7220_IBC_LREV_MASK;
2152 break;
2153
2154 default:
2155 ret = -ENOTSUPP;
2156 goto bail;
2157 }
2158 dd->ipath_ibcddrctrl &= ~(maskr << lsb);
2159 dd->ipath_ibcddrctrl |= (((u64) val & maskr) << lsb);
2160 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
2161 dd->ipath_ibcddrctrl);
2162 if (setforce)
2163 dd->ipath_flags |= IPATH_IB_FORCE_NOTIFY;
2164bail:
2165 return ret;
2166}
2167
2168static void ipath_7220_read_counters(struct ipath_devdata *dd,
2169 struct infinipath_counters *cntrs)
2170{
2171 u64 *counters = (u64 *) cntrs;
2172 int i;
2173
2174 for (i = 0; i < sizeof(*cntrs) / sizeof(u64); i++)
2175 counters[i] = ipath_snap_cntr(dd, i);
2176}
2177
2178/* if we are using MSI, try to fallback to INTx */
2179static int ipath_7220_intr_fallback(struct ipath_devdata *dd)
2180{
2181 if (dd->ipath_msi_lo) {
2182 dev_info(&dd->pcidev->dev, "MSI interrupt not detected,"
2183 " trying INTx interrupts\n");
2184 ipath_7220_nomsi(dd);
2185 ipath_enable_intx(dd->pcidev);
2186 /*
2187 * some newer kernels require free_irq before disable_msi,
2188 * and irq can be changed during disable and intx enable
2189 * and we need to therefore use the pcidev->irq value,
2190 * not our saved MSI value.
2191 */
2192 dd->ipath_irq = dd->pcidev->irq;
2193 if (request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
2194 IPATH_DRV_NAME, dd))
2195 ipath_dev_err(dd,
2196 "Could not re-request_irq for INTx\n");
2197 return 1;
2198 }
2199 return 0;
2200}
2201
2202/*
2203 * reset the XGXS (between serdes and IBC). Slightly less intrusive
2204 * than resetting the IBC or external link state, and useful in some
2205 * cases to cause some retraining. To do this right, we reset IBC
2206 * as well.
2207 */
2208static void ipath_7220_xgxs_reset(struct ipath_devdata *dd)
2209{
2210 u64 val, prev_val;
2211
2212 prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2213 val = prev_val | INFINIPATH_XGXS_RESET;
2214 prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
2215 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2216 dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
2217 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2218 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
2219 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
2220 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2221 dd->ipath_control);
2222}
2223
2224
2225/* Still needs cleanup, too much hardwired stuff */
2226static void autoneg_send(struct ipath_devdata *dd,
2227 u32 *hdr, u32 dcnt, u32 *data)
2228{
2229 int i;
2230 u64 cnt;
2231 u32 __iomem *piobuf;
2232 u32 pnum;
2233
2234 i = 0;
2235 cnt = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
2236 while (!(piobuf = ipath_getpiobuf(dd, cnt, &pnum))) {
2237 if (i++ > 15) {
2238 ipath_dbg("Couldn't get pio buffer for send\n");
2239 return;
2240 }
2241 udelay(2);
2242 }
2243 if (dd->ipath_flags&IPATH_HAS_PBC_CNT)
2244 cnt |= 0x80000000UL<<32; /* mark as VL15 */
2245 writeq(cnt, piobuf);
2246 ipath_flush_wc();
2247 __iowrite32_copy(piobuf + 2, hdr, 7);
2248 __iowrite32_copy(piobuf + 9, data, dcnt);
2249 ipath_flush_wc();
2250}
2251
2252/*
2253 * _start packet gets sent twice at start, _done gets sent twice at end
2254 */
2255static void ipath_autoneg_send(struct ipath_devdata *dd, int which)
2256{
2257 static u32 swapped;
2258 u32 dw, i, hcnt, dcnt, *data;
2259 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
2260 static u32 madpayload_start[0x40] = {
2261 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
2262 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
2263 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
2264 };
2265 static u32 madpayload_done[0x40] = {
2266 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
2267 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
2268 0x40000001, 0x1388, 0x15e, /* rest 0's */
2269 };
2270 dcnt = ARRAY_SIZE(madpayload_start);
2271 hcnt = ARRAY_SIZE(hdr);
2272 if (!swapped) {
2273 /* for maintainability, do it at runtime */
2274 for (i = 0; i < hcnt; i++) {
2275 dw = (__force u32) cpu_to_be32(hdr[i]);
2276 hdr[i] = dw;
2277 }
2278 for (i = 0; i < dcnt; i++) {
2279 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
2280 madpayload_start[i] = dw;
2281 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
2282 madpayload_done[i] = dw;
2283 }
2284 swapped = 1;
2285 }
2286
2287 data = which ? madpayload_done : madpayload_start;
2288 ipath_cdbg(PKT, "Sending %s special MADs\n", which?"done":"start");
2289
2290 autoneg_send(dd, hdr, dcnt, data);
2291 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2292 udelay(2);
2293 autoneg_send(dd, hdr, dcnt, data);
2294 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2295 udelay(2);
2296}
2297
2298
2299
2300/*
2301 * Do the absolute minimum to cause an IB speed change, and make it
2302 * ready, but don't actually trigger the change. The caller will
2303 * do that when ready (if link is in Polling training state, it will
2304 * happen immediately, otherwise when link next goes down)
2305 *
2306 * This routine should only be used as part of the DDR autonegotation
2307 * code for devices that are not compliant with IB 1.2 (or code that
2308 * fixes things up for same).
2309 *
2310 * When link has gone down, and autoneg enabled, or autoneg has
2311 * failed and we give up until next time we set both speeds, and
2312 * then we want IBTA enabled as well as "use max enabled speed.
2313 */
2314static void set_speed_fast(struct ipath_devdata *dd, u32 speed)
2315{
2316 dd->ipath_ibcddrctrl &= ~(IBA7220_IBC_SPEED_AUTONEG_MASK |
2317 IBA7220_IBC_IBTA_1_2_MASK |
2318 (IBA7220_IBC_WIDTH_MASK << IBA7220_IBC_WIDTH_SHIFT));
2319
2320 if (speed == (IPATH_IB_SDR | IPATH_IB_DDR))
2321 dd->ipath_ibcddrctrl |= IBA7220_IBC_SPEED_AUTONEG_MASK |
2322 IBA7220_IBC_IBTA_1_2_MASK;
2323 else
2324 dd->ipath_ibcddrctrl |= speed == IPATH_IB_DDR ?
2325 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
2326
2327 /*
2328 * Convert from IB-style 1 = 1x, 2 = 4x, 3 = auto
2329 * to chip-centric 0 = 1x, 1 = 4x, 2 = auto
2330 */
2331 dd->ipath_ibcddrctrl |= (u64)(dd->ipath_link_width_enabled - 1) <<
2332 IBA7220_IBC_WIDTH_SHIFT;
2333 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
2334 dd->ipath_ibcddrctrl);
2335 ipath_cdbg(VERBOSE, "setup for IB speed (%x) done\n", speed);
2336}
2337
2338
2339/*
2340 * this routine is only used when we are not talking to another
2341 * IB 1.2-compliant device that we think can do DDR.
2342 * (This includes all existing switch chips as of Oct 2007.)
2343 * 1.2-compliant devices go directly to DDR prior to reaching INIT
2344 */
2345static void try_auto_neg(struct ipath_devdata *dd)
2346{
2347 /*
2348 * required for older non-IB1.2 DDR switches. Newer
2349 * non-IB-compliant switches don't need it, but so far,
2350 * aren't bothered by it either. "Magic constant"
2351 */
2352 ipath_write_kreg(dd, IPATH_KREG_OFFSET(IBNCModeCtrl),
2353 0x3b9dc07);
2354 dd->ipath_flags |= IPATH_IB_AUTONEG_INPROG;
2355 ipath_autoneg_send(dd, 0);
2356 set_speed_fast(dd, IPATH_IB_DDR);
2357 ipath_toggle_rclkrls(dd);
2358 /* 2 msec is minimum length of a poll cycle */
2359 schedule_delayed_work(&dd->ipath_autoneg_work,
2360 msecs_to_jiffies(2));
2361}
2362
2363
2364static int ipath_7220_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
2365{
2366 int ret = 0, symadj = 0;
2367 u32 ltstate = ipath_ib_linkstate(dd, ibcs);
2368
2369 dd->ipath_link_width_active =
2370 ((ibcs >> IBA7220_IBCS_LINKWIDTH_SHIFT) & 1) ?
2371 IB_WIDTH_4X : IB_WIDTH_1X;
2372 dd->ipath_link_speed_active =
2373 ((ibcs >> IBA7220_IBCS_LINKSPEED_SHIFT) & 1) ?
2374 IPATH_IB_DDR : IPATH_IB_SDR;
2375
2376 if (!ibup) {
2377 /*
2378 * when link goes down we don't want aeq running, so it
2379 * won't't interfere with IBC training, etc., and we need
2380 * to go back to the static SerDes preset values
2381 */
2382 if (dd->ipath_x1_fix_tries &&
2383 ltstate <= INFINIPATH_IBCS_LT_STATE_SLEEPQUIET &&
2384 ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP)
2385 dd->ipath_x1_fix_tries = 0;
2386 if (!(dd->ipath_flags & (IPATH_IB_AUTONEG_FAILED |
2387 IPATH_IB_AUTONEG_INPROG)))
2388 set_speed_fast(dd, dd->ipath_link_speed_enabled);
2389 if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)) {
2390 ipath_cdbg(VERBOSE, "Setting RXEQ defaults\n");
2391 ipath_sd7220_presets(dd);
2392 }
2393 /* this might better in ipath_sd7220_presets() */
2394 ipath_set_relock_poll(dd, ibup);
2395 } else {
2396 if (ipath_compat_ddr_negotiate &&
2397 !(dd->ipath_flags & (IPATH_IB_AUTONEG_FAILED |
2398 IPATH_IB_AUTONEG_INPROG)) &&
2399 dd->ipath_link_speed_active == IPATH_IB_SDR &&
2400 (dd->ipath_link_speed_enabled &
2401 (IPATH_IB_DDR | IPATH_IB_SDR)) ==
2402 (IPATH_IB_DDR | IPATH_IB_SDR) &&
2403 dd->ipath_autoneg_tries < IPATH_AUTONEG_TRIES) {
2404 /* we are SDR, and DDR auto-negotiation enabled */
2405 ++dd->ipath_autoneg_tries;
2406 ipath_dbg("DDR negotiation try, %u/%u\n",
2407 dd->ipath_autoneg_tries,
2408 IPATH_AUTONEG_TRIES);
2409 if (!dd->ibdeltainprog) {
2410 dd->ibdeltainprog = 1;
2411 dd->ibsymsnap = ipath_read_creg32(dd,
2412 dd->ipath_cregs->cr_ibsymbolerrcnt);
2413 dd->iblnkerrsnap = ipath_read_creg32(dd,
2414 dd->ipath_cregs->cr_iblinkerrrecovcnt);
2415 }
2416 try_auto_neg(dd);
2417 ret = 1; /* no other IB status change processing */
2418 } else if ((dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)
2419 && dd->ipath_link_speed_active == IPATH_IB_SDR) {
2420 ipath_autoneg_send(dd, 1);
2421 set_speed_fast(dd, IPATH_IB_DDR);
2422 udelay(2);
2423 ipath_toggle_rclkrls(dd);
2424 ret = 1; /* no other IB status change processing */
2425 } else {
2426 if ((dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) &&
2427 (dd->ipath_link_speed_active & IPATH_IB_DDR)) {
2428 ipath_dbg("Got to INIT with DDR autoneg\n");
2429 dd->ipath_flags &= ~(IPATH_IB_AUTONEG_INPROG
2430 | IPATH_IB_AUTONEG_FAILED);
2431 dd->ipath_autoneg_tries = 0;
2432 /* re-enable SDR, for next link down */
2433 set_speed_fast(dd,
2434 dd->ipath_link_speed_enabled);
2435 wake_up(&dd->ipath_autoneg_wait);
2436 symadj = 1;
2437 } else if (dd->ipath_flags & IPATH_IB_AUTONEG_FAILED) {
2438 /*
2439 * clear autoneg failure flag, and do setup
2440 * so we'll try next time link goes down and
2441 * back to INIT (possibly connected to different
2442 * device).
2443 */
2444 ipath_dbg("INIT %sDR after autoneg failure\n",
2445 (dd->ipath_link_speed_active &
2446 IPATH_IB_DDR) ? "D" : "S");
2447 dd->ipath_flags &= ~IPATH_IB_AUTONEG_FAILED;
2448 dd->ipath_ibcddrctrl |=
2449 IBA7220_IBC_IBTA_1_2_MASK;
2450 ipath_write_kreg(dd,
2451 IPATH_KREG_OFFSET(IBNCModeCtrl), 0);
2452 symadj = 1;
2453 }
2454 }
2455 /*
2456 * if we are in 1X on rev1 only, and are in autoneg width,
2457 * it could be due to an xgxs problem, so if we haven't
2458 * already tried, try twice to get to 4X; if we
2459 * tried, and couldn't, report it, since it will
2460 * probably not be what is desired.
2461 */
2462 if (dd->ipath_minrev == 1 &&
2463 (dd->ipath_link_width_enabled & (IB_WIDTH_1X |
2464 IB_WIDTH_4X)) == (IB_WIDTH_1X | IB_WIDTH_4X)
2465 && dd->ipath_link_width_active == IB_WIDTH_1X
2466 && dd->ipath_x1_fix_tries < 3) {
2467 if (++dd->ipath_x1_fix_tries == 3) {
2468 dev_info(&dd->pcidev->dev,
2469 "IB link is in 1X mode\n");
2470 if (!(dd->ipath_flags &
2471 IPATH_IB_AUTONEG_INPROG))
2472 symadj = 1;
2473 }
2474 else {
2475 ipath_cdbg(VERBOSE, "IB 1X in "
2476 "auto-width, try %u to be "
2477 "sure it's really 1X; "
2478 "ltstate %u\n",
2479 dd->ipath_x1_fix_tries,
2480 ltstate);
2481 dd->ipath_f_xgxs_reset(dd);
2482 ret = 1; /* skip other processing */
2483 }
2484 } else if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG))
2485 symadj = 1;
2486
2487 if (!ret) {
2488 dd->delay_mult = rate_to_delay
2489 [(ibcs >> IBA7220_IBCS_LINKSPEED_SHIFT) & 1]
2490 [(ibcs >> IBA7220_IBCS_LINKWIDTH_SHIFT) & 1];
2491
2492 ipath_set_relock_poll(dd, ibup);
2493 }
2494 }
2495
2496 if (symadj) {
2497 if (dd->ibdeltainprog) {
2498 dd->ibdeltainprog = 0;
2499 dd->ibsymdelta += ipath_read_creg32(dd,
2500 dd->ipath_cregs->cr_ibsymbolerrcnt) -
2501 dd->ibsymsnap;
2502 dd->iblnkerrdelta += ipath_read_creg32(dd,
2503 dd->ipath_cregs->cr_iblinkerrrecovcnt) -
2504 dd->iblnkerrsnap;
2505 }
2506 } else if (!ibup && !dd->ibdeltainprog
2507 && !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)) {
2508 dd->ibdeltainprog = 1;
2509 dd->ibsymsnap = ipath_read_creg32(dd,
2510 dd->ipath_cregs->cr_ibsymbolerrcnt);
2511 dd->iblnkerrsnap = ipath_read_creg32(dd,
2512 dd->ipath_cregs->cr_iblinkerrrecovcnt);
2513 }
2514
2515 if (!ret)
2516 ipath_setup_7220_setextled(dd, ipath_ib_linkstate(dd, ibcs),
2517 ltstate);
2518 return ret;
2519}
2520
2521
2522/*
2523 * Handle the empirically determined mechanism for auto-negotiation
2524 * of DDR speed with switches.
2525 */
2526static void autoneg_work(struct work_struct *work)
2527{
2528 struct ipath_devdata *dd;
2529 u64 startms;
2530 u32 lastlts, i;
2531
2532 dd = container_of(work, struct ipath_devdata,
2533 ipath_autoneg_work.work);
2534
2535 startms = jiffies_to_msecs(jiffies);
2536
2537 /*
2538 * busy wait for this first part, it should be at most a
2539 * few hundred usec, since we scheduled ourselves for 2msec.
2540 */
2541 for (i = 0; i < 25; i++) {
2542 lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat);
2543 if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
2544 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN_DISABLE);
2545 break;
2546 }
2547 udelay(100);
2548 }
2549
2550 if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG))
2551 goto done; /* we got there early or told to stop */
2552
2553 /* we expect this to timeout */
2554 if (wait_event_timeout(dd->ipath_autoneg_wait,
2555 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2556 msecs_to_jiffies(90)))
2557 goto done;
2558
2559 ipath_toggle_rclkrls(dd);
2560
2561 /* we expect this to timeout */
2562 if (wait_event_timeout(dd->ipath_autoneg_wait,
2563 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2564 msecs_to_jiffies(1700)))
2565 goto done;
2566
2567 set_speed_fast(dd, IPATH_IB_SDR);
2568 ipath_toggle_rclkrls(dd);
2569
2570 /*
2571 * wait up to 250 msec for link to train and get to INIT at DDR;
2572 * this should terminate early
2573 */
2574 wait_event_timeout(dd->ipath_autoneg_wait,
2575 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2576 msecs_to_jiffies(250));
2577done:
2578 if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
2579 ipath_dbg("Did not get to DDR INIT (%x) after %Lu msecs\n",
2580 ipath_ib_state(dd, dd->ipath_lastibcstat),
2581 (unsigned long long) jiffies_to_msecs(jiffies)-startms);
2582 dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
2583 if (dd->ipath_autoneg_tries == IPATH_AUTONEG_TRIES) {
2584 dd->ipath_flags |= IPATH_IB_AUTONEG_FAILED;
2585 ipath_dbg("Giving up on DDR until next IB "
2586 "link Down\n");
2587 dd->ipath_autoneg_tries = 0;
2588 }
2589 set_speed_fast(dd, dd->ipath_link_speed_enabled);
2590 }
2591}
2592
2593
2594/**
2595 * ipath_init_iba7220_funcs - set up the chip-specific function pointers
2596 * @dd: the infinipath device
2597 *
2598 * This is global, and is called directly at init to set up the
2599 * chip-specific function pointers for later use.
2600 */
2601void ipath_init_iba7220_funcs(struct ipath_devdata *dd)
2602{
2603 dd->ipath_f_intrsetup = ipath_7220_intconfig;
2604 dd->ipath_f_bus = ipath_setup_7220_config;
2605 dd->ipath_f_reset = ipath_setup_7220_reset;
2606 dd->ipath_f_get_boardname = ipath_7220_boardname;
2607 dd->ipath_f_init_hwerrors = ipath_7220_init_hwerrors;
2608 dd->ipath_f_early_init = ipath_7220_early_init;
2609 dd->ipath_f_handle_hwerrors = ipath_7220_handle_hwerrors;
2610 dd->ipath_f_quiet_serdes = ipath_7220_quiet_serdes;
2611 dd->ipath_f_bringup_serdes = ipath_7220_bringup_serdes;
2612 dd->ipath_f_clear_tids = ipath_7220_clear_tids;
2613 dd->ipath_f_put_tid = ipath_7220_put_tid;
2614 dd->ipath_f_cleanup = ipath_setup_7220_cleanup;
2615 dd->ipath_f_setextled = ipath_setup_7220_setextled;
2616 dd->ipath_f_get_base_info = ipath_7220_get_base_info;
2617 dd->ipath_f_free_irq = ipath_7220_free_irq;
2618 dd->ipath_f_tidtemplate = ipath_7220_tidtemplate;
2619 dd->ipath_f_intr_fallback = ipath_7220_intr_fallback;
2620 dd->ipath_f_xgxs_reset = ipath_7220_xgxs_reset;
2621 dd->ipath_f_get_ib_cfg = ipath_7220_get_ib_cfg;
2622 dd->ipath_f_set_ib_cfg = ipath_7220_set_ib_cfg;
2623 dd->ipath_f_config_jint = ipath_7220_config_jint;
2624 dd->ipath_f_config_ports = ipath_7220_config_ports;
2625 dd->ipath_f_read_counters = ipath_7220_read_counters;
2626 dd->ipath_f_get_msgheader = ipath_7220_get_msgheader;
2627 dd->ipath_f_ib_updown = ipath_7220_ib_updown;
2628
2629 /* initialize chip-specific variables */
2630 ipath_init_7220_variables(dd);
2631}
diff --git a/drivers/infiniband/hw/ipath/ipath_kernel.h b/drivers/infiniband/hw/ipath/ipath_kernel.h
index b3d7efcdf02..6559af60bff 100644
--- a/drivers/infiniband/hw/ipath/ipath_kernel.h
+++ b/drivers/infiniband/hw/ipath/ipath_kernel.h
@@ -1030,8 +1030,6 @@ void ipath_free_data(struct ipath_portdata *dd);
1030u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32, u32 *); 1030u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32, u32 *);
1031void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start, 1031void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1032 unsigned len, int avail); 1032 unsigned len, int avail);
1033void ipath_init_iba7220_funcs(struct ipath_devdata *);
1034void ipath_init_iba6120_funcs(struct ipath_devdata *);
1035void ipath_init_iba6110_funcs(struct ipath_devdata *); 1033void ipath_init_iba6110_funcs(struct ipath_devdata *);
1036void ipath_get_eeprom_info(struct ipath_devdata *); 1034void ipath_get_eeprom_info(struct ipath_devdata *);
1037int ipath_update_eeprom_log(struct ipath_devdata *dd); 1035int ipath_update_eeprom_log(struct ipath_devdata *dd);
diff --git a/drivers/infiniband/hw/ipath/ipath_sd7220.c b/drivers/infiniband/hw/ipath/ipath_sd7220.c
deleted file mode 100644
index 2a68d9f624d..00000000000
--- a/drivers/infiniband/hw/ipath/ipath_sd7220.c
+++ /dev/null
@@ -1,1462 +0,0 @@
1/*
2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33/*
34 * This file contains all of the code that is specific to the SerDes
35 * on the InfiniPath 7220 chip.
36 */
37
38#include <linux/pci.h>
39#include <linux/delay.h>
40
41#include "ipath_kernel.h"
42#include "ipath_registers.h"
43#include "ipath_7220.h"
44
45/*
46 * The IBSerDesMappTable is a memory that holds values to be stored in
47 * various SerDes registers by IBC. It is not part of the normal kregs
48 * map and is used in exactly one place, hence the #define below.
49 */
50#define KR_IBSerDesMappTable (0x94000 / (sizeof(uint64_t)))
51
52/*
53 * Below used for sdnum parameter, selecting one of the two sections
54 * used for PCIe, or the single SerDes used for IB.
55 */
56#define PCIE_SERDES0 0
57#define PCIE_SERDES1 1
58
59/*
60 * The EPB requires addressing in a particular form. EPB_LOC() is intended
61 * to make #definitions a little more readable.
62 */
63#define EPB_ADDR_SHF 8
64#define EPB_LOC(chn, elt, reg) \
65 (((elt & 0xf) | ((chn & 7) << 4) | ((reg & 0x3f) << 9)) << \
66 EPB_ADDR_SHF)
67#define EPB_IB_QUAD0_CS_SHF (25)
68#define EPB_IB_QUAD0_CS (1U << EPB_IB_QUAD0_CS_SHF)
69#define EPB_IB_UC_CS_SHF (26)
70#define EPB_PCIE_UC_CS_SHF (27)
71#define EPB_GLOBAL_WR (1U << (EPB_ADDR_SHF + 8))
72
73/* Forward declarations. */
74static int ipath_sd7220_reg_mod(struct ipath_devdata *dd, int sdnum, u32 loc,
75 u32 data, u32 mask);
76static int ibsd_mod_allchnls(struct ipath_devdata *dd, int loc, int val,
77 int mask);
78static int ipath_sd_trimdone_poll(struct ipath_devdata *dd);
79static void ipath_sd_trimdone_monitor(struct ipath_devdata *dd,
80 const char *where);
81static int ipath_sd_setvals(struct ipath_devdata *dd);
82static int ipath_sd_early(struct ipath_devdata *dd);
83static int ipath_sd_dactrim(struct ipath_devdata *dd);
84/* Set the registers that IBC may muck with to their default "preset" values */
85int ipath_sd7220_presets(struct ipath_devdata *dd);
86static int ipath_internal_presets(struct ipath_devdata *dd);
87/* Tweak the register (CMUCTRL5) that contains the TRIMSELF controls */
88static int ipath_sd_trimself(struct ipath_devdata *dd, int val);
89static int epb_access(struct ipath_devdata *dd, int sdnum, int claim);
90
91void ipath_set_relock_poll(struct ipath_devdata *dd, int ibup);
92
93/*
94 * Below keeps track of whether the "once per power-on" initialization has
95 * been done, because uC code Version 1.32.17 or higher allows the uC to
96 * be reset at will, and Automatic Equalization may require it. So the
97 * state of the reset "pin", as reflected in was_reset parameter to
98 * ipath_sd7220_init() is no longer valid. Instead, we check for the
99 * actual uC code having been loaded.
100 */
101static int ipath_ibsd_ucode_loaded(struct ipath_devdata *dd)
102{
103 if (!dd->serdes_first_init_done && (ipath_sd7220_ib_vfy(dd) > 0))
104 dd->serdes_first_init_done = 1;
105 return dd->serdes_first_init_done;
106}
107
108/* repeat #define for local use. "Real" #define is in ipath_iba7220.c */
109#define INFINIPATH_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
110#define IB_MPREG5 (EPB_LOC(6, 0, 0xE) | (1L << EPB_IB_UC_CS_SHF))
111#define IB_MPREG6 (EPB_LOC(6, 0, 0xF) | (1U << EPB_IB_UC_CS_SHF))
112#define UC_PAR_CLR_D 8
113#define UC_PAR_CLR_M 0xC
114#define IB_CTRL2(chn) (EPB_LOC(chn, 7, 3) | EPB_IB_QUAD0_CS)
115#define START_EQ1(chan) EPB_LOC(chan, 7, 0x27)
116
117void ipath_sd7220_clr_ibpar(struct ipath_devdata *dd)
118{
119 int ret;
120
121 /* clear, then re-enable parity errs */
122 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6,
123 UC_PAR_CLR_D, UC_PAR_CLR_M);
124 if (ret < 0) {
125 ipath_dev_err(dd, "Failed clearing IBSerDes Parity err\n");
126 goto bail;
127 }
128 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0,
129 UC_PAR_CLR_M);
130
131 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
132 udelay(4);
133 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
134 INFINIPATH_HWE_IB_UC_MEMORYPARITYERR);
135 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
136bail:
137 return;
138}
139
140/*
141 * After a reset or other unusual event, the epb interface may need
142 * to be re-synchronized, between the host and the uC.
143 * returns <0 for failure to resync within IBSD_RESYNC_TRIES (not expected)
144 */
145#define IBSD_RESYNC_TRIES 3
146#define IB_PGUDP(chn) (EPB_LOC((chn), 2, 1) | EPB_IB_QUAD0_CS)
147#define IB_CMUDONE(chn) (EPB_LOC((chn), 7, 0xF) | EPB_IB_QUAD0_CS)
148
149static int ipath_resync_ibepb(struct ipath_devdata *dd)
150{
151 int ret, pat, tries, chn;
152 u32 loc;
153
154 ret = -1;
155 chn = 0;
156 for (tries = 0; tries < (4 * IBSD_RESYNC_TRIES); ++tries) {
157 loc = IB_PGUDP(chn);
158 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
159 if (ret < 0) {
160 ipath_dev_err(dd, "Failed read in resync\n");
161 continue;
162 }
163 if (ret != 0xF0 && ret != 0x55 && tries == 0)
164 ipath_dev_err(dd, "unexpected pattern in resync\n");
165 pat = ret ^ 0xA5; /* alternate F0 and 55 */
166 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, pat, 0xFF);
167 if (ret < 0) {
168 ipath_dev_err(dd, "Failed write in resync\n");
169 continue;
170 }
171 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
172 if (ret < 0) {
173 ipath_dev_err(dd, "Failed re-read in resync\n");
174 continue;
175 }
176 if (ret != pat) {
177 ipath_dev_err(dd, "Failed compare1 in resync\n");
178 continue;
179 }
180 loc = IB_CMUDONE(chn);
181 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
182 if (ret < 0) {
183 ipath_dev_err(dd, "Failed CMUDONE rd in resync\n");
184 continue;
185 }
186 if ((ret & 0x70) != ((chn << 4) | 0x40)) {
187 ipath_dev_err(dd, "Bad CMUDONE value %02X, chn %d\n",
188 ret, chn);
189 continue;
190 }
191 if (++chn == 4)
192 break; /* Success */
193 }
194 ipath_cdbg(VERBOSE, "Resync in %d tries\n", tries);
195 return (ret > 0) ? 0 : ret;
196}
197
198/*
199 * Localize the stuff that should be done to change IB uC reset
200 * returns <0 for errors.
201 */
202static int ipath_ibsd_reset(struct ipath_devdata *dd, int assert_rst)
203{
204 u64 rst_val;
205 int ret = 0;
206 unsigned long flags;
207
208 rst_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibserdesctrl);
209 if (assert_rst) {
210 /*
211 * Vendor recommends "interrupting" uC before reset, to
212 * minimize possible glitches.
213 */
214 spin_lock_irqsave(&dd->ipath_sdepb_lock, flags);
215 epb_access(dd, IB_7220_SERDES, 1);
216 rst_val |= 1ULL;
217 /* Squelch possible parity error from _asserting_ reset */
218 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
219 dd->ipath_hwerrmask &
220 ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR);
221 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibserdesctrl, rst_val);
222 /* flush write, delay to ensure it took effect */
223 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
224 udelay(2);
225 /* once it's reset, can remove interrupt */
226 epb_access(dd, IB_7220_SERDES, -1);
227 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
228 } else {
229 /*
230 * Before we de-assert reset, we need to deal with
231 * possible glitch on the Parity-error line.
232 * Suppress it around the reset, both in chip-level
233 * hwerrmask and in IB uC control reg. uC will allow
234 * it again during startup.
235 */
236 u64 val;
237 rst_val &= ~(1ULL);
238 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
239 dd->ipath_hwerrmask &
240 ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR);
241
242 ret = ipath_resync_ibepb(dd);
243 if (ret < 0)
244 ipath_dev_err(dd, "unable to re-sync IB EPB\n");
245
246 /* set uC control regs to suppress parity errs */
247 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG5, 1, 1);
248 if (ret < 0)
249 goto bail;
250 /* IB uC code past Version 1.32.17 allow suppression of wdog */
251 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80,
252 0x80);
253 if (ret < 0) {
254 ipath_dev_err(dd, "Failed to set WDOG disable\n");
255 goto bail;
256 }
257 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibserdesctrl, rst_val);
258 /* flush write, delay for startup */
259 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
260 udelay(1);
261 /* clear, then re-enable parity errs */
262 ipath_sd7220_clr_ibpar(dd);
263 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
264 if (val & INFINIPATH_HWE_IB_UC_MEMORYPARITYERR) {
265 ipath_dev_err(dd, "IBUC Parity still set after RST\n");
266 dd->ipath_hwerrmask &=
267 ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR;
268 }
269 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
270 dd->ipath_hwerrmask);
271 }
272
273bail:
274 return ret;
275}
276
277static void ipath_sd_trimdone_monitor(struct ipath_devdata *dd,
278 const char *where)
279{
280 int ret, chn, baduns;
281 u64 val;
282
283 if (!where)
284 where = "?";
285
286 /* give time for reset to settle out in EPB */
287 udelay(2);
288
289 ret = ipath_resync_ibepb(dd);
290 if (ret < 0)
291 ipath_dev_err(dd, "not able to re-sync IB EPB (%s)\n", where);
292
293 /* Do "sacrificial read" to get EPB in sane state after reset */
294 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_CTRL2(0), 0, 0);
295 if (ret < 0)
296 ipath_dev_err(dd, "Failed TRIMDONE 1st read, (%s)\n", where);
297
298 /* Check/show "summary" Trim-done bit in IBCStatus */
299 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
300 if (val & (1ULL << 11))
301 ipath_cdbg(VERBOSE, "IBCS TRIMDONE set (%s)\n", where);
302 else
303 ipath_dev_err(dd, "IBCS TRIMDONE clear (%s)\n", where);
304
305 udelay(2);
306
307 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80, 0x80);
308 if (ret < 0)
309 ipath_dev_err(dd, "Failed Dummy RMW, (%s)\n", where);
310 udelay(10);
311
312 baduns = 0;
313
314 for (chn = 3; chn >= 0; --chn) {
315 /* Read CTRL reg for each channel to check TRIMDONE */
316 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
317 IB_CTRL2(chn), 0, 0);
318 if (ret < 0)
319 ipath_dev_err(dd, "Failed checking TRIMDONE, chn %d"
320 " (%s)\n", chn, where);
321
322 if (!(ret & 0x10)) {
323 int probe;
324 baduns |= (1 << chn);
325 ipath_dev_err(dd, "TRIMDONE cleared on chn %d (%02X)."
326 " (%s)\n", chn, ret, where);
327 probe = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
328 IB_PGUDP(0), 0, 0);
329 ipath_dev_err(dd, "probe is %d (%02X)\n",
330 probe, probe);
331 probe = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
332 IB_CTRL2(chn), 0, 0);
333 ipath_dev_err(dd, "re-read: %d (%02X)\n",
334 probe, probe);
335 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
336 IB_CTRL2(chn), 0x10, 0x10);
337 if (ret < 0)
338 ipath_dev_err(dd,
339 "Err on TRIMDONE rewrite1\n");
340 }
341 }
342 for (chn = 3; chn >= 0; --chn) {
343 /* Read CTRL reg for each channel to check TRIMDONE */
344 if (baduns & (1 << chn)) {
345 ipath_dev_err(dd,
346 "Reseting TRIMDONE on chn %d (%s)\n",
347 chn, where);
348 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
349 IB_CTRL2(chn), 0x10, 0x10);
350 if (ret < 0)
351 ipath_dev_err(dd, "Failed re-setting "
352 "TRIMDONE, chn %d (%s)\n",
353 chn, where);
354 }
355 }
356}
357
358/*
359 * Below is portion of IBA7220-specific bringup_serdes() that actually
360 * deals with registers and memory within the SerDes itself.
361 * Post IB uC code version 1.32.17, was_reset being 1 is not really
362 * informative, so we double-check.
363 */
364int ipath_sd7220_init(struct ipath_devdata *dd, int was_reset)
365{
366 int ret = 1; /* default to failure */
367 int first_reset;
368 int val_stat;
369
370 if (!was_reset) {
371 /* entered with reset not asserted, we need to do it */
372 ipath_ibsd_reset(dd, 1);
373 ipath_sd_trimdone_monitor(dd, "Driver-reload");
374 }
375
376 /* Substitute our deduced value for was_reset */
377 ret = ipath_ibsd_ucode_loaded(dd);
378 if (ret < 0) {
379 ret = 1;
380 goto done;
381 }
382 first_reset = !ret; /* First reset if IBSD uCode not yet loaded */
383
384 /*
385 * Alter some regs per vendor latest doc, reset-defaults
386 * are not right for IB.
387 */
388 ret = ipath_sd_early(dd);
389 if (ret < 0) {
390 ipath_dev_err(dd, "Failed to set IB SERDES early defaults\n");
391 ret = 1;
392 goto done;
393 }
394
395 /*
396 * Set DAC manual trim IB.
397 * We only do this once after chip has been reset (usually
398 * same as once per system boot).
399 */
400 if (first_reset) {
401 ret = ipath_sd_dactrim(dd);
402 if (ret < 0) {
403 ipath_dev_err(dd, "Failed IB SERDES DAC trim\n");
404 ret = 1;
405 goto done;
406 }
407 }
408
409 /*
410 * Set various registers (DDS and RXEQ) that will be
411 * controlled by IBC (in 1.2 mode) to reasonable preset values
412 * Calling the "internal" version avoids the "check for needed"
413 * and "trimdone monitor" that might be counter-productive.
414 */
415 ret = ipath_internal_presets(dd);
416 if (ret < 0) {
417 ipath_dev_err(dd, "Failed to set IB SERDES presets\n");
418 ret = 1;
419 goto done;
420 }
421 ret = ipath_sd_trimself(dd, 0x80);
422 if (ret < 0) {
423 ipath_dev_err(dd, "Failed to set IB SERDES TRIMSELF\n");
424 ret = 1;
425 goto done;
426 }
427
428 /* Load image, then try to verify */
429 ret = 0; /* Assume success */
430 if (first_reset) {
431 int vfy;
432 int trim_done;
433 ipath_dbg("SerDes uC was reset, reloading PRAM\n");
434 ret = ipath_sd7220_ib_load(dd);
435 if (ret < 0) {
436 ipath_dev_err(dd, "Failed to load IB SERDES image\n");
437 ret = 1;
438 goto done;
439 }
440
441 /* Loaded image, try to verify */
442 vfy = ipath_sd7220_ib_vfy(dd);
443 if (vfy != ret) {
444 ipath_dev_err(dd, "SERDES PRAM VFY failed\n");
445 ret = 1;
446 goto done;
447 }
448 /*
449 * Loaded and verified. Almost good...
450 * hold "success" in ret
451 */
452 ret = 0;
453
454 /*
455 * Prev steps all worked, continue bringup
456 * De-assert RESET to uC, only in first reset, to allow
457 * trimming.
458 *
459 * Since our default setup sets START_EQ1 to
460 * PRESET, we need to clear that for this very first run.
461 */
462 ret = ibsd_mod_allchnls(dd, START_EQ1(0), 0, 0x38);
463 if (ret < 0) {
464 ipath_dev_err(dd, "Failed clearing START_EQ1\n");
465 ret = 1;
466 goto done;
467 }
468
469 ipath_ibsd_reset(dd, 0);
470 /*
471 * If this is not the first reset, trimdone should be set
472 * already.
473 */
474 trim_done = ipath_sd_trimdone_poll(dd);
475 /*
476 * Whether or not trimdone succeeded, we need to put the
477 * uC back into reset to avoid a possible fight with the
478 * IBC state-machine.
479 */
480 ipath_ibsd_reset(dd, 1);
481
482 if (!trim_done) {
483 ipath_dev_err(dd, "No TRIMDONE seen\n");
484 ret = 1;
485 goto done;
486 }
487
488 ipath_sd_trimdone_monitor(dd, "First-reset");
489 /* Remember so we do not re-do the load, dactrim, etc. */
490 dd->serdes_first_init_done = 1;
491 }
492 /*
493 * Setup for channel training and load values for
494 * RxEq and DDS in tables used by IBC in IB1.2 mode
495 */
496
497 val_stat = ipath_sd_setvals(dd);
498 if (val_stat < 0)
499 ret = 1;
500done:
501 /* start relock timer regardless, but start at 1 second */
502 ipath_set_relock_poll(dd, -1);
503 return ret;
504}
505
506#define EPB_ACC_REQ 1
507#define EPB_ACC_GNT 0x100
508#define EPB_DATA_MASK 0xFF
509#define EPB_RD (1ULL << 24)
510#define EPB_TRANS_RDY (1ULL << 31)
511#define EPB_TRANS_ERR (1ULL << 30)
512#define EPB_TRANS_TRIES 5
513
514/*
515 * query, claim, release ownership of the EPB (External Parallel Bus)
516 * for a specified SERDES.
517 * the "claim" parameter is >0 to claim, <0 to release, 0 to query.
518 * Returns <0 for errors, >0 if we had ownership, else 0.
519 */
520static int epb_access(struct ipath_devdata *dd, int sdnum, int claim)
521{
522 u16 acc;
523 u64 accval;
524 int owned = 0;
525 u64 oct_sel = 0;
526
527 switch (sdnum) {
528 case IB_7220_SERDES :
529 /*
530 * The IB SERDES "ownership" is fairly simple. A single each
531 * request/grant.
532 */
533 acc = dd->ipath_kregs->kr_ib_epbacc;
534 break;
535 case PCIE_SERDES0 :
536 case PCIE_SERDES1 :
537 /* PCIe SERDES has two "octants", need to select which */
538 acc = dd->ipath_kregs->kr_pcie_epbacc;
539 oct_sel = (2 << (sdnum - PCIE_SERDES0));
540 break;
541 default :
542 return 0;
543 }
544
545 /* Make sure any outstanding transaction was seen */
546 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
547 udelay(15);
548
549 accval = ipath_read_kreg32(dd, acc);
550
551 owned = !!(accval & EPB_ACC_GNT);
552 if (claim < 0) {
553 /* Need to release */
554 u64 pollval;
555 /*
556 * The only writeable bits are the request and CS.
557 * Both should be clear
558 */
559 u64 newval = 0;
560 ipath_write_kreg(dd, acc, newval);
561 /* First read after write is not trustworthy */
562 pollval = ipath_read_kreg32(dd, acc);
563 udelay(5);
564 pollval = ipath_read_kreg32(dd, acc);
565 if (pollval & EPB_ACC_GNT)
566 owned = -1;
567 } else if (claim > 0) {
568 /* Need to claim */
569 u64 pollval;
570 u64 newval = EPB_ACC_REQ | oct_sel;
571 ipath_write_kreg(dd, acc, newval);
572 /* First read after write is not trustworthy */
573 pollval = ipath_read_kreg32(dd, acc);
574 udelay(5);
575 pollval = ipath_read_kreg32(dd, acc);
576 if (!(pollval & EPB_ACC_GNT))
577 owned = -1;
578 }
579 return owned;
580}
581
582/*
583 * Lemma to deal with race condition of write..read to epb regs
584 */
585static int epb_trans(struct ipath_devdata *dd, u16 reg, u64 i_val, u64 *o_vp)
586{
587 int tries;
588 u64 transval;
589
590
591 ipath_write_kreg(dd, reg, i_val);
592 /* Throw away first read, as RDY bit may be stale */
593 transval = ipath_read_kreg64(dd, reg);
594
595 for (tries = EPB_TRANS_TRIES; tries; --tries) {
596 transval = ipath_read_kreg32(dd, reg);
597 if (transval & EPB_TRANS_RDY)
598 break;
599 udelay(5);
600 }
601 if (transval & EPB_TRANS_ERR)
602 return -1;
603 if (tries > 0 && o_vp)
604 *o_vp = transval;
605 return tries;
606}
607
608/**
609 *
610 * ipath_sd7220_reg_mod - modify SERDES register
611 * @dd: the infinipath device
612 * @sdnum: which SERDES to access
613 * @loc: location - channel, element, register, as packed by EPB_LOC() macro.
614 * @wd: Write Data - value to set in register
615 * @mask: ones where data should be spliced into reg.
616 *
617 * Basic register read/modify/write, with un-needed accesses elided. That is,
618 * a mask of zero will prevent write, while a mask of 0xFF will prevent read.
619 * returns current (presumed, if a write was done) contents of selected
620 * register, or <0 if errors.
621 */
622static int ipath_sd7220_reg_mod(struct ipath_devdata *dd, int sdnum, u32 loc,
623 u32 wd, u32 mask)
624{
625 u16 trans;
626 u64 transval;
627 int owned;
628 int tries, ret;
629 unsigned long flags;
630
631 switch (sdnum) {
632 case IB_7220_SERDES :
633 trans = dd->ipath_kregs->kr_ib_epbtrans;
634 break;
635 case PCIE_SERDES0 :
636 case PCIE_SERDES1 :
637 trans = dd->ipath_kregs->kr_pcie_epbtrans;
638 break;
639 default :
640 return -1;
641 }
642
643 /*
644 * All access is locked in software (vs other host threads) and
645 * hardware (vs uC access).
646 */
647 spin_lock_irqsave(&dd->ipath_sdepb_lock, flags);
648
649 owned = epb_access(dd, sdnum, 1);
650 if (owned < 0) {
651 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
652 return -1;
653 }
654 ret = 0;
655 for (tries = EPB_TRANS_TRIES; tries; --tries) {
656 transval = ipath_read_kreg32(dd, trans);
657 if (transval & EPB_TRANS_RDY)
658 break;
659 udelay(5);
660 }
661
662 if (tries > 0) {
663 tries = 1; /* to make read-skip work */
664 if (mask != 0xFF) {
665 /*
666 * Not a pure write, so need to read.
667 * loc encodes chip-select as well as address
668 */
669 transval = loc | EPB_RD;
670 tries = epb_trans(dd, trans, transval, &transval);
671 }
672 if (tries > 0 && mask != 0) {
673 /*
674 * Not a pure read, so need to write.
675 */
676 wd = (wd & mask) | (transval & ~mask);
677 transval = loc | (wd & EPB_DATA_MASK);
678 tries = epb_trans(dd, trans, transval, &transval);
679 }
680 }
681 /* else, failed to see ready, what error-handling? */
682
683 /*
684 * Release bus. Failure is an error.
685 */
686 if (epb_access(dd, sdnum, -1) < 0)
687 ret = -1;
688 else
689 ret = transval & EPB_DATA_MASK;
690
691 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
692 if (tries <= 0)
693 ret = -1;
694 return ret;
695}
696
697#define EPB_ROM_R (2)
698#define EPB_ROM_W (1)
699/*
700 * Below, all uC-related, use appropriate UC_CS, depending
701 * on which SerDes is used.
702 */
703#define EPB_UC_CTL EPB_LOC(6, 0, 0)
704#define EPB_MADDRL EPB_LOC(6, 0, 2)
705#define EPB_MADDRH EPB_LOC(6, 0, 3)
706#define EPB_ROMDATA EPB_LOC(6, 0, 4)
707#define EPB_RAMDATA EPB_LOC(6, 0, 5)
708
709/* Transfer date to/from uC Program RAM of IB or PCIe SerDes */
710static int ipath_sd7220_ram_xfer(struct ipath_devdata *dd, int sdnum, u32 loc,
711 u8 *buf, int cnt, int rd_notwr)
712{
713 u16 trans;
714 u64 transval;
715 u64 csbit;
716 int owned;
717 int tries;
718 int sofar;
719 int addr;
720 int ret;
721 unsigned long flags;
722 const char *op;
723
724 /* Pick appropriate transaction reg and "Chip select" for this serdes */
725 switch (sdnum) {
726 case IB_7220_SERDES :
727 csbit = 1ULL << EPB_IB_UC_CS_SHF;
728 trans = dd->ipath_kregs->kr_ib_epbtrans;
729 break;
730 case PCIE_SERDES0 :
731 case PCIE_SERDES1 :
732 /* PCIe SERDES has uC "chip select" in different bit, too */
733 csbit = 1ULL << EPB_PCIE_UC_CS_SHF;
734 trans = dd->ipath_kregs->kr_pcie_epbtrans;
735 break;
736 default :
737 return -1;
738 }
739
740 op = rd_notwr ? "Rd" : "Wr";
741 spin_lock_irqsave(&dd->ipath_sdepb_lock, flags);
742
743 owned = epb_access(dd, sdnum, 1);
744 if (owned < 0) {
745 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
746 ipath_dbg("Could not get %s access to %s EPB: %X, loc %X\n",
747 op, (sdnum == IB_7220_SERDES) ? "IB" : "PCIe",
748 owned, loc);
749 return -1;
750 }
751
752 /*
753 * In future code, we may need to distinguish several address ranges,
754 * and select various memories based on this. For now, just trim
755 * "loc" (location including address and memory select) to
756 * "addr" (address within memory). we will only support PRAM
757 * The memory is 8KB.
758 */
759 addr = loc & 0x1FFF;
760 for (tries = EPB_TRANS_TRIES; tries; --tries) {
761 transval = ipath_read_kreg32(dd, trans);
762 if (transval & EPB_TRANS_RDY)
763 break;
764 udelay(5);
765 }
766
767 sofar = 0;
768 if (tries <= 0)
769 ipath_dbg("No initial RDY on EPB access request\n");
770 else {
771 /*
772 * Every "memory" access is doubly-indirect.
773 * We set two bytes of address, then read/write
774 * one or mores bytes of data.
775 */
776
777 /* First, we set control to "Read" or "Write" */
778 transval = csbit | EPB_UC_CTL |
779 (rd_notwr ? EPB_ROM_R : EPB_ROM_W);
780 tries = epb_trans(dd, trans, transval, &transval);
781 if (tries <= 0)
782 ipath_dbg("No EPB response to uC %s cmd\n", op);
783 while (tries > 0 && sofar < cnt) {
784 if (!sofar) {
785 /* Only set address at start of chunk */
786 int addrbyte = (addr + sofar) >> 8;
787 transval = csbit | EPB_MADDRH | addrbyte;
788 tries = epb_trans(dd, trans, transval,
789 &transval);
790 if (tries <= 0) {
791 ipath_dbg("No EPB response ADDRH\n");
792 break;
793 }
794 addrbyte = (addr + sofar) & 0xFF;
795 transval = csbit | EPB_MADDRL | addrbyte;
796 tries = epb_trans(dd, trans, transval,
797 &transval);
798 if (tries <= 0) {
799 ipath_dbg("No EPB response ADDRL\n");
800 break;
801 }
802 }
803
804 if (rd_notwr)
805 transval = csbit | EPB_ROMDATA | EPB_RD;
806 else
807 transval = csbit | EPB_ROMDATA | buf[sofar];
808 tries = epb_trans(dd, trans, transval, &transval);
809 if (tries <= 0) {
810 ipath_dbg("No EPB response DATA\n");
811 break;
812 }
813 if (rd_notwr)
814 buf[sofar] = transval & EPB_DATA_MASK;
815 ++sofar;
816 }
817 /* Finally, clear control-bit for Read or Write */
818 transval = csbit | EPB_UC_CTL;
819 tries = epb_trans(dd, trans, transval, &transval);
820 if (tries <= 0)
821 ipath_dbg("No EPB response to drop of uC %s cmd\n", op);
822 }
823
824 ret = sofar;
825 /* Release bus. Failure is an error */
826 if (epb_access(dd, sdnum, -1) < 0)
827 ret = -1;
828
829 spin_unlock_irqrestore(&dd->ipath_sdepb_lock, flags);
830 if (tries <= 0) {
831 ipath_dbg("SERDES PRAM %s failed after %d bytes\n", op, sofar);
832 ret = -1;
833 }
834 return ret;
835}
836
837#define PROG_CHUNK 64
838
839int ipath_sd7220_prog_ld(struct ipath_devdata *dd, int sdnum,
840 u8 *img, int len, int offset)
841{
842 int cnt, sofar, req;
843
844 sofar = 0;
845 while (sofar < len) {
846 req = len - sofar;
847 if (req > PROG_CHUNK)
848 req = PROG_CHUNK;
849 cnt = ipath_sd7220_ram_xfer(dd, sdnum, offset + sofar,
850 img + sofar, req, 0);
851 if (cnt < req) {
852 sofar = -1;
853 break;
854 }
855 sofar += req;
856 }
857 return sofar;
858}
859
860#define VFY_CHUNK 64
861#define SD_PRAM_ERROR_LIMIT 42
862
863int ipath_sd7220_prog_vfy(struct ipath_devdata *dd, int sdnum,
864 const u8 *img, int len, int offset)
865{
866 int cnt, sofar, req, idx, errors;
867 unsigned char readback[VFY_CHUNK];
868
869 errors = 0;
870 sofar = 0;
871 while (sofar < len) {
872 req = len - sofar;
873 if (req > VFY_CHUNK)
874 req = VFY_CHUNK;
875 cnt = ipath_sd7220_ram_xfer(dd, sdnum, sofar + offset,
876 readback, req, 1);
877 if (cnt < req) {
878 /* failed in read itself */
879 sofar = -1;
880 break;
881 }
882 for (idx = 0; idx < cnt; ++idx) {
883 if (readback[idx] != img[idx+sofar])
884 ++errors;
885 }
886 sofar += cnt;
887 }
888 return errors ? -errors : sofar;
889}
890
891/* IRQ not set up at this point in init, so we poll. */
892#define IB_SERDES_TRIM_DONE (1ULL << 11)
893#define TRIM_TMO (30)
894
895static int ipath_sd_trimdone_poll(struct ipath_devdata *dd)
896{
897 int trim_tmo, ret;
898 uint64_t val;
899
900 /*
901 * Default to failure, so IBC will not start
902 * without IB_SERDES_TRIM_DONE.
903 */
904 ret = 0;
905 for (trim_tmo = 0; trim_tmo < TRIM_TMO; ++trim_tmo) {
906 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
907 if (val & IB_SERDES_TRIM_DONE) {
908 ipath_cdbg(VERBOSE, "TRIMDONE after %d\n", trim_tmo);
909 ret = 1;
910 break;
911 }
912 msleep(10);
913 }
914 if (trim_tmo >= TRIM_TMO) {
915 ipath_dev_err(dd, "No TRIMDONE in %d tries\n", trim_tmo);
916 ret = 0;
917 }
918 return ret;
919}
920
921#define TX_FAST_ELT (9)
922
923/*
924 * Set the "negotiation" values for SERDES. These are used by the IB1.2
925 * link negotiation. Macros below are attempt to keep the values a
926 * little more human-editable.
927 * First, values related to Drive De-emphasis Settings.
928 */
929
930#define NUM_DDS_REGS 6
931#define DDS_REG_MAP 0x76A910 /* LSB-first list of regs (in elt 9) to mod */
932
933#define DDS_VAL(amp_d, main_d, ipst_d, ipre_d, amp_s, main_s, ipst_s, ipre_s) \
934 { { ((amp_d & 0x1F) << 1) | 1, ((amp_s & 0x1F) << 1) | 1, \
935 (main_d << 3) | 4 | (ipre_d >> 2), \
936 (main_s << 3) | 4 | (ipre_s >> 2), \
937 ((ipst_d & 0xF) << 1) | ((ipre_d & 3) << 6) | 0x21, \
938 ((ipst_s & 0xF) << 1) | ((ipre_s & 3) << 6) | 0x21 } }
939
940static struct dds_init {
941 uint8_t reg_vals[NUM_DDS_REGS];
942} dds_init_vals[] = {
943 /* DDR(FDR) SDR(HDR) */
944 /* Vendor recommends below for 3m cable */
945#define DDS_3M 0
946 DDS_VAL(31, 19, 12, 0, 29, 22, 9, 0),
947 DDS_VAL(31, 12, 15, 4, 31, 15, 15, 1),
948 DDS_VAL(31, 13, 15, 3, 31, 16, 15, 0),
949 DDS_VAL(31, 14, 15, 2, 31, 17, 14, 0),
950 DDS_VAL(31, 15, 15, 1, 31, 18, 13, 0),
951 DDS_VAL(31, 16, 15, 0, 31, 19, 12, 0),
952 DDS_VAL(31, 17, 14, 0, 31, 20, 11, 0),
953 DDS_VAL(31, 18, 13, 0, 30, 21, 10, 0),
954 DDS_VAL(31, 20, 11, 0, 28, 23, 8, 0),
955 DDS_VAL(31, 21, 10, 0, 27, 24, 7, 0),
956 DDS_VAL(31, 22, 9, 0, 26, 25, 6, 0),
957 DDS_VAL(30, 23, 8, 0, 25, 26, 5, 0),
958 DDS_VAL(29, 24, 7, 0, 23, 27, 4, 0),
959 /* Vendor recommends below for 1m cable */
960#define DDS_1M 13
961 DDS_VAL(28, 25, 6, 0, 21, 28, 3, 0),
962 DDS_VAL(27, 26, 5, 0, 19, 29, 2, 0),
963 DDS_VAL(25, 27, 4, 0, 17, 30, 1, 0)
964};
965
966/*
967 * Next, values related to Receive Equalization.
968 * In comments, FDR (Full) is IB DDR, HDR (Half) is IB SDR
969 */
970/* Hardware packs an element number and register address thus: */
971#define RXEQ_INIT_RDESC(elt, addr) (((elt) & 0xF) | ((addr) << 4))
972#define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \
973 {RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} }
974
975#define RXEQ_VAL_ALL(elt, adr, val) \
976 {RXEQ_INIT_RDESC((elt), (adr)), {(val), (val), (val), (val)} }
977
978#define RXEQ_SDR_DFELTH 0
979#define RXEQ_SDR_TLTH 0
980#define RXEQ_SDR_G1CNT_Z1CNT 0x11
981#define RXEQ_SDR_ZCNT 23
982
983static struct rxeq_init {
984 u16 rdesc; /* in form used in SerDesDDSRXEQ */
985 u8 rdata[4];
986} rxeq_init_vals[] = {
987 /* Set Rcv Eq. to Preset node */
988 RXEQ_VAL_ALL(7, 0x27, 0x10),
989 /* Set DFELTHFDR/HDR thresholds */
990 RXEQ_VAL(7, 8, 0, 0, 0, 0), /* FDR */
991 RXEQ_VAL(7, 0x21, 0, 0, 0, 0), /* HDR */
992 /* Set TLTHFDR/HDR threshold */
993 RXEQ_VAL(7, 9, 2, 2, 2, 2), /* FDR */
994 RXEQ_VAL(7, 0x23, 2, 2, 2, 2), /* HDR */
995 /* Set Preamp setting 2 (ZFR/ZCNT) */
996 RXEQ_VAL(7, 0x1B, 12, 12, 12, 12), /* FDR */
997 RXEQ_VAL(7, 0x1C, 12, 12, 12, 12), /* HDR */
998 /* Set Preamp DC gain and Setting 1 (GFR/GHR) */
999 RXEQ_VAL(7, 0x1E, 0x10, 0x10, 0x10, 0x10), /* FDR */
1000 RXEQ_VAL(7, 0x1F, 0x10, 0x10, 0x10, 0x10), /* HDR */
1001 /* Toggle RELOCK (in VCDL_CTRL0) to lock to data */
1002 RXEQ_VAL_ALL(6, 6, 0x20), /* Set D5 High */
1003 RXEQ_VAL_ALL(6, 6, 0), /* Set D5 Low */
1004};
1005
1006/* There are 17 values from vendor, but IBC only accesses the first 16 */
1007#define DDS_ROWS (16)
1008#define RXEQ_ROWS ARRAY_SIZE(rxeq_init_vals)
1009
1010static int ipath_sd_setvals(struct ipath_devdata *dd)
1011{
1012 int idx, midx;
1013 int min_idx; /* Minimum index for this portion of table */
1014 uint32_t dds_reg_map;
1015 u64 __iomem *taddr, *iaddr;
1016 uint64_t data;
1017 uint64_t sdctl;
1018
1019 taddr = dd->ipath_kregbase + KR_IBSerDesMappTable;
1020 iaddr = dd->ipath_kregbase + dd->ipath_kregs->kr_ib_ddsrxeq;
1021
1022 /*
1023 * Init the DDS section of the table.
1024 * Each "row" of the table provokes NUM_DDS_REG writes, to the
1025 * registers indicated in DDS_REG_MAP.
1026 */
1027 sdctl = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibserdesctrl);
1028 sdctl = (sdctl & ~(0x1f << 8)) | (NUM_DDS_REGS << 8);
1029 sdctl = (sdctl & ~(0x1f << 13)) | (RXEQ_ROWS << 13);
1030 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibserdesctrl, sdctl);
1031
1032 /*
1033 * Iterate down table within loop for each register to store.
1034 */
1035 dds_reg_map = DDS_REG_MAP;
1036 for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1037 data = ((dds_reg_map & 0xF) << 4) | TX_FAST_ELT;
1038 writeq(data, iaddr + idx);
1039 mmiowb();
1040 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1041 dds_reg_map >>= 4;
1042 for (midx = 0; midx < DDS_ROWS; ++midx) {
1043 u64 __iomem *daddr = taddr + ((midx << 4) + idx);
1044 data = dds_init_vals[midx].reg_vals[idx];
1045 writeq(data, daddr);
1046 mmiowb();
1047 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1048 } /* End inner for (vals for this reg, each row) */
1049 } /* end outer for (regs to be stored) */
1050
1051 /*
1052 * Init the RXEQ section of the table. As explained above the table
1053 * rxeq_init_vals[], this runs in a different order, as the pattern
1054 * of register references is more complex, but there are only
1055 * four "data" values per register.
1056 */
1057 min_idx = idx; /* RXEQ indices pick up where DDS left off */
1058 taddr += 0x100; /* RXEQ data is in second half of table */
1059 /* Iterate through RXEQ register addresses */
1060 for (idx = 0; idx < RXEQ_ROWS; ++idx) {
1061 int didx; /* "destination" */
1062 int vidx;
1063
1064 /* didx is offset by min_idx to address RXEQ range of regs */
1065 didx = idx + min_idx;
1066 /* Store the next RXEQ register address */
1067 writeq(rxeq_init_vals[idx].rdesc, iaddr + didx);
1068 mmiowb();
1069 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1070 /* Iterate through RXEQ values */
1071 for (vidx = 0; vidx < 4; vidx++) {
1072 data = rxeq_init_vals[idx].rdata[vidx];
1073 writeq(data, taddr + (vidx << 6) + idx);
1074 mmiowb();
1075 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1076 }
1077 } /* end outer for (Reg-writes for RXEQ) */
1078 return 0;
1079}
1080
1081#define CMUCTRL5 EPB_LOC(7, 0, 0x15)
1082#define RXHSCTRL0(chan) EPB_LOC(chan, 6, 0)
1083#define VCDL_DAC2(chan) EPB_LOC(chan, 6, 5)
1084#define VCDL_CTRL0(chan) EPB_LOC(chan, 6, 6)
1085#define VCDL_CTRL2(chan) EPB_LOC(chan, 6, 8)
1086#define START_EQ2(chan) EPB_LOC(chan, 7, 0x28)
1087
1088static int ibsd_sto_noisy(struct ipath_devdata *dd, int loc, int val, int mask)
1089{
1090 int ret = -1;
1091 int sloc; /* shifted loc, for messages */
1092
1093 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1094 sloc = loc >> EPB_ADDR_SHF;
1095
1096 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, mask);
1097 if (ret < 0)
1098 ipath_dev_err(dd, "Write failed: elt %d,"
1099 " addr 0x%X, chnl %d, val 0x%02X, mask 0x%02X\n",
1100 (sloc & 0xF), (sloc >> 9) & 0x3f, (sloc >> 4) & 7,
1101 val & 0xFF, mask & 0xFF);
1102 return ret;
1103}
1104
1105/*
1106 * Repeat a "store" across all channels of the IB SerDes.
1107 * Although nominally it inherits the "read value" of the last
1108 * channel it modified, the only really useful return is <0 for
1109 * failure, >= 0 for success. The parameter 'loc' is assumed to
1110 * be the location for the channel-0 copy of the register to
1111 * be modified.
1112 */
1113static int ibsd_mod_allchnls(struct ipath_devdata *dd, int loc, int val,
1114 int mask)
1115{
1116 int ret = -1;
1117 int chnl;
1118
1119 if (loc & EPB_GLOBAL_WR) {
1120 /*
1121 * Our caller has assured us that we can set all four
1122 * channels at once. Trust that. If mask is not 0xFF,
1123 * we will read the _specified_ channel for our starting
1124 * value.
1125 */
1126 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1127 chnl = (loc >> (4 + EPB_ADDR_SHF)) & 7;
1128 if (mask != 0xFF) {
1129 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES,
1130 loc & ~EPB_GLOBAL_WR, 0, 0);
1131 if (ret < 0) {
1132 int sloc = loc >> EPB_ADDR_SHF;
1133 ipath_dev_err(dd, "pre-read failed: elt %d,"
1134 " addr 0x%X, chnl %d\n", (sloc & 0xF),
1135 (sloc >> 9) & 0x3f, chnl);
1136 return ret;
1137 }
1138 val = (ret & ~mask) | (val & mask);
1139 }
1140 loc &= ~(7 << (4+EPB_ADDR_SHF));
1141 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF);
1142 if (ret < 0) {
1143 int sloc = loc >> EPB_ADDR_SHF;
1144 ipath_dev_err(dd, "Global WR failed: elt %d,"
1145 " addr 0x%X, val %02X\n",
1146 (sloc & 0xF), (sloc >> 9) & 0x3f, val);
1147 }
1148 return ret;
1149 }
1150 /* Clear "channel" and set CS so we can simply iterate */
1151 loc &= ~(7 << (4+EPB_ADDR_SHF));
1152 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1153 for (chnl = 0; chnl < 4; ++chnl) {
1154 int cloc;
1155 cloc = loc | (chnl << (4+EPB_ADDR_SHF));
1156 ret = ipath_sd7220_reg_mod(dd, IB_7220_SERDES, cloc, val, mask);
1157 if (ret < 0) {
1158 int sloc = loc >> EPB_ADDR_SHF;
1159 ipath_dev_err(dd, "Write failed: elt %d,"
1160 " addr 0x%X, chnl %d, val 0x%02X,"
1161 " mask 0x%02X\n",
1162 (sloc & 0xF), (sloc >> 9) & 0x3f, chnl,
1163 val & 0xFF, mask & 0xFF);
1164 break;
1165 }
1166 }
1167 return ret;
1168}
1169
1170/*
1171 * Set the Tx values normally modified by IBC in IB1.2 mode to default
1172 * values, as gotten from first row of init table.
1173 */
1174static int set_dds_vals(struct ipath_devdata *dd, struct dds_init *ddi)
1175{
1176 int ret;
1177 int idx, reg, data;
1178 uint32_t regmap;
1179
1180 regmap = DDS_REG_MAP;
1181 for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1182 reg = (regmap & 0xF);
1183 regmap >>= 4;
1184 data = ddi->reg_vals[idx];
1185 /* Vendor says RMW not needed for these regs, use 0xFF mask */
1186 ret = ibsd_mod_allchnls(dd, EPB_LOC(0, 9, reg), data, 0xFF);
1187 if (ret < 0)
1188 break;
1189 }
1190 return ret;
1191}
1192
1193/*
1194 * Set the Rx values normally modified by IBC in IB1.2 mode to default
1195 * values, as gotten from selected column of init table.
1196 */
1197static int set_rxeq_vals(struct ipath_devdata *dd, int vsel)
1198{
1199 int ret;
1200 int ridx;
1201 int cnt = ARRAY_SIZE(rxeq_init_vals);
1202
1203 for (ridx = 0; ridx < cnt; ++ridx) {
1204 int elt, reg, val, loc;
1205 elt = rxeq_init_vals[ridx].rdesc & 0xF;
1206 reg = rxeq_init_vals[ridx].rdesc >> 4;
1207 loc = EPB_LOC(0, elt, reg);
1208 val = rxeq_init_vals[ridx].rdata[vsel];
1209 /* mask of 0xFF, because hardware does full-byte store. */
1210 ret = ibsd_mod_allchnls(dd, loc, val, 0xFF);
1211 if (ret < 0)
1212 break;
1213 }
1214 return ret;
1215}
1216
1217/*
1218 * Set the default values (row 0) for DDR Driver Demphasis.
1219 * we do this initially and whenever we turn off IB-1.2
1220 * The "default" values for Rx equalization are also stored to
1221 * SerDes registers. Formerly (and still default), we used set 2.
1222 * For experimenting with cables and link-partners, we allow changing
1223 * that via a module parameter.
1224 */
1225static unsigned ipath_rxeq_set = 2;
1226module_param_named(rxeq_default_set, ipath_rxeq_set, uint,
1227 S_IWUSR | S_IRUGO);
1228MODULE_PARM_DESC(rxeq_default_set,
1229 "Which set [0..3] of Rx Equalization values is default");
1230
1231static int ipath_internal_presets(struct ipath_devdata *dd)
1232{
1233 int ret = 0;
1234
1235 ret = set_dds_vals(dd, dds_init_vals + DDS_3M);
1236
1237 if (ret < 0)
1238 ipath_dev_err(dd, "Failed to set default DDS values\n");
1239 ret = set_rxeq_vals(dd, ipath_rxeq_set & 3);
1240 if (ret < 0)
1241 ipath_dev_err(dd, "Failed to set default RXEQ values\n");
1242 return ret;
1243}
1244
1245int ipath_sd7220_presets(struct ipath_devdata *dd)
1246{
1247 int ret = 0;
1248
1249 if (!dd->ipath_presets_needed)
1250 return ret;
1251 dd->ipath_presets_needed = 0;
1252 /* Assert uC reset, so we don't clash with it. */
1253 ipath_ibsd_reset(dd, 1);
1254 udelay(2);
1255 ipath_sd_trimdone_monitor(dd, "link-down");
1256
1257 ret = ipath_internal_presets(dd);
1258return ret;
1259}
1260
1261static int ipath_sd_trimself(struct ipath_devdata *dd, int val)
1262{
1263 return ibsd_sto_noisy(dd, CMUCTRL5, val, 0xFF);
1264}
1265
1266static int ipath_sd_early(struct ipath_devdata *dd)
1267{
1268 int ret = -1; /* Default failed */
1269 int chnl;
1270
1271 for (chnl = 0; chnl < 4; ++chnl) {
1272 ret = ibsd_sto_noisy(dd, RXHSCTRL0(chnl), 0xD4, 0xFF);
1273 if (ret < 0)
1274 goto bail;
1275 }
1276 for (chnl = 0; chnl < 4; ++chnl) {
1277 ret = ibsd_sto_noisy(dd, VCDL_DAC2(chnl), 0x2D, 0xFF);
1278 if (ret < 0)
1279 goto bail;
1280 }
1281 /* more fine-tuning of what will be default */
1282 for (chnl = 0; chnl < 4; ++chnl) {
1283 ret = ibsd_sto_noisy(dd, VCDL_CTRL2(chnl), 3, 0xF);
1284 if (ret < 0)
1285 goto bail;
1286 }
1287 for (chnl = 0; chnl < 4; ++chnl) {
1288 ret = ibsd_sto_noisy(dd, START_EQ1(chnl), 0x10, 0xFF);
1289 if (ret < 0)
1290 goto bail;
1291 }
1292 for (chnl = 0; chnl < 4; ++chnl) {
1293 ret = ibsd_sto_noisy(dd, START_EQ2(chnl), 0x30, 0xFF);
1294 if (ret < 0)
1295 goto bail;
1296 }
1297bail:
1298 return ret;
1299}
1300
1301#define BACTRL(chnl) EPB_LOC(chnl, 6, 0x0E)
1302#define LDOUTCTRL1(chnl) EPB_LOC(chnl, 7, 6)
1303#define RXHSSTATUS(chnl) EPB_LOC(chnl, 6, 0xF)
1304
1305static int ipath_sd_dactrim(struct ipath_devdata *dd)
1306{
1307 int ret = -1; /* Default failed */
1308 int chnl;
1309
1310 for (chnl = 0; chnl < 4; ++chnl) {
1311 ret = ibsd_sto_noisy(dd, BACTRL(chnl), 0x40, 0xFF);
1312 if (ret < 0)
1313 goto bail;
1314 }
1315 for (chnl = 0; chnl < 4; ++chnl) {
1316 ret = ibsd_sto_noisy(dd, LDOUTCTRL1(chnl), 0x04, 0xFF);
1317 if (ret < 0)
1318 goto bail;
1319 }
1320 for (chnl = 0; chnl < 4; ++chnl) {
1321 ret = ibsd_sto_noisy(dd, RXHSSTATUS(chnl), 0x04, 0xFF);
1322 if (ret < 0)
1323 goto bail;
1324 }
1325 /*
1326 * delay for max possible number of steps, with slop.
1327 * Each step is about 4usec.
1328 */
1329 udelay(415);
1330 for (chnl = 0; chnl < 4; ++chnl) {
1331 ret = ibsd_sto_noisy(dd, LDOUTCTRL1(chnl), 0x00, 0xFF);
1332 if (ret < 0)
1333 goto bail;
1334 }
1335bail:
1336 return ret;
1337}
1338
1339#define RELOCK_FIRST_MS 3
1340#define RXLSPPM(chan) EPB_LOC(chan, 0, 2)
1341void ipath_toggle_rclkrls(struct ipath_devdata *dd)
1342{
1343 int loc = RXLSPPM(0) | EPB_GLOBAL_WR;
1344 int ret;
1345
1346 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1347 if (ret < 0)
1348 ipath_dev_err(dd, "RCLKRLS failed to clear D7\n");
1349 else {
1350 udelay(1);
1351 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1352 }
1353 /* And again for good measure */
1354 udelay(1);
1355 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1356 if (ret < 0)
1357 ipath_dev_err(dd, "RCLKRLS failed to clear D7\n");
1358 else {
1359 udelay(1);
1360 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1361 }
1362 /* Now reset xgxs and IBC to complete the recovery */
1363 dd->ipath_f_xgxs_reset(dd);
1364}
1365
1366/*
1367 * Shut down the timer that polls for relock occasions, if needed
1368 * this is "hooked" from ipath_7220_quiet_serdes(), which is called
1369 * just before ipath_shutdown_device() in ipath_driver.c shuts down all
1370 * the other timers
1371 */
1372void ipath_shutdown_relock_poll(struct ipath_devdata *dd)
1373{
1374 struct ipath_relock *irp = &dd->ipath_relock_singleton;
1375 if (atomic_read(&irp->ipath_relock_timer_active)) {
1376 del_timer_sync(&irp->ipath_relock_timer);
1377 atomic_set(&irp->ipath_relock_timer_active, 0);
1378 }
1379}
1380
1381static unsigned ipath_relock_by_timer = 1;
1382module_param_named(relock_by_timer, ipath_relock_by_timer, uint,
1383 S_IWUSR | S_IRUGO);
1384MODULE_PARM_DESC(relock_by_timer, "Allow relock attempt if link not up");
1385
1386static void ipath_run_relock(unsigned long opaque)
1387{
1388 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
1389 struct ipath_relock *irp = &dd->ipath_relock_singleton;
1390 u64 val, ltstate;
1391
1392 if (!(dd->ipath_flags & IPATH_INITTED)) {
1393 /* Not yet up, just reenable the timer for later */
1394 irp->ipath_relock_interval = HZ;
1395 mod_timer(&irp->ipath_relock_timer, jiffies + HZ);
1396 return;
1397 }
1398
1399 /*
1400 * Check link-training state for "stuck" state.
1401 * if found, try relock and schedule another try at
1402 * exponentially growing delay, maxed at one second.
1403 * if not stuck, our work is done.
1404 */
1405 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
1406 ltstate = ipath_ib_linktrstate(dd, val);
1407
1408 if (ltstate <= INFINIPATH_IBCS_LT_STATE_CFGWAITRMT
1409 && ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
1410 int timeoff;
1411 /* Not up yet. Try again, if allowed by module-param */
1412 if (ipath_relock_by_timer) {
1413 if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)
1414 ipath_cdbg(VERBOSE, "Skip RELOCK in AUTONEG\n");
1415 else if (!(dd->ipath_flags & IPATH_IB_LINK_DISABLED)) {
1416 ipath_cdbg(VERBOSE, "RELOCK\n");
1417 ipath_toggle_rclkrls(dd);
1418 }
1419 }
1420 /* re-set timer for next check */
1421 timeoff = irp->ipath_relock_interval << 1;
1422 if (timeoff > HZ)
1423 timeoff = HZ;
1424 irp->ipath_relock_interval = timeoff;
1425
1426 mod_timer(&irp->ipath_relock_timer, jiffies + timeoff);
1427 } else {
1428 /* Up, so no more need to check so often */
1429 mod_timer(&irp->ipath_relock_timer, jiffies + HZ);
1430 }
1431}
1432
1433void ipath_set_relock_poll(struct ipath_devdata *dd, int ibup)
1434{
1435 struct ipath_relock *irp = &dd->ipath_relock_singleton;
1436
1437 if (ibup > 0) {
1438 /* we are now up, so relax timer to 1 second interval */
1439 if (atomic_read(&irp->ipath_relock_timer_active))
1440 mod_timer(&irp->ipath_relock_timer, jiffies + HZ);
1441 } else {
1442 /* Transition to down, (re-)set timer to short interval. */
1443 int timeout;
1444 timeout = (HZ * ((ibup == -1) ? 1000 : RELOCK_FIRST_MS))/1000;
1445 if (timeout == 0)
1446 timeout = 1;
1447 /* If timer has not yet been started, do so. */
1448 if (atomic_inc_return(&irp->ipath_relock_timer_active) == 1) {
1449 init_timer(&irp->ipath_relock_timer);
1450 irp->ipath_relock_timer.function = ipath_run_relock;
1451 irp->ipath_relock_timer.data = (unsigned long) dd;
1452 irp->ipath_relock_interval = timeout;
1453 irp->ipath_relock_timer.expires = jiffies + timeout;
1454 add_timer(&irp->ipath_relock_timer);
1455 } else {
1456 irp->ipath_relock_interval = timeout;
1457 mod_timer(&irp->ipath_relock_timer, jiffies + timeout);
1458 atomic_dec(&irp->ipath_relock_timer_active);
1459 }
1460 }
1461}
1462
diff --git a/drivers/infiniband/hw/ipath/ipath_sd7220_img.c b/drivers/infiniband/hw/ipath/ipath_sd7220_img.c
deleted file mode 100644
index 5ef59da9270..00000000000
--- a/drivers/infiniband/hw/ipath/ipath_sd7220_img.c
+++ /dev/null
@@ -1,1082 +0,0 @@
1/*
2 * Copyright (c) 2007, 2008 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33/*
34 * This file contains the memory image from the vendor, to be copied into
35 * the IB SERDES of the IBA7220 during initialization.
36 * The file also includes the two functions which use this image.
37 */
38#include <linux/pci.h>
39#include <linux/delay.h>
40
41#include "ipath_kernel.h"
42#include "ipath_registers.h"
43#include "ipath_7220.h"
44
45static unsigned char ipath_sd7220_ib_img[] = {
46/*0000*/0x02, 0x0A, 0x29, 0x02, 0x0A, 0x87, 0xE5, 0xE6,
47 0x30, 0xE6, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F,
48/*0010*/0x00, 0xE5, 0xE2, 0x30, 0xE4, 0x04, 0x7E, 0x01,
49 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x5F, 0x60, 0x08,
50/*0020*/0x53, 0xF9, 0xF7, 0xE4, 0xF5, 0xFE, 0x80, 0x08,
51 0x7F, 0x0A, 0x12, 0x17, 0x31, 0x12, 0x0E, 0xA2,
52/*0030*/0x75, 0xFC, 0x08, 0xE4, 0xF5, 0xFD, 0xE5, 0xE7,
53 0x20, 0xE7, 0x03, 0x43, 0xF9, 0x08, 0x22, 0x00,
54/*0040*/0x01, 0x20, 0x11, 0x00, 0x04, 0x20, 0x00, 0x75,
55 0x51, 0x01, 0xE4, 0xF5, 0x52, 0xF5, 0x53, 0xF5,
56/*0050*/0x52, 0xF5, 0x7E, 0x7F, 0x04, 0x02, 0x04, 0x38,
57 0xC2, 0x36, 0x05, 0x52, 0xE5, 0x52, 0xD3, 0x94,
58/*0060*/0x0C, 0x40, 0x05, 0x75, 0x52, 0x01, 0xD2, 0x36,
59 0x90, 0x07, 0x0C, 0x74, 0x07, 0xF0, 0xA3, 0x74,
60/*0070*/0xFF, 0xF0, 0xE4, 0xF5, 0x0C, 0xA3, 0xF0, 0x90,
61 0x07, 0x14, 0xF0, 0xA3, 0xF0, 0x75, 0x0B, 0x20,
62/*0080*/0xF5, 0x09, 0xE4, 0xF5, 0x08, 0xE5, 0x08, 0xD3,
63 0x94, 0x30, 0x40, 0x03, 0x02, 0x04, 0x04, 0x12,
64/*0090*/0x00, 0x06, 0x15, 0x0B, 0xE5, 0x08, 0x70, 0x04,
65 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5, 0x09,
66/*00A0*/0x70, 0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00,
67 0xEE, 0x5F, 0x60, 0x05, 0x12, 0x18, 0x71, 0xD2,
68/*00B0*/0x35, 0x53, 0xE1, 0xF7, 0xE5, 0x08, 0x45, 0x09,
69 0xFF, 0xE5, 0x0B, 0x25, 0xE0, 0x25, 0xE0, 0x24,
70/*00C0*/0x83, 0xF5, 0x82, 0xE4, 0x34, 0x07, 0xF5, 0x83,
71 0xEF, 0xF0, 0x85, 0xE2, 0x20, 0xE5, 0x52, 0xD3,
72/*00D0*/0x94, 0x01, 0x40, 0x0D, 0x12, 0x19, 0xF3, 0xE0,
73 0x54, 0xA0, 0x64, 0x40, 0x70, 0x03, 0x02, 0x03,
74/*00E0*/0xFB, 0x53, 0xF9, 0xF8, 0x90, 0x94, 0x70, 0xE4,
75 0xF0, 0xE0, 0xF5, 0x10, 0xAF, 0x09, 0x12, 0x1E,
76/*00F0*/0xB3, 0xAF, 0x08, 0xEF, 0x44, 0x08, 0xF5, 0x82,
77 0x75, 0x83, 0x80, 0xE0, 0xF5, 0x29, 0xEF, 0x44,
78/*0100*/0x07, 0x12, 0x1A, 0x3C, 0xF5, 0x22, 0x54, 0x40,
79 0xD3, 0x94, 0x00, 0x40, 0x1E, 0xE5, 0x29, 0x54,
80/*0110*/0xF0, 0x70, 0x21, 0x12, 0x19, 0xF3, 0xE0, 0x44,
81 0x80, 0xF0, 0xE5, 0x22, 0x54, 0x30, 0x65, 0x08,
82/*0120*/0x70, 0x09, 0x12, 0x19, 0xF3, 0xE0, 0x54, 0xBF,
83 0xF0, 0x80, 0x09, 0x12, 0x19, 0xF3, 0x74, 0x40,
84/*0130*/0xF0, 0x02, 0x03, 0xFB, 0x12, 0x1A, 0x12, 0x75,
85 0x83, 0xAE, 0x74, 0xFF, 0xF0, 0xAF, 0x08, 0x7E,
86/*0140*/0x00, 0xEF, 0x44, 0x07, 0xF5, 0x82, 0xE0, 0xFD,
87 0xE5, 0x0B, 0x25, 0xE0, 0x25, 0xE0, 0x24, 0x81,
88/*0150*/0xF5, 0x82, 0xE4, 0x34, 0x07, 0xF5, 0x83, 0xED,
89 0xF0, 0x90, 0x07, 0x0E, 0xE0, 0x04, 0xF0, 0xEF,
90/*0160*/0x44, 0x07, 0xF5, 0x82, 0x75, 0x83, 0x98, 0xE0,
91 0xF5, 0x28, 0x12, 0x1A, 0x23, 0x40, 0x0C, 0x12,
92/*0170*/0x19, 0xF3, 0xE0, 0x44, 0x01, 0x12, 0x1A, 0x32,
93 0x02, 0x03, 0xF6, 0xAF, 0x08, 0x7E, 0x00, 0x74,
94/*0180*/0x80, 0xCD, 0xEF, 0xCD, 0x8D, 0x82, 0xF5, 0x83,
95 0xE0, 0x30, 0xE0, 0x0A, 0x12, 0x19, 0xF3, 0xE0,
96/*0190*/0x44, 0x20, 0xF0, 0x02, 0x03, 0xFB, 0x12, 0x19,
97 0xF3, 0xE0, 0x54, 0xDF, 0xF0, 0xEE, 0x44, 0xAE,
98/*01A0*/0x12, 0x1A, 0x43, 0x30, 0xE4, 0x03, 0x02, 0x03,
99 0xFB, 0x74, 0x9E, 0x12, 0x1A, 0x05, 0x20, 0xE0,
100/*01B0*/0x03, 0x02, 0x03, 0xFB, 0x8F, 0x82, 0x8E, 0x83,
101 0xE0, 0x20, 0xE0, 0x03, 0x02, 0x03, 0xFB, 0x12,
102/*01C0*/0x19, 0xF3, 0xE0, 0x44, 0x10, 0xF0, 0xE5, 0xE3,
103 0x20, 0xE7, 0x08, 0xE5, 0x08, 0x12, 0x1A, 0x3A,
104/*01D0*/0x44, 0x04, 0xF0, 0xAF, 0x08, 0x7E, 0x00, 0xEF,
105 0x12, 0x1A, 0x3A, 0x20, 0xE2, 0x34, 0x12, 0x19,
106/*01E0*/0xF3, 0xE0, 0x44, 0x08, 0xF0, 0xE5, 0xE4, 0x30,
107 0xE6, 0x04, 0x7D, 0x01, 0x80, 0x02, 0x7D, 0x00,
108/*01F0*/0xE5, 0x7E, 0xC3, 0x94, 0x04, 0x50, 0x04, 0x7C,
109 0x01, 0x80, 0x02, 0x7C, 0x00, 0xEC, 0x4D, 0x60,
110/*0200*/0x05, 0xC2, 0x35, 0x02, 0x03, 0xFB, 0xEE, 0x44,
111 0xD2, 0x12, 0x1A, 0x43, 0x44, 0x40, 0xF0, 0x02,
112/*0210*/0x03, 0xFB, 0x12, 0x19, 0xF3, 0xE0, 0x54, 0xF7,
113 0xF0, 0x12, 0x1A, 0x12, 0x75, 0x83, 0xD2, 0xE0,
114/*0220*/0x54, 0xBF, 0xF0, 0x90, 0x07, 0x14, 0xE0, 0x04,
115 0xF0, 0xE5, 0x7E, 0x70, 0x03, 0x75, 0x7E, 0x01,
116/*0230*/0xAF, 0x08, 0x7E, 0x00, 0x12, 0x1A, 0x23, 0x40,
117 0x12, 0x12, 0x19, 0xF3, 0xE0, 0x44, 0x01, 0x12,
118/*0240*/0x19, 0xF2, 0xE0, 0x54, 0x02, 0x12, 0x1A, 0x32,
119 0x02, 0x03, 0xFB, 0x12, 0x19, 0xF3, 0xE0, 0x44,
120/*0250*/0x02, 0x12, 0x19, 0xF2, 0xE0, 0x54, 0xFE, 0xF0,
121 0xC2, 0x35, 0xEE, 0x44, 0x8A, 0x8F, 0x82, 0xF5,
122/*0260*/0x83, 0xE0, 0xF5, 0x17, 0x54, 0x8F, 0x44, 0x40,
123 0xF0, 0x74, 0x90, 0xFC, 0xE5, 0x08, 0x44, 0x07,
124/*0270*/0xFD, 0xF5, 0x82, 0x8C, 0x83, 0xE0, 0x54, 0x3F,
125 0x90, 0x07, 0x02, 0xF0, 0xE0, 0x54, 0xC0, 0x8D,
126/*0280*/0x82, 0x8C, 0x83, 0xF0, 0x74, 0x92, 0x12, 0x1A,
127 0x05, 0x90, 0x07, 0x03, 0x12, 0x1A, 0x19, 0x74,
128/*0290*/0x82, 0x12, 0x1A, 0x05, 0x90, 0x07, 0x04, 0x12,
129 0x1A, 0x19, 0x74, 0xB4, 0x12, 0x1A, 0x05, 0x90,
130/*02A0*/0x07, 0x05, 0x12, 0x1A, 0x19, 0x74, 0x94, 0xFE,
131 0xE5, 0x08, 0x44, 0x06, 0x12, 0x1A, 0x0A, 0xF5,
132/*02B0*/0x10, 0x30, 0xE0, 0x04, 0xD2, 0x37, 0x80, 0x02,
133 0xC2, 0x37, 0xE5, 0x10, 0x54, 0x7F, 0x8F, 0x82,
134/*02C0*/0x8E, 0x83, 0xF0, 0x30, 0x44, 0x30, 0x12, 0x1A,
135 0x03, 0x54, 0x80, 0xD3, 0x94, 0x00, 0x40, 0x04,
136/*02D0*/0xD2, 0x39, 0x80, 0x02, 0xC2, 0x39, 0x8F, 0x82,
137 0x8E, 0x83, 0xE0, 0x44, 0x80, 0xF0, 0x12, 0x1A,
138/*02E0*/0x03, 0x54, 0x40, 0xD3, 0x94, 0x00, 0x40, 0x04,
139 0xD2, 0x3A, 0x80, 0x02, 0xC2, 0x3A, 0x8F, 0x82,
140/*02F0*/0x8E, 0x83, 0xE0, 0x44, 0x40, 0xF0, 0x74, 0x92,
141 0xFE, 0xE5, 0x08, 0x44, 0x06, 0x12, 0x1A, 0x0A,
142/*0300*/0x30, 0xE7, 0x04, 0xD2, 0x38, 0x80, 0x02, 0xC2,
143 0x38, 0x8F, 0x82, 0x8E, 0x83, 0xE0, 0x54, 0x7F,
144/*0310*/0xF0, 0x12, 0x1E, 0x46, 0xE4, 0xF5, 0x0A, 0x20,
145 0x03, 0x02, 0x80, 0x03, 0x30, 0x43, 0x03, 0x12,
146/*0320*/0x19, 0x95, 0x20, 0x02, 0x02, 0x80, 0x03, 0x30,
147 0x42, 0x03, 0x12, 0x0C, 0x8F, 0x30, 0x30, 0x06,
148/*0330*/0x12, 0x19, 0x95, 0x12, 0x0C, 0x8F, 0x12, 0x0D,
149 0x47, 0x12, 0x19, 0xF3, 0xE0, 0x54, 0xFB, 0xF0,
150/*0340*/0xE5, 0x0A, 0xC3, 0x94, 0x01, 0x40, 0x46, 0x43,
151 0xE1, 0x08, 0x12, 0x19, 0xF3, 0xE0, 0x44, 0x04,
152/*0350*/0xF0, 0xE5, 0xE4, 0x20, 0xE7, 0x2A, 0x12, 0x1A,
153 0x12, 0x75, 0x83, 0xD2, 0xE0, 0x54, 0x08, 0xD3,
154/*0360*/0x94, 0x00, 0x40, 0x04, 0x7F, 0x01, 0x80, 0x02,
155 0x7F, 0x00, 0xE5, 0x0A, 0xC3, 0x94, 0x01, 0x40,
156/*0370*/0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEF,
157 0x5E, 0x60, 0x05, 0x12, 0x1D, 0xD7, 0x80, 0x17,
158/*0380*/0x12, 0x1A, 0x12, 0x75, 0x83, 0xD2, 0xE0, 0x44,
159 0x08, 0xF0, 0x02, 0x03, 0xFB, 0x12, 0x1A, 0x12,
160/*0390*/0x75, 0x83, 0xD2, 0xE0, 0x54, 0xF7, 0xF0, 0x12,
161 0x1E, 0x46, 0x7F, 0x08, 0x12, 0x17, 0x31, 0x74,
162/*03A0*/0x8E, 0xFE, 0x12, 0x1A, 0x12, 0x8E, 0x83, 0xE0,
163 0xF5, 0x10, 0x54, 0xFE, 0xF0, 0xE5, 0x10, 0x44,
164/*03B0*/0x01, 0xFF, 0xE5, 0x08, 0xFD, 0xED, 0x44, 0x07,
165 0xF5, 0x82, 0xEF, 0xF0, 0xE5, 0x10, 0x54, 0xFE,
166/*03C0*/0xFF, 0xED, 0x44, 0x07, 0xF5, 0x82, 0xEF, 0x12,
167 0x1A, 0x11, 0x75, 0x83, 0x86, 0xE0, 0x44, 0x10,
168/*03D0*/0x12, 0x1A, 0x11, 0xE0, 0x44, 0x10, 0xF0, 0x12,
169 0x19, 0xF3, 0xE0, 0x54, 0xFD, 0x44, 0x01, 0xFF,
170/*03E0*/0x12, 0x19, 0xF3, 0xEF, 0x12, 0x1A, 0x32, 0x30,
171 0x32, 0x0C, 0xE5, 0x08, 0x44, 0x08, 0xF5, 0x82,
172/*03F0*/0x75, 0x83, 0x82, 0x74, 0x05, 0xF0, 0xAF, 0x0B,
173 0x12, 0x18, 0xD7, 0x74, 0x10, 0x25, 0x08, 0xF5,
174/*0400*/0x08, 0x02, 0x00, 0x85, 0x05, 0x09, 0xE5, 0x09,
175 0xD3, 0x94, 0x07, 0x50, 0x03, 0x02, 0x00, 0x82,
176/*0410*/0xE5, 0x7E, 0xD3, 0x94, 0x00, 0x40, 0x04, 0x7F,
177 0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5, 0x7E, 0xC3,
178/*0420*/0x94, 0xFA, 0x50, 0x04, 0x7E, 0x01, 0x80, 0x02,
179 0x7E, 0x00, 0xEE, 0x5F, 0x60, 0x02, 0x05, 0x7E,
180/*0430*/0x30, 0x35, 0x0B, 0x43, 0xE1, 0x01, 0x7F, 0x09,
181 0x12, 0x17, 0x31, 0x02, 0x00, 0x58, 0x53, 0xE1,
182/*0440*/0xFE, 0x02, 0x00, 0x58, 0x8E, 0x6A, 0x8F, 0x6B,
183 0x8C, 0x6C, 0x8D, 0x6D, 0x75, 0x6E, 0x01, 0x75,
184/*0450*/0x6F, 0x01, 0x75, 0x70, 0x01, 0xE4, 0xF5, 0x73,
185 0xF5, 0x74, 0xF5, 0x75, 0x90, 0x07, 0x2F, 0xF0,
186/*0460*/0xF5, 0x3C, 0xF5, 0x3E, 0xF5, 0x46, 0xF5, 0x47,
187 0xF5, 0x3D, 0xF5, 0x3F, 0xF5, 0x6F, 0xE5, 0x6F,
188/*0470*/0x70, 0x0F, 0xE5, 0x6B, 0x45, 0x6A, 0x12, 0x07,
189 0x2A, 0x75, 0x83, 0x80, 0x74, 0x3A, 0xF0, 0x80,
190/*0480*/0x09, 0x12, 0x07, 0x2A, 0x75, 0x83, 0x80, 0x74,
191 0x1A, 0xF0, 0xE4, 0xF5, 0x6E, 0xC3, 0x74, 0x3F,
192/*0490*/0x95, 0x6E, 0xFF, 0x12, 0x08, 0x65, 0x75, 0x83,
193 0x82, 0xEF, 0xF0, 0x12, 0x1A, 0x4D, 0x12, 0x08,
194/*04A0*/0xC6, 0xE5, 0x33, 0xF0, 0x12, 0x08, 0xFA, 0x12,
195 0x08, 0xB1, 0x40, 0xE1, 0xE5, 0x6F, 0x70, 0x0B,
196/*04B0*/0x12, 0x07, 0x2A, 0x75, 0x83, 0x80, 0x74, 0x36,
197 0xF0, 0x80, 0x09, 0x12, 0x07, 0x2A, 0x75, 0x83,
198/*04C0*/0x80, 0x74, 0x16, 0xF0, 0x75, 0x6E, 0x01, 0x12,
199 0x07, 0x2A, 0x75, 0x83, 0xB4, 0xE5, 0x6E, 0xF0,
200/*04D0*/0x12, 0x1A, 0x4D, 0x74, 0x3F, 0x25, 0x6E, 0xF5,
201 0x82, 0xE4, 0x34, 0x00, 0xF5, 0x83, 0xE5, 0x33,
202/*04E0*/0xF0, 0x74, 0xBF, 0x25, 0x6E, 0xF5, 0x82, 0xE4,
203 0x34, 0x00, 0x12, 0x08, 0xB1, 0x40, 0xD8, 0xE4,
204/*04F0*/0xF5, 0x70, 0xF5, 0x46, 0xF5, 0x47, 0xF5, 0x6E,
205 0x12, 0x08, 0xFA, 0xF5, 0x83, 0xE0, 0xFE, 0x12,
206/*0500*/0x08, 0xC6, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF,
207 0xEC, 0x3E, 0xFE, 0xAD, 0x3B, 0xD3, 0xEF, 0x9D,
208/*0510*/0xEE, 0x9C, 0x50, 0x04, 0x7B, 0x01, 0x80, 0x02,
209 0x7B, 0x00, 0xE5, 0x70, 0x70, 0x04, 0x7A, 0x01,
210/*0520*/0x80, 0x02, 0x7A, 0x00, 0xEB, 0x5A, 0x60, 0x06,
211 0x85, 0x6E, 0x46, 0x75, 0x70, 0x01, 0xD3, 0xEF,
212/*0530*/0x9D, 0xEE, 0x9C, 0x50, 0x04, 0x7F, 0x01, 0x80,
213 0x02, 0x7F, 0x00, 0xE5, 0x70, 0xB4, 0x01, 0x04,
214/*0540*/0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEF, 0x5E,
215 0x60, 0x03, 0x85, 0x6E, 0x47, 0x05, 0x6E, 0xE5,
216/*0550*/0x6E, 0x64, 0x7F, 0x70, 0xA3, 0xE5, 0x46, 0x60,
217 0x05, 0xE5, 0x47, 0xB4, 0x7E, 0x03, 0x85, 0x46,
218/*0560*/0x47, 0xE5, 0x6F, 0x70, 0x08, 0x85, 0x46, 0x76,
219 0x85, 0x47, 0x77, 0x80, 0x0E, 0xC3, 0x74, 0x7F,
220/*0570*/0x95, 0x46, 0xF5, 0x78, 0xC3, 0x74, 0x7F, 0x95,
221 0x47, 0xF5, 0x79, 0xE5, 0x6F, 0x70, 0x37, 0xE5,
222/*0580*/0x46, 0x65, 0x47, 0x70, 0x0C, 0x75, 0x73, 0x01,
223 0x75, 0x74, 0x01, 0xF5, 0x3C, 0xF5, 0x3D, 0x80,
224/*0590*/0x35, 0xE4, 0xF5, 0x4E, 0xC3, 0xE5, 0x47, 0x95,
225 0x46, 0xF5, 0x3C, 0xC3, 0x13, 0xF5, 0x71, 0x25,
226/*05A0*/0x46, 0xF5, 0x72, 0xC3, 0x94, 0x3F, 0x40, 0x05,
227 0xE4, 0xF5, 0x3D, 0x80, 0x40, 0xC3, 0x74, 0x3F,
228/*05B0*/0x95, 0x72, 0xF5, 0x3D, 0x80, 0x37, 0xE5, 0x46,
229 0x65, 0x47, 0x70, 0x0F, 0x75, 0x73, 0x01, 0x75,
230/*05C0*/0x75, 0x01, 0xF5, 0x3E, 0xF5, 0x3F, 0x75, 0x4E,
231 0x01, 0x80, 0x22, 0xE4, 0xF5, 0x4E, 0xC3, 0xE5,
232/*05D0*/0x47, 0x95, 0x46, 0xF5, 0x3E, 0xC3, 0x13, 0xF5,
233 0x71, 0x25, 0x46, 0xF5, 0x72, 0xD3, 0x94, 0x3F,
234/*05E0*/0x50, 0x05, 0xE4, 0xF5, 0x3F, 0x80, 0x06, 0xE5,
235 0x72, 0x24, 0xC1, 0xF5, 0x3F, 0x05, 0x6F, 0xE5,
236/*05F0*/0x6F, 0xC3, 0x94, 0x02, 0x50, 0x03, 0x02, 0x04,
237 0x6E, 0xE5, 0x6D, 0x45, 0x6C, 0x70, 0x02, 0x80,
238/*0600*/0x04, 0xE5, 0x74, 0x45, 0x75, 0x90, 0x07, 0x2F,
239 0xF0, 0x7F, 0x01, 0xE5, 0x3E, 0x60, 0x04, 0xE5,
240/*0610*/0x3C, 0x70, 0x14, 0xE4, 0xF5, 0x3C, 0xF5, 0x3D,
241 0xF5, 0x3E, 0xF5, 0x3F, 0x12, 0x08, 0xD2, 0x70,
242/*0620*/0x04, 0xF0, 0x02, 0x06, 0xA4, 0x80, 0x7A, 0xE5,
243 0x3C, 0xC3, 0x95, 0x3E, 0x40, 0x07, 0xE5, 0x3C,
244/*0630*/0x95, 0x3E, 0xFF, 0x80, 0x06, 0xC3, 0xE5, 0x3E,
245 0x95, 0x3C, 0xFF, 0xE5, 0x76, 0xD3, 0x95, 0x79,
246/*0640*/0x40, 0x05, 0x85, 0x76, 0x7A, 0x80, 0x03, 0x85,
247 0x79, 0x7A, 0xE5, 0x77, 0xC3, 0x95, 0x78, 0x50,
248/*0650*/0x05, 0x85, 0x77, 0x7B, 0x80, 0x03, 0x85, 0x78,
249 0x7B, 0xE5, 0x7B, 0xD3, 0x95, 0x7A, 0x40, 0x30,
250/*0660*/0xE5, 0x7B, 0x95, 0x7A, 0xF5, 0x3C, 0xF5, 0x3E,
251 0xC3, 0xE5, 0x7B, 0x95, 0x7A, 0x90, 0x07, 0x19,
252/*0670*/0xF0, 0xE5, 0x3C, 0xC3, 0x13, 0xF5, 0x71, 0x25,
253 0x7A, 0xF5, 0x72, 0xC3, 0x94, 0x3F, 0x40, 0x05,
254/*0680*/0xE4, 0xF5, 0x3D, 0x80, 0x1F, 0xC3, 0x74, 0x3F,
255 0x95, 0x72, 0xF5, 0x3D, 0xF5, 0x3F, 0x80, 0x14,
256/*0690*/0xE4, 0xF5, 0x3C, 0xF5, 0x3E, 0x90, 0x07, 0x19,
257 0xF0, 0x12, 0x08, 0xD2, 0x70, 0x03, 0xF0, 0x80,
258/*06A0*/0x03, 0x74, 0x01, 0xF0, 0x12, 0x08, 0x65, 0x75,
259 0x83, 0xD0, 0xE0, 0x54, 0x0F, 0xFE, 0xAD, 0x3C,
260/*06B0*/0x70, 0x02, 0x7E, 0x07, 0xBE, 0x0F, 0x02, 0x7E,
261 0x80, 0xEE, 0xFB, 0xEF, 0xD3, 0x9B, 0x74, 0x80,
262/*06C0*/0xF8, 0x98, 0x40, 0x1F, 0xE4, 0xF5, 0x3C, 0xF5,
263 0x3E, 0x12, 0x08, 0xD2, 0x70, 0x03, 0xF0, 0x80,
264/*06D0*/0x12, 0x74, 0x01, 0xF0, 0xE5, 0x08, 0xFB, 0xEB,
265 0x44, 0x07, 0xF5, 0x82, 0x75, 0x83, 0xD2, 0xE0,
266/*06E0*/0x44, 0x10, 0xF0, 0xE5, 0x08, 0xFB, 0xEB, 0x44,
267 0x09, 0xF5, 0x82, 0x75, 0x83, 0x9E, 0xED, 0xF0,
268/*06F0*/0xEB, 0x44, 0x07, 0xF5, 0x82, 0x75, 0x83, 0xCA,
269 0xED, 0xF0, 0x12, 0x08, 0x65, 0x75, 0x83, 0xCC,
270/*0700*/0xEF, 0xF0, 0x22, 0xE5, 0x08, 0x44, 0x07, 0xF5,
271 0x82, 0x75, 0x83, 0xBC, 0xE0, 0x54, 0xF0, 0xF0,
272/*0710*/0xE5, 0x08, 0x44, 0x07, 0xF5, 0x82, 0x75, 0x83,
273 0xBE, 0xE0, 0x54, 0xF0, 0xF0, 0xE5, 0x08, 0x44,
274/*0720*/0x07, 0xF5, 0x82, 0x75, 0x83, 0xC0, 0xE0, 0x54,
275 0xF0, 0xF0, 0xE5, 0x08, 0x44, 0x07, 0xF5, 0x82,
276/*0730*/0x22, 0xF0, 0x90, 0x07, 0x28, 0xE0, 0xFE, 0xA3,
277 0xE0, 0xF5, 0x82, 0x8E, 0x83, 0x22, 0x85, 0x42,
278/*0740*/0x42, 0x85, 0x41, 0x41, 0x85, 0x40, 0x40, 0x74,
279 0xC0, 0x2F, 0xF5, 0x82, 0x74, 0x02, 0x3E, 0xF5,
280/*0750*/0x83, 0xE5, 0x42, 0xF0, 0x74, 0xE0, 0x2F, 0xF5,
281 0x82, 0x74, 0x02, 0x3E, 0xF5, 0x83, 0x22, 0xE5,
282/*0760*/0x42, 0x29, 0xFD, 0xE4, 0x33, 0xFC, 0xE5, 0x3C,
283 0xC3, 0x9D, 0xEC, 0x64, 0x80, 0xF8, 0x74, 0x80,
284/*0770*/0x98, 0x22, 0xF5, 0x83, 0xE0, 0x90, 0x07, 0x22,
285 0x54, 0x1F, 0xFD, 0xE0, 0xFA, 0xA3, 0xE0, 0xF5,
286/*0780*/0x82, 0x8A, 0x83, 0xED, 0xF0, 0x22, 0x90, 0x07,
287 0x22, 0xE0, 0xFC, 0xA3, 0xE0, 0xF5, 0x82, 0x8C,
288/*0790*/0x83, 0x22, 0x90, 0x07, 0x24, 0xFF, 0xED, 0x44,
289 0x07, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x85,
290/*07A0*/0x38, 0x38, 0x85, 0x39, 0x39, 0x85, 0x3A, 0x3A,
291 0x74, 0xC0, 0x2F, 0xF5, 0x82, 0x74, 0x02, 0x3E,
292/*07B0*/0xF5, 0x83, 0x22, 0x90, 0x07, 0x26, 0xFF, 0xED,
293 0x44, 0x07, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0x22,
294/*07C0*/0xF0, 0x74, 0xA0, 0x2F, 0xF5, 0x82, 0x74, 0x02,
295 0x3E, 0xF5, 0x83, 0x22, 0x74, 0xC0, 0x25, 0x11,
296/*07D0*/0xF5, 0x82, 0xE4, 0x34, 0x01, 0xF5, 0x83, 0x22,
297 0x74, 0x00, 0x25, 0x11, 0xF5, 0x82, 0xE4, 0x34,
298/*07E0*/0x02, 0xF5, 0x83, 0x22, 0x74, 0x60, 0x25, 0x11,
299 0xF5, 0x82, 0xE4, 0x34, 0x03, 0xF5, 0x83, 0x22,
300/*07F0*/0x74, 0x80, 0x25, 0x11, 0xF5, 0x82, 0xE4, 0x34,
301 0x03, 0xF5, 0x83, 0x22, 0x74, 0xE0, 0x25, 0x11,
302/*0800*/0xF5, 0x82, 0xE4, 0x34, 0x03, 0xF5, 0x83, 0x22,
303 0x74, 0x40, 0x25, 0x11, 0xF5, 0x82, 0xE4, 0x34,
304/*0810*/0x06, 0xF5, 0x83, 0x22, 0x74, 0x80, 0x2F, 0xF5,
305 0x82, 0x74, 0x02, 0x3E, 0xF5, 0x83, 0x22, 0xAF,
306/*0820*/0x08, 0x7E, 0x00, 0xEF, 0x44, 0x07, 0xF5, 0x82,
307 0x22, 0xF5, 0x83, 0xE5, 0x82, 0x44, 0x07, 0xF5,
308/*0830*/0x82, 0xE5, 0x40, 0xF0, 0x22, 0x74, 0x40, 0x25,
309 0x11, 0xF5, 0x82, 0xE4, 0x34, 0x02, 0xF5, 0x83,
310/*0840*/0x22, 0x74, 0xC0, 0x25, 0x11, 0xF5, 0x82, 0xE4,
311 0x34, 0x03, 0xF5, 0x83, 0x22, 0x74, 0x00, 0x25,
312/*0850*/0x11, 0xF5, 0x82, 0xE4, 0x34, 0x06, 0xF5, 0x83,
313 0x22, 0x74, 0x20, 0x25, 0x11, 0xF5, 0x82, 0xE4,
314/*0860*/0x34, 0x06, 0xF5, 0x83, 0x22, 0xE5, 0x08, 0xFD,
315 0xED, 0x44, 0x07, 0xF5, 0x82, 0x22, 0xE5, 0x41,
316/*0870*/0xF0, 0xE5, 0x65, 0x64, 0x01, 0x45, 0x64, 0x22,
317 0x7E, 0x00, 0xFB, 0x7A, 0x00, 0xFD, 0x7C, 0x00,
318/*0880*/0x22, 0x74, 0x20, 0x25, 0x11, 0xF5, 0x82, 0xE4,
319 0x34, 0x02, 0x22, 0x74, 0xA0, 0x25, 0x11, 0xF5,
320/*0890*/0x82, 0xE4, 0x34, 0x03, 0x22, 0x85, 0x3E, 0x42,
321 0x85, 0x3F, 0x41, 0x8F, 0x40, 0x22, 0x85, 0x3C,
322/*08A0*/0x42, 0x85, 0x3D, 0x41, 0x8F, 0x40, 0x22, 0x75,
323 0x45, 0x3F, 0x90, 0x07, 0x20, 0xE4, 0xF0, 0xA3,
324/*08B0*/0x22, 0xF5, 0x83, 0xE5, 0x32, 0xF0, 0x05, 0x6E,
325 0xE5, 0x6E, 0xC3, 0x94, 0x40, 0x22, 0xF0, 0xE5,
326/*08C0*/0x08, 0x44, 0x06, 0xF5, 0x82, 0x22, 0x74, 0x00,
327 0x25, 0x6E, 0xF5, 0x82, 0xE4, 0x34, 0x00, 0xF5,
328/*08D0*/0x83, 0x22, 0xE5, 0x6D, 0x45, 0x6C, 0x90, 0x07,
329 0x2F, 0x22, 0xE4, 0xF9, 0xE5, 0x3C, 0xD3, 0x95,
330/*08E0*/0x3E, 0x22, 0x74, 0x80, 0x2E, 0xF5, 0x82, 0xE4,
331 0x34, 0x02, 0xF5, 0x83, 0xE0, 0x22, 0x74, 0xA0,
332/*08F0*/0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x02, 0xF5, 0x83,
333 0xE0, 0x22, 0x74, 0x80, 0x25, 0x6E, 0xF5, 0x82,
334/*0900*/0xE4, 0x34, 0x00, 0x22, 0x25, 0x42, 0xFD, 0xE4,
335 0x33, 0xFC, 0x22, 0x85, 0x42, 0x42, 0x85, 0x41,
336/*0910*/0x41, 0x85, 0x40, 0x40, 0x22, 0xED, 0x4C, 0x60,
337 0x03, 0x02, 0x09, 0xE5, 0xEF, 0x4E, 0x70, 0x37,
338/*0920*/0x90, 0x07, 0x26, 0x12, 0x07, 0x89, 0xE0, 0xFD,
339 0x12, 0x07, 0xCC, 0xED, 0xF0, 0x90, 0x07, 0x28,
340/*0930*/0x12, 0x07, 0x89, 0xE0, 0xFD, 0x12, 0x07, 0xD8,
341 0xED, 0xF0, 0x12, 0x07, 0x86, 0xE0, 0x54, 0x1F,
342/*0940*/0xFD, 0x12, 0x08, 0x81, 0xF5, 0x83, 0xED, 0xF0,
343 0x90, 0x07, 0x24, 0x12, 0x07, 0x89, 0xE0, 0x54,
344/*0950*/0x1F, 0xFD, 0x12, 0x08, 0x35, 0xED, 0xF0, 0xEF,
345 0x64, 0x04, 0x4E, 0x70, 0x37, 0x90, 0x07, 0x26,
346/*0960*/0x12, 0x07, 0x89, 0xE0, 0xFD, 0x12, 0x07, 0xE4,
347 0xED, 0xF0, 0x90, 0x07, 0x28, 0x12, 0x07, 0x89,
348/*0970*/0xE0, 0xFD, 0x12, 0x07, 0xF0, 0xED, 0xF0, 0x12,
349 0x07, 0x86, 0xE0, 0x54, 0x1F, 0xFD, 0x12, 0x08,
350/*0980*/0x8B, 0xF5, 0x83, 0xED, 0xF0, 0x90, 0x07, 0x24,
351 0x12, 0x07, 0x89, 0xE0, 0x54, 0x1F, 0xFD, 0x12,
352/*0990*/0x08, 0x41, 0xED, 0xF0, 0xEF, 0x64, 0x01, 0x4E,
353 0x70, 0x04, 0x7D, 0x01, 0x80, 0x02, 0x7D, 0x00,
354/*09A0*/0xEF, 0x64, 0x02, 0x4E, 0x70, 0x04, 0x7F, 0x01,
355 0x80, 0x02, 0x7F, 0x00, 0xEF, 0x4D, 0x60, 0x78,
356/*09B0*/0x90, 0x07, 0x26, 0x12, 0x07, 0x35, 0xE0, 0xFF,
357 0x12, 0x07, 0xFC, 0xEF, 0x12, 0x07, 0x31, 0xE0,
358/*09C0*/0xFF, 0x12, 0x08, 0x08, 0xEF, 0xF0, 0x90, 0x07,
359 0x22, 0x12, 0x07, 0x35, 0xE0, 0x54, 0x1F, 0xFF,
360/*09D0*/0x12, 0x08, 0x4D, 0xEF, 0xF0, 0x90, 0x07, 0x24,
361 0x12, 0x07, 0x35, 0xE0, 0x54, 0x1F, 0xFF, 0x12,
362/*09E0*/0x08, 0x59, 0xEF, 0xF0, 0x22, 0x12, 0x07, 0xCC,
363 0xE4, 0xF0, 0x12, 0x07, 0xD8, 0xE4, 0xF0, 0x12,
364/*09F0*/0x08, 0x81, 0xF5, 0x83, 0xE4, 0xF0, 0x12, 0x08,
365 0x35, 0x74, 0x14, 0xF0, 0x12, 0x07, 0xE4, 0xE4,
366/*0A00*/0xF0, 0x12, 0x07, 0xF0, 0xE4, 0xF0, 0x12, 0x08,
367 0x8B, 0xF5, 0x83, 0xE4, 0xF0, 0x12, 0x08, 0x41,
368/*0A10*/0x74, 0x14, 0xF0, 0x12, 0x07, 0xFC, 0xE4, 0xF0,
369 0x12, 0x08, 0x08, 0xE4, 0xF0, 0x12, 0x08, 0x4D,
370/*0A20*/0xE4, 0xF0, 0x12, 0x08, 0x59, 0x74, 0x14, 0xF0,
371 0x22, 0x53, 0xF9, 0xF7, 0x75, 0xFC, 0x10, 0xE4,
372/*0A30*/0xF5, 0xFD, 0x75, 0xFE, 0x30, 0xF5, 0xFF, 0xE5,
373 0xE7, 0x20, 0xE7, 0x03, 0x43, 0xF9, 0x08, 0xE5,
374/*0A40*/0xE6, 0x20, 0xE7, 0x0B, 0x78, 0xFF, 0xE4, 0xF6,
375 0xD8, 0xFD, 0x53, 0xE6, 0xFE, 0x80, 0x09, 0x78,
376/*0A50*/0x08, 0xE4, 0xF6, 0xD8, 0xFD, 0x53, 0xE6, 0xFE,
377 0x75, 0x81, 0x80, 0xE4, 0xF5, 0xA8, 0xD2, 0xA8,
378/*0A60*/0xC2, 0xA9, 0xD2, 0xAF, 0xE5, 0xE2, 0x20, 0xE5,
379 0x05, 0x20, 0xE6, 0x02, 0x80, 0x03, 0x43, 0xE1,
380/*0A70*/0x02, 0xE5, 0xE2, 0x20, 0xE0, 0x0E, 0x90, 0x00,
381 0x00, 0x7F, 0x00, 0x7E, 0x08, 0xE4, 0xF0, 0xA3,
382/*0A80*/0xDF, 0xFC, 0xDE, 0xFA, 0x02, 0x0A, 0xDB, 0x43,
383 0xFA, 0x01, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83,
384/*0A90*/0xC0, 0x82, 0xC0, 0xD0, 0x12, 0x1C, 0xE7, 0xD0,
385 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, 0xD0,
386/*0AA0*/0xE0, 0x53, 0xFA, 0xFE, 0x32, 0x02, 0x1B, 0x55,
387 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0xF6,
388/*0AB0*/0x08, 0xDF, 0xF9, 0x80, 0x29, 0xE4, 0x93, 0xA3,
389 0xF8, 0x54, 0x07, 0x24, 0x0C, 0xC8, 0xC3, 0x33,
390/*0AC0*/0xC4, 0x54, 0x0F, 0x44, 0x20, 0xC8, 0x83, 0x40,
391 0x04, 0xF4, 0x56, 0x80, 0x01, 0x46, 0xF6, 0xDF,
392/*0AD0*/0xE4, 0x80, 0x0B, 0x01, 0x02, 0x04, 0x08, 0x10,
393 0x20, 0x40, 0x80, 0x90, 0x00, 0x3F, 0xE4, 0x7E,
394/*0AE0*/0x01, 0x93, 0x60, 0xC1, 0xA3, 0xFF, 0x54, 0x3F,
395 0x30, 0xE5, 0x09, 0x54, 0x1F, 0xFE, 0xE4, 0x93,
396/*0AF0*/0xA3, 0x60, 0x01, 0x0E, 0xCF, 0x54, 0xC0, 0x25,
397 0xE0, 0x60, 0xAD, 0x40, 0xB8, 0x80, 0xFE, 0x8C,
398/*0B00*/0x64, 0x8D, 0x65, 0x8A, 0x66, 0x8B, 0x67, 0xE4,
399 0xF5, 0x69, 0xEF, 0x4E, 0x70, 0x03, 0x02, 0x1D,
400/*0B10*/0x55, 0xE4, 0xF5, 0x68, 0xE5, 0x67, 0x45, 0x66,
401 0x70, 0x32, 0x12, 0x07, 0x2A, 0x75, 0x83, 0x90,
402/*0B20*/0xE4, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC2, 0xE4,
403 0x12, 0x07, 0x29, 0x75, 0x83, 0xC4, 0xE4, 0x12,
404/*0B30*/0x08, 0x70, 0x70, 0x29, 0x12, 0x07, 0x2A, 0x75,
405 0x83, 0x92, 0xE4, 0x12, 0x07, 0x29, 0x75, 0x83,
406/*0B40*/0xC6, 0xE4, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC8,
407 0xE4, 0xF0, 0x80, 0x11, 0x90, 0x07, 0x26, 0x12,
408/*0B50*/0x07, 0x35, 0xE4, 0x12, 0x08, 0x70, 0x70, 0x05,
409 0x12, 0x07, 0x32, 0xE4, 0xF0, 0x12, 0x1D, 0x55,
410/*0B60*/0x12, 0x1E, 0xBF, 0xE5, 0x67, 0x45, 0x66, 0x70,
411 0x33, 0x12, 0x07, 0x2A, 0x75, 0x83, 0x90, 0xE5,
412/*0B70*/0x41, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC2, 0xE5,
413 0x41, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC4, 0x12,
414/*0B80*/0x08, 0x6E, 0x70, 0x29, 0x12, 0x07, 0x2A, 0x75,
415 0x83, 0x92, 0xE5, 0x40, 0x12, 0x07, 0x29, 0x75,
416/*0B90*/0x83, 0xC6, 0xE5, 0x40, 0x12, 0x07, 0x29, 0x75,
417 0x83, 0xC8, 0x80, 0x0E, 0x90, 0x07, 0x26, 0x12,
418/*0BA0*/0x07, 0x35, 0x12, 0x08, 0x6E, 0x70, 0x06, 0x12,
419 0x07, 0x32, 0xE5, 0x40, 0xF0, 0xAF, 0x69, 0x7E,
420/*0BB0*/0x00, 0xAD, 0x67, 0xAC, 0x66, 0x12, 0x04, 0x44,
421 0x12, 0x07, 0x2A, 0x75, 0x83, 0xCA, 0xE0, 0xD3,
422/*0BC0*/0x94, 0x00, 0x50, 0x0C, 0x05, 0x68, 0xE5, 0x68,
423 0xC3, 0x94, 0x05, 0x50, 0x03, 0x02, 0x0B, 0x14,
424/*0BD0*/0x22, 0x8C, 0x60, 0x8D, 0x61, 0x12, 0x08, 0xDA,
425 0x74, 0x20, 0x40, 0x0D, 0x2F, 0xF5, 0x82, 0x74,
426/*0BE0*/0x03, 0x3E, 0xF5, 0x83, 0xE5, 0x3E, 0xF0, 0x80,
427 0x0B, 0x2F, 0xF5, 0x82, 0x74, 0x03, 0x3E, 0xF5,
428/*0BF0*/0x83, 0xE5, 0x3C, 0xF0, 0xE5, 0x3C, 0xD3, 0x95,
429 0x3E, 0x40, 0x3C, 0xE5, 0x61, 0x45, 0x60, 0x70,
430/*0C00*/0x10, 0xE9, 0x12, 0x09, 0x04, 0xE5, 0x3E, 0x12,
431 0x07, 0x68, 0x40, 0x3B, 0x12, 0x08, 0x95, 0x80,
432/*0C10*/0x18, 0xE5, 0x3E, 0xC3, 0x95, 0x38, 0x40, 0x1D,
433 0x85, 0x3E, 0x38, 0xE5, 0x3E, 0x60, 0x05, 0x85,
434/*0C20*/0x3F, 0x39, 0x80, 0x03, 0x85, 0x39, 0x39, 0x8F,
435 0x3A, 0x12, 0x08, 0x14, 0xE5, 0x3E, 0x12, 0x07,
436/*0C30*/0xC0, 0xE5, 0x3F, 0xF0, 0x22, 0x80, 0x43, 0xE5,
437 0x61, 0x45, 0x60, 0x70, 0x19, 0x12, 0x07, 0x5F,
438/*0C40*/0x40, 0x05, 0x12, 0x08, 0x9E, 0x80, 0x27, 0x12,
439 0x09, 0x0B, 0x12, 0x08, 0x14, 0xE5, 0x42, 0x12,
440/*0C50*/0x07, 0xC0, 0xE5, 0x41, 0xF0, 0x22, 0xE5, 0x3C,
441 0xC3, 0x95, 0x38, 0x40, 0x1D, 0x85, 0x3C, 0x38,
442/*0C60*/0xE5, 0x3C, 0x60, 0x05, 0x85, 0x3D, 0x39, 0x80,
443 0x03, 0x85, 0x39, 0x39, 0x8F, 0x3A, 0x12, 0x08,
444/*0C70*/0x14, 0xE5, 0x3C, 0x12, 0x07, 0xC0, 0xE5, 0x3D,
445 0xF0, 0x22, 0x85, 0x38, 0x38, 0x85, 0x39, 0x39,
446/*0C80*/0x85, 0x3A, 0x3A, 0x12, 0x08, 0x14, 0xE5, 0x38,
447 0x12, 0x07, 0xC0, 0xE5, 0x39, 0xF0, 0x22, 0x7F,
448/*0C90*/0x06, 0x12, 0x17, 0x31, 0x12, 0x1D, 0x23, 0x12,
449 0x0E, 0x04, 0x12, 0x0E, 0x33, 0xE0, 0x44, 0x0A,
450/*0CA0*/0xF0, 0x74, 0x8E, 0xFE, 0x12, 0x0E, 0x04, 0x12,
451 0x0E, 0x0B, 0xEF, 0xF0, 0xE5, 0x28, 0x30, 0xE5,
452/*0CB0*/0x03, 0xD3, 0x80, 0x01, 0xC3, 0x40, 0x05, 0x75,
453 0x14, 0x20, 0x80, 0x03, 0x75, 0x14, 0x08, 0x12,
454/*0CC0*/0x0E, 0x04, 0x75, 0x83, 0x8A, 0xE5, 0x14, 0xF0,
455 0xB4, 0xFF, 0x05, 0x75, 0x12, 0x80, 0x80, 0x06,
456/*0CD0*/0xE5, 0x14, 0xC3, 0x13, 0xF5, 0x12, 0xE4, 0xF5,
457 0x16, 0xF5, 0x7F, 0x12, 0x19, 0x36, 0x12, 0x13,
458/*0CE0*/0xA3, 0xE5, 0x0A, 0xC3, 0x94, 0x01, 0x50, 0x09,
459 0x05, 0x16, 0xE5, 0x16, 0xC3, 0x94, 0x14, 0x40,
460/*0CF0*/0xEA, 0xE5, 0xE4, 0x20, 0xE7, 0x28, 0x12, 0x0E,
461 0x04, 0x75, 0x83, 0xD2, 0xE0, 0x54, 0x08, 0xD3,
462/*0D00*/0x94, 0x00, 0x40, 0x04, 0x7F, 0x01, 0x80, 0x02,
463 0x7F, 0x00, 0xE5, 0x0A, 0xC3, 0x94, 0x01, 0x40,
464/*0D10*/0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEF,
465 0x5E, 0x60, 0x03, 0x12, 0x1D, 0xD7, 0xE5, 0x7F,
466/*0D20*/0xC3, 0x94, 0x11, 0x40, 0x14, 0x12, 0x0E, 0x04,
467 0x75, 0x83, 0xD2, 0xE0, 0x44, 0x80, 0xF0, 0xE5,
468/*0D30*/0xE4, 0x20, 0xE7, 0x0F, 0x12, 0x1D, 0xD7, 0x80,
469 0x0A, 0x12, 0x0E, 0x04, 0x75, 0x83, 0xD2, 0xE0,
470/*0D40*/0x54, 0x7F, 0xF0, 0x12, 0x1D, 0x23, 0x22, 0x74,
471 0x8A, 0x85, 0x08, 0x82, 0xF5, 0x83, 0xE5, 0x17,
472/*0D50*/0xF0, 0x12, 0x0E, 0x3A, 0xE4, 0xF0, 0x90, 0x07,
473 0x02, 0xE0, 0x12, 0x0E, 0x17, 0x75, 0x83, 0x90,
474/*0D60*/0xEF, 0xF0, 0x74, 0x92, 0xFE, 0xE5, 0x08, 0x44,
475 0x07, 0xFF, 0xF5, 0x82, 0x8E, 0x83, 0xE0, 0x54,
476/*0D70*/0xC0, 0xFD, 0x90, 0x07, 0x03, 0xE0, 0x54, 0x3F,
477 0x4D, 0x8F, 0x82, 0x8E, 0x83, 0xF0, 0x90, 0x07,
478/*0D80*/0x04, 0xE0, 0x12, 0x0E, 0x17, 0x75, 0x83, 0x82,
479 0xEF, 0xF0, 0x90, 0x07, 0x05, 0xE0, 0xFF, 0xED,
480/*0D90*/0x44, 0x07, 0xF5, 0x82, 0x75, 0x83, 0xB4, 0xEF,
481 0x12, 0x0E, 0x03, 0x75, 0x83, 0x80, 0xE0, 0x54,
482/*0DA0*/0xBF, 0xF0, 0x30, 0x37, 0x0A, 0x12, 0x0E, 0x91,
483 0x75, 0x83, 0x94, 0xE0, 0x44, 0x80, 0xF0, 0x30,
484/*0DB0*/0x38, 0x0A, 0x12, 0x0E, 0x91, 0x75, 0x83, 0x92,
485 0xE0, 0x44, 0x80, 0xF0, 0xE5, 0x28, 0x30, 0xE4,
486/*0DC0*/0x1A, 0x20, 0x39, 0x0A, 0x12, 0x0E, 0x04, 0x75,
487 0x83, 0x88, 0xE0, 0x54, 0x7F, 0xF0, 0x20, 0x3A,
488/*0DD0*/0x0A, 0x12, 0x0E, 0x04, 0x75, 0x83, 0x88, 0xE0,
489 0x54, 0xBF, 0xF0, 0x74, 0x8C, 0xFE, 0x12, 0x0E,
490/*0DE0*/0x04, 0x8E, 0x83, 0xE0, 0x54, 0x0F, 0x12, 0x0E,
491 0x03, 0x75, 0x83, 0x86, 0xE0, 0x54, 0xBF, 0xF0,
492/*0DF0*/0xE5, 0x08, 0x44, 0x06, 0x12, 0x0D, 0xFD, 0x75,
493 0x83, 0x8A, 0xE4, 0xF0, 0x22, 0xF5, 0x82, 0x75,
494/*0E00*/0x83, 0x82, 0xE4, 0xF0, 0xE5, 0x08, 0x44, 0x07,
495 0xF5, 0x82, 0x22, 0x8E, 0x83, 0xE0, 0xF5, 0x10,
496/*0E10*/0x54, 0xFE, 0xF0, 0xE5, 0x10, 0x44, 0x01, 0xFF,
497 0xE5, 0x08, 0xFD, 0xED, 0x44, 0x07, 0xF5, 0x82,
498/*0E20*/0x22, 0xE5, 0x15, 0xC4, 0x54, 0x07, 0xFF, 0xE5,
499 0x08, 0xFD, 0xED, 0x44, 0x08, 0xF5, 0x82, 0x75,
500/*0E30*/0x83, 0x82, 0x22, 0x75, 0x83, 0x80, 0xE0, 0x44,
501 0x40, 0xF0, 0xE5, 0x08, 0x44, 0x08, 0xF5, 0x82,
502/*0E40*/0x75, 0x83, 0x8A, 0x22, 0xE5, 0x16, 0x25, 0xE0,
503 0x25, 0xE0, 0x24, 0xAF, 0xF5, 0x82, 0xE4, 0x34,
504/*0E50*/0x1A, 0xF5, 0x83, 0xE4, 0x93, 0xF5, 0x0D, 0x22,
505 0x43, 0xE1, 0x10, 0x43, 0xE1, 0x80, 0x53, 0xE1,
506/*0E60*/0xFD, 0x85, 0xE1, 0x10, 0x22, 0xE5, 0x16, 0x25,
507 0xE0, 0x25, 0xE0, 0x24, 0xB2, 0xF5, 0x82, 0xE4,
508/*0E70*/0x34, 0x1A, 0xF5, 0x83, 0xE4, 0x93, 0x22, 0x85,
509 0x55, 0x82, 0x85, 0x54, 0x83, 0xE5, 0x15, 0xF0,
510/*0E80*/0x22, 0xE5, 0xE2, 0x54, 0x20, 0xD3, 0x94, 0x00,
511 0x22, 0xE5, 0xE2, 0x54, 0x40, 0xD3, 0x94, 0x00,
512/*0E90*/0x22, 0xE5, 0x08, 0x44, 0x06, 0xF5, 0x82, 0x22,
513 0xFD, 0xE5, 0x08, 0xFB, 0xEB, 0x44, 0x07, 0xF5,
514/*0EA0*/0x82, 0x22, 0x53, 0xF9, 0xF7, 0x75, 0xFE, 0x30,
515 0x22, 0xEF, 0x4E, 0x70, 0x26, 0x12, 0x07, 0xCC,
516/*0EB0*/0xE0, 0xFD, 0x90, 0x07, 0x26, 0x12, 0x07, 0x7B,
517 0x12, 0x07, 0xD8, 0xE0, 0xFD, 0x90, 0x07, 0x28,
518/*0EC0*/0x12, 0x07, 0x7B, 0x12, 0x08, 0x81, 0x12, 0x07,
519 0x72, 0x12, 0x08, 0x35, 0xE0, 0x90, 0x07, 0x24,
520/*0ED0*/0x12, 0x07, 0x78, 0xEF, 0x64, 0x04, 0x4E, 0x70,
521 0x29, 0x12, 0x07, 0xE4, 0xE0, 0xFD, 0x90, 0x07,
522/*0EE0*/0x26, 0x12, 0x07, 0x7B, 0x12, 0x07, 0xF0, 0xE0,
523 0xFD, 0x90, 0x07, 0x28, 0x12, 0x07, 0x7B, 0x12,
524/*0EF0*/0x08, 0x8B, 0x12, 0x07, 0x72, 0x12, 0x08, 0x41,
525 0xE0, 0x54, 0x1F, 0xFD, 0x90, 0x07, 0x24, 0x12,
526/*0F00*/0x07, 0x7B, 0xEF, 0x64, 0x01, 0x4E, 0x70, 0x04,
527 0x7D, 0x01, 0x80, 0x02, 0x7D, 0x00, 0xEF, 0x64,
528/*0F10*/0x02, 0x4E, 0x70, 0x04, 0x7F, 0x01, 0x80, 0x02,
529 0x7F, 0x00, 0xEF, 0x4D, 0x60, 0x35, 0x12, 0x07,
530/*0F20*/0xFC, 0xE0, 0xFF, 0x90, 0x07, 0x26, 0x12, 0x07,
531 0x89, 0xEF, 0xF0, 0x12, 0x08, 0x08, 0xE0, 0xFF,
532/*0F30*/0x90, 0x07, 0x28, 0x12, 0x07, 0x89, 0xEF, 0xF0,
533 0x12, 0x08, 0x4D, 0xE0, 0x54, 0x1F, 0xFF, 0x12,
534/*0F40*/0x07, 0x86, 0xEF, 0xF0, 0x12, 0x08, 0x59, 0xE0,
535 0x54, 0x1F, 0xFF, 0x90, 0x07, 0x24, 0x12, 0x07,
536/*0F50*/0x89, 0xEF, 0xF0, 0x22, 0xE4, 0xF5, 0x53, 0x12,
537 0x0E, 0x81, 0x40, 0x04, 0x7F, 0x01, 0x80, 0x02,
538/*0F60*/0x7F, 0x00, 0x12, 0x0E, 0x89, 0x40, 0x04, 0x7E,
539 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x4F, 0x70,
540/*0F70*/0x03, 0x02, 0x0F, 0xF6, 0x85, 0xE1, 0x10, 0x43,
541 0xE1, 0x02, 0x53, 0xE1, 0x0F, 0x85, 0xE1, 0x10,
542/*0F80*/0xE4, 0xF5, 0x51, 0xE5, 0xE3, 0x54, 0x3F, 0xF5,
543 0x52, 0x12, 0x0E, 0x89, 0x40, 0x1D, 0xAD, 0x52,
544/*0F90*/0xAF, 0x51, 0x12, 0x11, 0x18, 0xEF, 0x60, 0x08,
545 0x85, 0xE1, 0x10, 0x43, 0xE1, 0x40, 0x80, 0x0B,
546/*0FA0*/0x53, 0xE1, 0xBF, 0x12, 0x0E, 0x58, 0x12, 0x00,
547 0x06, 0x80, 0xFB, 0xE5, 0xE3, 0x54, 0x3F, 0xF5,
548/*0FB0*/0x51, 0xE5, 0xE4, 0x54, 0x3F, 0xF5, 0x52, 0x12,
549 0x0E, 0x81, 0x40, 0x1D, 0xAD, 0x52, 0xAF, 0x51,
550/*0FC0*/0x12, 0x11, 0x18, 0xEF, 0x60, 0x08, 0x85, 0xE1,
551 0x10, 0x43, 0xE1, 0x20, 0x80, 0x0B, 0x53, 0xE1,
552/*0FD0*/0xDF, 0x12, 0x0E, 0x58, 0x12, 0x00, 0x06, 0x80,
553 0xFB, 0x12, 0x0E, 0x81, 0x40, 0x04, 0x7F, 0x01,
554/*0FE0*/0x80, 0x02, 0x7F, 0x00, 0x12, 0x0E, 0x89, 0x40,
555 0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE,
556/*0FF0*/0x4F, 0x60, 0x03, 0x12, 0x0E, 0x5B, 0x22, 0x12,
557 0x0E, 0x21, 0xEF, 0xF0, 0x12, 0x10, 0x91, 0x22,
558/*1000*/0x02, 0x11, 0x00, 0x02, 0x10, 0x40, 0x02, 0x10,
559 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
560/*1010*/0x01, 0x20, 0x01, 0x20, 0xE4, 0xF5, 0x57, 0x12,
561 0x16, 0xBD, 0x12, 0x16, 0x44, 0xE4, 0x12, 0x10,
562/*1020*/0x56, 0x12, 0x14, 0xB7, 0x90, 0x07, 0x26, 0x12,
563 0x07, 0x35, 0xE4, 0x12, 0x07, 0x31, 0xE4, 0xF0,
564/*1030*/0x12, 0x10, 0x56, 0x12, 0x14, 0xB7, 0x90, 0x07,
565 0x26, 0x12, 0x07, 0x35, 0xE5, 0x41, 0x12, 0x07,
566/*1040*/0x31, 0xE5, 0x40, 0xF0, 0xAF, 0x57, 0x7E, 0x00,
567 0xAD, 0x56, 0x7C, 0x00, 0x12, 0x04, 0x44, 0xAF,
568/*1050*/0x56, 0x7E, 0x00, 0x02, 0x11, 0xEE, 0xFF, 0x90,
569 0x07, 0x20, 0xA3, 0xE0, 0xFD, 0xE4, 0xF5, 0x56,
570/*1060*/0xF5, 0x40, 0xFE, 0xFC, 0xAB, 0x56, 0xFA, 0x12,
571 0x11, 0x51, 0x7F, 0x0F, 0x7D, 0x18, 0xE4, 0xF5,
572/*1070*/0x56, 0xF5, 0x40, 0xFE, 0xFC, 0xAB, 0x56, 0xFA,
573 0x12, 0x15, 0x41, 0xAF, 0x56, 0x7E, 0x00, 0x12,
574/*1080*/0x1A, 0xFF, 0xE4, 0xFF, 0xF5, 0x56, 0x7D, 0x1F,
575 0xF5, 0x40, 0xFE, 0xFC, 0xAB, 0x56, 0xFA, 0x22,
576/*1090*/0x22, 0xE4, 0xF5, 0x55, 0xE5, 0x08, 0xFD, 0x74,
577 0xA0, 0xF5, 0x56, 0xED, 0x44, 0x07, 0xF5, 0x57,
578/*10A0*/0xE5, 0x28, 0x30, 0xE5, 0x03, 0xD3, 0x80, 0x01,
579 0xC3, 0x40, 0x05, 0x7F, 0x28, 0xEF, 0x80, 0x04,
580/*10B0*/0x7F, 0x14, 0xEF, 0xC3, 0x13, 0xF5, 0x54, 0xE4,
581 0xF9, 0x12, 0x0E, 0x18, 0x75, 0x83, 0x8E, 0xE0,
582/*10C0*/0xF5, 0x10, 0xCE, 0xEF, 0xCE, 0xEE, 0xD3, 0x94,
583 0x00, 0x40, 0x26, 0xE5, 0x10, 0x54, 0xFE, 0x12,
584/*10D0*/0x0E, 0x98, 0x75, 0x83, 0x8E, 0xED, 0xF0, 0xE5,
585 0x10, 0x44, 0x01, 0xFD, 0xEB, 0x44, 0x07, 0xF5,
586/*10E0*/0x82, 0xED, 0xF0, 0x85, 0x57, 0x82, 0x85, 0x56,
587 0x83, 0xE0, 0x30, 0xE3, 0x01, 0x09, 0x1E, 0x80,
588/*10F0*/0xD4, 0xC2, 0x34, 0xE9, 0xC3, 0x95, 0x54, 0x40,
589 0x02, 0xD2, 0x34, 0x22, 0x02, 0x00, 0x06, 0x22,
590/*1100*/0x30, 0x30, 0x11, 0x90, 0x10, 0x00, 0xE4, 0x93,
591 0xF5, 0x10, 0x90, 0x10, 0x10, 0xE4, 0x93, 0xF5,
592/*1110*/0x10, 0x12, 0x10, 0x90, 0x12, 0x11, 0x50, 0x22,
593 0xE4, 0xFC, 0xC3, 0xED, 0x9F, 0xFA, 0xEF, 0xF5,
594/*1120*/0x83, 0x75, 0x82, 0x00, 0x79, 0xFF, 0xE4, 0x93,
595 0xCC, 0x6C, 0xCC, 0xA3, 0xD9, 0xF8, 0xDA, 0xF6,
596/*1130*/0xE5, 0xE2, 0x30, 0xE4, 0x02, 0x8C, 0xE5, 0xED,
597 0x24, 0xFF, 0xFF, 0xEF, 0x75, 0x82, 0xFF, 0xF5,
598/*1140*/0x83, 0xE4, 0x93, 0x6C, 0x70, 0x03, 0x7F, 0x01,
599 0x22, 0x7F, 0x00, 0x22, 0x22, 0x11, 0x00, 0x00,
600/*1150*/0x22, 0x8E, 0x58, 0x8F, 0x59, 0x8C, 0x5A, 0x8D,
601 0x5B, 0x8A, 0x5C, 0x8B, 0x5D, 0x75, 0x5E, 0x01,
602/*1160*/0xE4, 0xF5, 0x5F, 0xF5, 0x60, 0xF5, 0x62, 0x12,
603 0x07, 0x2A, 0x75, 0x83, 0xD0, 0xE0, 0xFF, 0xC4,
604/*1170*/0x54, 0x0F, 0xF5, 0x61, 0x12, 0x1E, 0xA5, 0x85,
605 0x59, 0x5E, 0xD3, 0xE5, 0x5E, 0x95, 0x5B, 0xE5,
606/*1180*/0x5A, 0x12, 0x07, 0x6B, 0x50, 0x4B, 0x12, 0x07,
607 0x03, 0x75, 0x83, 0xBC, 0xE0, 0x45, 0x5E, 0x12,
608/*1190*/0x07, 0x29, 0x75, 0x83, 0xBE, 0xE0, 0x45, 0x5E,
609 0x12, 0x07, 0x29, 0x75, 0x83, 0xC0, 0xE0, 0x45,
610/*11A0*/0x5E, 0xF0, 0xAF, 0x5F, 0xE5, 0x60, 0x12, 0x08,
611 0x78, 0x12, 0x0A, 0xFF, 0xAF, 0x62, 0x7E, 0x00,
612/*11B0*/0xAD, 0x5D, 0xAC, 0x5C, 0x12, 0x04, 0x44, 0xE5,
613 0x61, 0xAF, 0x5E, 0x7E, 0x00, 0xB4, 0x03, 0x05,
614/*11C0*/0x12, 0x1E, 0x21, 0x80, 0x07, 0xAD, 0x5D, 0xAC,
615 0x5C, 0x12, 0x13, 0x17, 0x05, 0x5E, 0x02, 0x11,
616/*11D0*/0x7A, 0x12, 0x07, 0x03, 0x75, 0x83, 0xBC, 0xE0,
617 0x45, 0x40, 0x12, 0x07, 0x29, 0x75, 0x83, 0xBE,
618/*11E0*/0xE0, 0x45, 0x40, 0x12, 0x07, 0x29, 0x75, 0x83,
619 0xC0, 0xE0, 0x45, 0x40, 0xF0, 0x22, 0x8E, 0x58,
620/*11F0*/0x8F, 0x59, 0x75, 0x5A, 0x01, 0x79, 0x01, 0x75,
621 0x5B, 0x01, 0xE4, 0xFB, 0x12, 0x07, 0x2A, 0x75,
622/*1200*/0x83, 0xAE, 0xE0, 0x54, 0x1A, 0xFF, 0x12, 0x08,
623 0x65, 0xE0, 0xC4, 0x13, 0x54, 0x07, 0xFE, 0xEF,
624/*1210*/0x70, 0x0C, 0xEE, 0x65, 0x35, 0x70, 0x07, 0x90,
625 0x07, 0x2F, 0xE0, 0xB4, 0x01, 0x0D, 0xAF, 0x35,
626/*1220*/0x7E, 0x00, 0x12, 0x0E, 0xA9, 0xCF, 0xEB, 0xCF,
627 0x02, 0x1E, 0x60, 0xE5, 0x59, 0x64, 0x02, 0x45,
628/*1230*/0x58, 0x70, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F,
629 0x00, 0xE5, 0x59, 0x45, 0x58, 0x70, 0x04, 0x7E,
630/*1240*/0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x4F, 0x60,
631 0x23, 0x85, 0x41, 0x49, 0x85, 0x40, 0x4B, 0xE5,
632/*1250*/0x59, 0x45, 0x58, 0x70, 0x2C, 0xAF, 0x5A, 0xFE,
633 0xCD, 0xE9, 0xCD, 0xFC, 0xAB, 0x59, 0xAA, 0x58,
634/*1260*/0x12, 0x0A, 0xFF, 0xAF, 0x5B, 0x7E, 0x00, 0x12,
635 0x1E, 0x60, 0x80, 0x15, 0xAF, 0x5B, 0x7E, 0x00,
636/*1270*/0x12, 0x1E, 0x60, 0x90, 0x07, 0x26, 0x12, 0x07,
637 0x35, 0xE5, 0x49, 0x12, 0x07, 0x31, 0xE5, 0x4B,
638/*1280*/0xF0, 0xE4, 0xFD, 0xAF, 0x35, 0xFE, 0xFC, 0x12,
639 0x09, 0x15, 0x22, 0x8C, 0x64, 0x8D, 0x65, 0x12,
640/*1290*/0x08, 0xDA, 0x40, 0x3C, 0xE5, 0x65, 0x45, 0x64,
641 0x70, 0x10, 0x12, 0x09, 0x04, 0xC3, 0xE5, 0x3E,
642/*12A0*/0x12, 0x07, 0x69, 0x40, 0x3B, 0x12, 0x08, 0x95,
643 0x80, 0x18, 0xE5, 0x3E, 0xC3, 0x95, 0x38, 0x40,
644/*12B0*/0x1D, 0x85, 0x3E, 0x38, 0xE5, 0x3E, 0x60, 0x05,
645 0x85, 0x3F, 0x39, 0x80, 0x03, 0x85, 0x39, 0x39,
646/*12C0*/0x8F, 0x3A, 0x12, 0x07, 0xA8, 0xE5, 0x3E, 0x12,
647 0x07, 0x53, 0xE5, 0x3F, 0xF0, 0x22, 0x80, 0x3B,
648/*12D0*/0xE5, 0x65, 0x45, 0x64, 0x70, 0x11, 0x12, 0x07,
649 0x5F, 0x40, 0x05, 0x12, 0x08, 0x9E, 0x80, 0x1F,
650/*12E0*/0x12, 0x07, 0x3E, 0xE5, 0x41, 0xF0, 0x22, 0xE5,
651 0x3C, 0xC3, 0x95, 0x38, 0x40, 0x1D, 0x85, 0x3C,
652/*12F0*/0x38, 0xE5, 0x3C, 0x60, 0x05, 0x85, 0x3D, 0x39,
653 0x80, 0x03, 0x85, 0x39, 0x39, 0x8F, 0x3A, 0x12,
654/*1300*/0x07, 0xA8, 0xE5, 0x3C, 0x12, 0x07, 0x53, 0xE5,
655 0x3D, 0xF0, 0x22, 0x12, 0x07, 0x9F, 0xE5, 0x38,
656/*1310*/0x12, 0x07, 0x53, 0xE5, 0x39, 0xF0, 0x22, 0x8C,
657 0x63, 0x8D, 0x64, 0x12, 0x08, 0xDA, 0x40, 0x3C,
658/*1320*/0xE5, 0x64, 0x45, 0x63, 0x70, 0x10, 0x12, 0x09,
659 0x04, 0xC3, 0xE5, 0x3E, 0x12, 0x07, 0x69, 0x40,
660/*1330*/0x3B, 0x12, 0x08, 0x95, 0x80, 0x18, 0xE5, 0x3E,
661 0xC3, 0x95, 0x38, 0x40, 0x1D, 0x85, 0x3E, 0x38,
662/*1340*/0xE5, 0x3E, 0x60, 0x05, 0x85, 0x3F, 0x39, 0x80,
663 0x03, 0x85, 0x39, 0x39, 0x8F, 0x3A, 0x12, 0x07,
664/*1350*/0xA8, 0xE5, 0x3E, 0x12, 0x07, 0x53, 0xE5, 0x3F,
665 0xF0, 0x22, 0x80, 0x3B, 0xE5, 0x64, 0x45, 0x63,
666/*1360*/0x70, 0x11, 0x12, 0x07, 0x5F, 0x40, 0x05, 0x12,
667 0x08, 0x9E, 0x80, 0x1F, 0x12, 0x07, 0x3E, 0xE5,
668/*1370*/0x41, 0xF0, 0x22, 0xE5, 0x3C, 0xC3, 0x95, 0x38,
669 0x40, 0x1D, 0x85, 0x3C, 0x38, 0xE5, 0x3C, 0x60,
670/*1380*/0x05, 0x85, 0x3D, 0x39, 0x80, 0x03, 0x85, 0x39,
671 0x39, 0x8F, 0x3A, 0x12, 0x07, 0xA8, 0xE5, 0x3C,
672/*1390*/0x12, 0x07, 0x53, 0xE5, 0x3D, 0xF0, 0x22, 0x12,
673 0x07, 0x9F, 0xE5, 0x38, 0x12, 0x07, 0x53, 0xE5,
674/*13A0*/0x39, 0xF0, 0x22, 0xE5, 0x0D, 0xFE, 0xE5, 0x08,
675 0x8E, 0x54, 0x44, 0x05, 0xF5, 0x55, 0x75, 0x15,
676/*13B0*/0x0F, 0xF5, 0x82, 0x12, 0x0E, 0x7A, 0x12, 0x17,
677 0xA3, 0x20, 0x31, 0x05, 0x75, 0x15, 0x03, 0x80,
678/*13C0*/0x03, 0x75, 0x15, 0x0B, 0xE5, 0x0A, 0xC3, 0x94,
679 0x01, 0x50, 0x38, 0x12, 0x14, 0x20, 0x20, 0x31,
680/*13D0*/0x06, 0x05, 0x15, 0x05, 0x15, 0x80, 0x04, 0x15,
681 0x15, 0x15, 0x15, 0xE5, 0x0A, 0xC3, 0x94, 0x01,
682/*13E0*/0x50, 0x21, 0x12, 0x14, 0x20, 0x20, 0x31, 0x04,
683 0x05, 0x15, 0x80, 0x02, 0x15, 0x15, 0xE5, 0x0A,
684/*13F0*/0xC3, 0x94, 0x01, 0x50, 0x0E, 0x12, 0x0E, 0x77,
685 0x12, 0x17, 0xA3, 0x20, 0x31, 0x05, 0x05, 0x15,
686/*1400*/0x12, 0x0E, 0x77, 0xE5, 0x15, 0xB4, 0x08, 0x04,
687 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5, 0x15,
688/*1410*/0xB4, 0x07, 0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E,
689 0x00, 0xEE, 0x4F, 0x60, 0x02, 0x05, 0x7F, 0x22,
690/*1420*/0x85, 0x55, 0x82, 0x85, 0x54, 0x83, 0xE5, 0x15,
691 0xF0, 0x12, 0x17, 0xA3, 0x22, 0x12, 0x07, 0x2A,
692/*1430*/0x75, 0x83, 0xAE, 0x74, 0xFF, 0x12, 0x07, 0x29,
693 0xE0, 0x54, 0x1A, 0xF5, 0x34, 0xE0, 0xC4, 0x13,
694/*1440*/0x54, 0x07, 0xF5, 0x35, 0x24, 0xFE, 0x60, 0x24,
695 0x24, 0xFE, 0x60, 0x3C, 0x24, 0x04, 0x70, 0x63,
696/*1450*/0x75, 0x31, 0x2D, 0xE5, 0x08, 0xFD, 0x74, 0xB6,
697 0x12, 0x07, 0x92, 0x74, 0xBC, 0x90, 0x07, 0x22,
698/*1460*/0x12, 0x07, 0x95, 0x74, 0x90, 0x12, 0x07, 0xB3,
699 0x74, 0x92, 0x80, 0x3C, 0x75, 0x31, 0x3A, 0xE5,
700/*1470*/0x08, 0xFD, 0x74, 0xBA, 0x12, 0x07, 0x92, 0x74,
701 0xC0, 0x90, 0x07, 0x22, 0x12, 0x07, 0xB6, 0x74,
702/*1480*/0xC4, 0x12, 0x07, 0xB3, 0x74, 0xC8, 0x80, 0x20,
703 0x75, 0x31, 0x35, 0xE5, 0x08, 0xFD, 0x74, 0xB8,
704/*1490*/0x12, 0x07, 0x92, 0x74, 0xBE, 0xFF, 0xED, 0x44,
705 0x07, 0x90, 0x07, 0x22, 0xCF, 0xF0, 0xA3, 0xEF,
706/*14A0*/0xF0, 0x74, 0xC2, 0x12, 0x07, 0xB3, 0x74, 0xC6,
707 0xFF, 0xED, 0x44, 0x07, 0xA3, 0xCF, 0xF0, 0xA3,
708/*14B0*/0xEF, 0xF0, 0x22, 0x75, 0x34, 0x01, 0x22, 0x8E,
709 0x58, 0x8F, 0x59, 0x8C, 0x5A, 0x8D, 0x5B, 0x8A,
710/*14C0*/0x5C, 0x8B, 0x5D, 0x75, 0x5E, 0x01, 0xE4, 0xF5,
711 0x5F, 0x12, 0x1E, 0xA5, 0x85, 0x59, 0x5E, 0xD3,
712/*14D0*/0xE5, 0x5E, 0x95, 0x5B, 0xE5, 0x5A, 0x12, 0x07,
713 0x6B, 0x50, 0x57, 0xE5, 0x5D, 0x45, 0x5C, 0x70,
714/*14E0*/0x30, 0x12, 0x07, 0x2A, 0x75, 0x83, 0x92, 0xE5,
715 0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC6, 0xE5,
716/*14F0*/0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC8, 0xE5,
717 0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0x90, 0xE5,
718/*1500*/0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC2, 0xE5,
719 0x5E, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC4, 0x80,
720/*1510*/0x03, 0x12, 0x07, 0x32, 0xE5, 0x5E, 0xF0, 0xAF,
721 0x5F, 0x7E, 0x00, 0xAD, 0x5D, 0xAC, 0x5C, 0x12,
722/*1520*/0x04, 0x44, 0xAF, 0x5E, 0x7E, 0x00, 0xAD, 0x5D,
723 0xAC, 0x5C, 0x12, 0x0B, 0xD1, 0x05, 0x5E, 0x02,
724/*1530*/0x14, 0xCF, 0xAB, 0x5D, 0xAA, 0x5C, 0xAD, 0x5B,
725 0xAC, 0x5A, 0xAF, 0x59, 0xAE, 0x58, 0x02, 0x1B,
726/*1540*/0xFB, 0x8C, 0x5C, 0x8D, 0x5D, 0x8A, 0x5E, 0x8B,
727 0x5F, 0x75, 0x60, 0x01, 0xE4, 0xF5, 0x61, 0xF5,
728/*1550*/0x62, 0xF5, 0x63, 0x12, 0x1E, 0xA5, 0x8F, 0x60,
729 0xD3, 0xE5, 0x60, 0x95, 0x5D, 0xE5, 0x5C, 0x12,
730/*1560*/0x07, 0x6B, 0x50, 0x61, 0xE5, 0x5F, 0x45, 0x5E,
731 0x70, 0x27, 0x12, 0x07, 0x2A, 0x75, 0x83, 0xB6,
732/*1570*/0xE5, 0x60, 0x12, 0x07, 0x29, 0x75, 0x83, 0xB8,
733 0xE5, 0x60, 0x12, 0x07, 0x29, 0x75, 0x83, 0xBA,
734/*1580*/0xE5, 0x60, 0xF0, 0xAF, 0x61, 0x7E, 0x00, 0xE5,
735 0x62, 0x12, 0x08, 0x7A, 0x12, 0x0A, 0xFF, 0x80,
736/*1590*/0x19, 0x90, 0x07, 0x24, 0x12, 0x07, 0x35, 0xE5,
737 0x60, 0x12, 0x07, 0x29, 0x75, 0x83, 0x8E, 0xE4,
738/*15A0*/0x12, 0x07, 0x29, 0x74, 0x01, 0x12, 0x07, 0x29,
739 0xE4, 0xF0, 0xAF, 0x63, 0x7E, 0x00, 0xAD, 0x5F,
740/*15B0*/0xAC, 0x5E, 0x12, 0x04, 0x44, 0xAF, 0x60, 0x7E,
741 0x00, 0xAD, 0x5F, 0xAC, 0x5E, 0x12, 0x12, 0x8B,
742/*15C0*/0x05, 0x60, 0x02, 0x15, 0x58, 0x22, 0x90, 0x11,
743 0x4D, 0xE4, 0x93, 0x90, 0x07, 0x2E, 0xF0, 0x12,
744/*15D0*/0x08, 0x1F, 0x75, 0x83, 0xAE, 0xE0, 0x54, 0x1A,
745 0xF5, 0x34, 0x70, 0x67, 0xEF, 0x44, 0x07, 0xF5,
746/*15E0*/0x82, 0x75, 0x83, 0xCE, 0xE0, 0xFF, 0x13, 0x13,
747 0x13, 0x54, 0x07, 0xF5, 0x36, 0x54, 0x0F, 0xD3,
748/*15F0*/0x94, 0x00, 0x40, 0x06, 0x12, 0x14, 0x2D, 0x12,
749 0x1B, 0xA9, 0xE5, 0x36, 0x54, 0x0F, 0x24, 0xFE,
750/*1600*/0x60, 0x0C, 0x14, 0x60, 0x0C, 0x14, 0x60, 0x19,
751 0x24, 0x03, 0x70, 0x37, 0x80, 0x10, 0x02, 0x1E,
752/*1610*/0x91, 0x12, 0x1E, 0x91, 0x12, 0x07, 0x2A, 0x75,
753 0x83, 0xCE, 0xE0, 0x54, 0xEF, 0xF0, 0x02, 0x1D,
754/*1620*/0xAE, 0x12, 0x10, 0x14, 0xE4, 0xF5, 0x55, 0x12,
755 0x1D, 0x85, 0x05, 0x55, 0xE5, 0x55, 0xC3, 0x94,
756/*1630*/0x05, 0x40, 0xF4, 0x12, 0x07, 0x2A, 0x75, 0x83,
757 0xCE, 0xE0, 0x54, 0xC7, 0x12, 0x07, 0x29, 0xE0,
758/*1640*/0x44, 0x08, 0xF0, 0x22, 0xE4, 0xF5, 0x58, 0xF5,
759 0x59, 0xAF, 0x08, 0xEF, 0x44, 0x07, 0xF5, 0x82,
760/*1650*/0x75, 0x83, 0xD0, 0xE0, 0xFD, 0xC4, 0x54, 0x0F,
761 0xF5, 0x5A, 0xEF, 0x44, 0x07, 0xF5, 0x82, 0x75,
762/*1660*/0x83, 0x80, 0x74, 0x01, 0xF0, 0x12, 0x08, 0x21,
763 0x75, 0x83, 0x82, 0xE5, 0x45, 0xF0, 0xEF, 0x44,
764/*1670*/0x07, 0xF5, 0x82, 0x75, 0x83, 0x8A, 0x74, 0xFF,
765 0xF0, 0x12, 0x1A, 0x4D, 0x12, 0x07, 0x2A, 0x75,
766/*1680*/0x83, 0xBC, 0xE0, 0x54, 0xEF, 0x12, 0x07, 0x29,
767 0x75, 0x83, 0xBE, 0xE0, 0x54, 0xEF, 0x12, 0x07,
768/*1690*/0x29, 0x75, 0x83, 0xC0, 0xE0, 0x54, 0xEF, 0x12,
769 0x07, 0x29, 0x75, 0x83, 0xBC, 0xE0, 0x44, 0x10,
770/*16A0*/0x12, 0x07, 0x29, 0x75, 0x83, 0xBE, 0xE0, 0x44,
771 0x10, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC0, 0xE0,
772/*16B0*/0x44, 0x10, 0xF0, 0xAF, 0x58, 0xE5, 0x59, 0x12,
773 0x08, 0x78, 0x02, 0x0A, 0xFF, 0xE4, 0xF5, 0x58,
774/*16C0*/0x7D, 0x01, 0xF5, 0x59, 0xAF, 0x35, 0xFE, 0xFC,
775 0x12, 0x09, 0x15, 0x12, 0x07, 0x2A, 0x75, 0x83,
776/*16D0*/0xB6, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83,
777 0xB8, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83,
778/*16E0*/0xBA, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83,
779 0xBC, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83,
780/*16F0*/0xBE, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83,
781 0xC0, 0x74, 0x10, 0x12, 0x07, 0x29, 0x75, 0x83,
782/*1700*/0x90, 0xE4, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC2,
783 0xE4, 0x12, 0x07, 0x29, 0x75, 0x83, 0xC4, 0xE4,
784/*1710*/0x12, 0x07, 0x29, 0x75, 0x83, 0x92, 0xE4, 0x12,
785 0x07, 0x29, 0x75, 0x83, 0xC6, 0xE4, 0x12, 0x07,
786/*1720*/0x29, 0x75, 0x83, 0xC8, 0xE4, 0xF0, 0xAF, 0x58,
787 0xFE, 0xE5, 0x59, 0x12, 0x08, 0x7A, 0x02, 0x0A,
788/*1730*/0xFF, 0xE5, 0xE2, 0x30, 0xE4, 0x6C, 0xE5, 0xE7,
789 0x54, 0xC0, 0x64, 0x40, 0x70, 0x64, 0xE5, 0x09,
790/*1740*/0xC4, 0x54, 0x30, 0xFE, 0xE5, 0x08, 0x25, 0xE0,
791 0x25, 0xE0, 0x54, 0xC0, 0x4E, 0xFE, 0xEF, 0x54,
792/*1750*/0x3F, 0x4E, 0xFD, 0xE5, 0x2B, 0xAE, 0x2A, 0x78,
793 0x02, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9,
794/*1760*/0xF5, 0x82, 0x8E, 0x83, 0xED, 0xF0, 0xE5, 0x2B,
795 0xAE, 0x2A, 0x78, 0x02, 0xC3, 0x33, 0xCE, 0x33,
796/*1770*/0xCE, 0xD8, 0xF9, 0xFF, 0xF5, 0x82, 0x8E, 0x83,
797 0xA3, 0xE5, 0xFE, 0xF0, 0x8F, 0x82, 0x8E, 0x83,
798/*1780*/0xA3, 0xA3, 0xE5, 0xFD, 0xF0, 0x8F, 0x82, 0x8E,
799 0x83, 0xA3, 0xA3, 0xA3, 0xE5, 0xFC, 0xF0, 0xC3,
800/*1790*/0xE5, 0x2B, 0x94, 0xFA, 0xE5, 0x2A, 0x94, 0x00,
801 0x50, 0x08, 0x05, 0x2B, 0xE5, 0x2B, 0x70, 0x02,
802/*17A0*/0x05, 0x2A, 0x22, 0xE4, 0xFF, 0xE4, 0xF5, 0x58,
803 0xF5, 0x56, 0xF5, 0x57, 0x74, 0x82, 0xFC, 0x12,
804/*17B0*/0x0E, 0x04, 0x8C, 0x83, 0xE0, 0xF5, 0x10, 0x54,
805 0x7F, 0xF0, 0xE5, 0x10, 0x44, 0x80, 0x12, 0x0E,
806/*17C0*/0x98, 0xED, 0xF0, 0x7E, 0x0A, 0x12, 0x0E, 0x04,
807 0x75, 0x83, 0xA0, 0xE0, 0x20, 0xE0, 0x26, 0xDE,
808/*17D0*/0xF4, 0x05, 0x57, 0xE5, 0x57, 0x70, 0x02, 0x05,
809 0x56, 0xE5, 0x14, 0x24, 0x01, 0xFD, 0xE4, 0x33,
810/*17E0*/0xFC, 0xD3, 0xE5, 0x57, 0x9D, 0xE5, 0x56, 0x9C,
811 0x40, 0xD9, 0xE5, 0x0A, 0x94, 0x20, 0x50, 0x02,
812/*17F0*/0x05, 0x0A, 0x43, 0xE1, 0x08, 0xC2, 0x31, 0x12,
813 0x0E, 0x04, 0x75, 0x83, 0xA6, 0xE0, 0x55, 0x12,
814/*1800*/0x65, 0x12, 0x70, 0x03, 0xD2, 0x31, 0x22, 0xC2,
815 0x31, 0x22, 0x90, 0x07, 0x26, 0xE0, 0xFA, 0xA3,
816/*1810*/0xE0, 0xF5, 0x82, 0x8A, 0x83, 0xE0, 0xF5, 0x41,
817 0xE5, 0x39, 0xC3, 0x95, 0x41, 0x40, 0x26, 0xE5,
818/*1820*/0x39, 0x95, 0x41, 0xC3, 0x9F, 0xEE, 0x12, 0x07,
819 0x6B, 0x40, 0x04, 0x7C, 0x01, 0x80, 0x02, 0x7C,
820/*1830*/0x00, 0xE5, 0x41, 0x64, 0x3F, 0x60, 0x04, 0x7B,
821 0x01, 0x80, 0x02, 0x7B, 0x00, 0xEC, 0x5B, 0x60,
822/*1840*/0x29, 0x05, 0x41, 0x80, 0x28, 0xC3, 0xE5, 0x41,
823 0x95, 0x39, 0xC3, 0x9F, 0xEE, 0x12, 0x07, 0x6B,
824/*1850*/0x40, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00,
825 0xE5, 0x41, 0x60, 0x04, 0x7E, 0x01, 0x80, 0x02,
826/*1860*/0x7E, 0x00, 0xEF, 0x5E, 0x60, 0x04, 0x15, 0x41,
827 0x80, 0x03, 0x85, 0x39, 0x41, 0x85, 0x3A, 0x40,
828/*1870*/0x22, 0xE5, 0xE2, 0x30, 0xE4, 0x60, 0xE5, 0xE1,
829 0x30, 0xE2, 0x5B, 0xE5, 0x09, 0x70, 0x04, 0x7F,
830/*1880*/0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5, 0x08, 0x70,
831 0x04, 0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE,
832/*1890*/0x5F, 0x60, 0x43, 0x53, 0xF9, 0xF8, 0xE5, 0xE2,
833 0x30, 0xE4, 0x3B, 0xE5, 0xE1, 0x30, 0xE2, 0x2E,
834/*18A0*/0x43, 0xFA, 0x02, 0x53, 0xFA, 0xFB, 0xE4, 0xF5,
835 0x10, 0x90, 0x94, 0x70, 0xE5, 0x10, 0xF0, 0xE5,
836/*18B0*/0xE1, 0x30, 0xE2, 0xE7, 0x90, 0x94, 0x70, 0xE0,
837 0x65, 0x10, 0x60, 0x03, 0x43, 0xFA, 0x04, 0x05,
838/*18C0*/0x10, 0x90, 0x94, 0x70, 0xE5, 0x10, 0xF0, 0x70,
839 0xE6, 0x12, 0x00, 0x06, 0x80, 0xE1, 0x53, 0xFA,
840/*18D0*/0xFD, 0x53, 0xFA, 0xFB, 0x80, 0xC0, 0x22, 0x8F,
841 0x54, 0x12, 0x00, 0x06, 0xE5, 0xE1, 0x30, 0xE0,
842/*18E0*/0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, 0xE5,
843 0x7E, 0xD3, 0x94, 0x05, 0x40, 0x04, 0x7E, 0x01,
844/*18F0*/0x80, 0x02, 0x7E, 0x00, 0xEE, 0x4F, 0x60, 0x3D,
845 0x85, 0x54, 0x11, 0xE5, 0xE2, 0x20, 0xE1, 0x32,
846/*1900*/0x74, 0xCE, 0x12, 0x1A, 0x05, 0x30, 0xE7, 0x04,
847 0x7D, 0x01, 0x80, 0x02, 0x7D, 0x00, 0x8F, 0x82,
848/*1910*/0x8E, 0x83, 0xE0, 0x30, 0xE6, 0x04, 0x7F, 0x01,
849 0x80, 0x02, 0x7F, 0x00, 0xEF, 0x5D, 0x70, 0x15,
850/*1920*/0x12, 0x15, 0xC6, 0x74, 0xCE, 0x12, 0x1A, 0x05,
851 0x30, 0xE6, 0x07, 0xE0, 0x44, 0x80, 0xF0, 0x43,
852/*1930*/0xF9, 0x80, 0x12, 0x18, 0x71, 0x22, 0x12, 0x0E,
853 0x44, 0xE5, 0x16, 0x25, 0xE0, 0x25, 0xE0, 0x24,
854/*1940*/0xB0, 0xF5, 0x82, 0xE4, 0x34, 0x1A, 0xF5, 0x83,
855 0xE4, 0x93, 0xF5, 0x0F, 0xE5, 0x16, 0x25, 0xE0,
856/*1950*/0x25, 0xE0, 0x24, 0xB1, 0xF5, 0x82, 0xE4, 0x34,
857 0x1A, 0xF5, 0x83, 0xE4, 0x93, 0xF5, 0x0E, 0x12,
858/*1960*/0x0E, 0x65, 0xF5, 0x10, 0xE5, 0x0F, 0x54, 0xF0,
859 0x12, 0x0E, 0x17, 0x75, 0x83, 0x8C, 0xEF, 0xF0,
860/*1970*/0xE5, 0x0F, 0x30, 0xE0, 0x0C, 0x12, 0x0E, 0x04,
861 0x75, 0x83, 0x86, 0xE0, 0x44, 0x40, 0xF0, 0x80,
862/*1980*/0x0A, 0x12, 0x0E, 0x04, 0x75, 0x83, 0x86, 0xE0,
863 0x54, 0xBF, 0xF0, 0x12, 0x0E, 0x91, 0x75, 0x83,
864/*1990*/0x82, 0xE5, 0x0E, 0xF0, 0x22, 0x7F, 0x05, 0x12,
865 0x17, 0x31, 0x12, 0x0E, 0x04, 0x12, 0x0E, 0x33,
866/*19A0*/0x74, 0x02, 0xF0, 0x74, 0x8E, 0xFE, 0x12, 0x0E,
867 0x04, 0x12, 0x0E, 0x0B, 0xEF, 0xF0, 0x75, 0x15,
868/*19B0*/0x70, 0x12, 0x0F, 0xF7, 0x20, 0x34, 0x05, 0x75,
869 0x15, 0x10, 0x80, 0x03, 0x75, 0x15, 0x50, 0x12,
870/*19C0*/0x0F, 0xF7, 0x20, 0x34, 0x04, 0x74, 0x10, 0x80,
871 0x02, 0x74, 0xF0, 0x25, 0x15, 0xF5, 0x15, 0x12,
872/*19D0*/0x0E, 0x21, 0xEF, 0xF0, 0x12, 0x10, 0x91, 0x20,
873 0x34, 0x17, 0xE5, 0x15, 0x64, 0x30, 0x60, 0x0C,
874/*19E0*/0x74, 0x10, 0x25, 0x15, 0xF5, 0x15, 0xB4, 0x80,
875 0x03, 0xE4, 0xF5, 0x15, 0x12, 0x0E, 0x21, 0xEF,
876/*19F0*/0xF0, 0x22, 0xF0, 0xE5, 0x0B, 0x25, 0xE0, 0x25,
877 0xE0, 0x24, 0x82, 0xF5, 0x82, 0xE4, 0x34, 0x07,
878/*1A00*/0xF5, 0x83, 0x22, 0x74, 0x88, 0xFE, 0xE5, 0x08,
879 0x44, 0x07, 0xFF, 0xF5, 0x82, 0x8E, 0x83, 0xE0,
880/*1A10*/0x22, 0xF0, 0xE5, 0x08, 0x44, 0x07, 0xF5, 0x82,
881 0x22, 0xF0, 0xE0, 0x54, 0xC0, 0x8F, 0x82, 0x8E,
882/*1A20*/0x83, 0xF0, 0x22, 0xEF, 0x44, 0x07, 0xF5, 0x82,
883 0x75, 0x83, 0x86, 0xE0, 0x54, 0x10, 0xD3, 0x94,
884/*1A30*/0x00, 0x22, 0xF0, 0x90, 0x07, 0x15, 0xE0, 0x04,
885 0xF0, 0x22, 0x44, 0x06, 0xF5, 0x82, 0x75, 0x83,
886/*1A40*/0x9E, 0xE0, 0x22, 0xFE, 0xEF, 0x44, 0x07, 0xF5,
887 0x82, 0x8E, 0x83, 0xE0, 0x22, 0xE4, 0x90, 0x07,
888/*1A50*/0x2A, 0xF0, 0xA3, 0xF0, 0x12, 0x07, 0x2A, 0x75,
889 0x83, 0x82, 0xE0, 0x54, 0x7F, 0x12, 0x07, 0x29,
890/*1A60*/0xE0, 0x44, 0x80, 0xF0, 0x12, 0x10, 0xFC, 0x12,
891 0x08, 0x1F, 0x75, 0x83, 0xA0, 0xE0, 0x20, 0xE0,
892/*1A70*/0x1A, 0x90, 0x07, 0x2B, 0xE0, 0x04, 0xF0, 0x70,
893 0x06, 0x90, 0x07, 0x2A, 0xE0, 0x04, 0xF0, 0x90,
894/*1A80*/0x07, 0x2A, 0xE0, 0xB4, 0x10, 0xE1, 0xA3, 0xE0,
895 0xB4, 0x00, 0xDC, 0xEE, 0x44, 0xA6, 0xFC, 0xEF,
896/*1A90*/0x44, 0x07, 0xF5, 0x82, 0x8C, 0x83, 0xE0, 0xF5,
897 0x32, 0xEE, 0x44, 0xA8, 0xFE, 0xEF, 0x44, 0x07,
898/*1AA0*/0xF5, 0x82, 0x8E, 0x83, 0xE0, 0xF5, 0x33, 0x22,
899 0x01, 0x20, 0x11, 0x00, 0x04, 0x20, 0x00, 0x90,
900/*1AB0*/0x00, 0x20, 0x0F, 0x92, 0x00, 0x21, 0x0F, 0x94,
901 0x00, 0x22, 0x0F, 0x96, 0x00, 0x23, 0x0F, 0x98,
902/*1AC0*/0x00, 0x24, 0x0F, 0x9A, 0x00, 0x25, 0x0F, 0x9C,
903 0x00, 0x26, 0x0F, 0x9E, 0x00, 0x27, 0x0F, 0xA0,
904/*1AD0*/0x01, 0x20, 0x01, 0xA2, 0x01, 0x21, 0x01, 0xA4,
905 0x01, 0x22, 0x01, 0xA6, 0x01, 0x23, 0x01, 0xA8,
906/*1AE0*/0x01, 0x24, 0x01, 0xAA, 0x01, 0x25, 0x01, 0xAC,
907 0x01, 0x26, 0x01, 0xAE, 0x01, 0x27, 0x01, 0xB0,
908/*1AF0*/0x01, 0x28, 0x01, 0xB4, 0x00, 0x28, 0x0F, 0xB6,
909 0x40, 0x28, 0x0F, 0xB8, 0x61, 0x28, 0x01, 0xCB,
910/*1B00*/0xEF, 0xCB, 0xCA, 0xEE, 0xCA, 0x7F, 0x01, 0xE4,
911 0xFD, 0xEB, 0x4A, 0x70, 0x24, 0xE5, 0x08, 0xF5,
912/*1B10*/0x82, 0x74, 0xB6, 0x12, 0x08, 0x29, 0xE5, 0x08,
913 0xF5, 0x82, 0x74, 0xB8, 0x12, 0x08, 0x29, 0xE5,
914/*1B20*/0x08, 0xF5, 0x82, 0x74, 0xBA, 0x12, 0x08, 0x29,
915 0x7E, 0x00, 0x7C, 0x00, 0x12, 0x0A, 0xFF, 0x80,
916/*1B30*/0x12, 0x90, 0x07, 0x26, 0x12, 0x07, 0x35, 0xE5,
917 0x41, 0xF0, 0x90, 0x07, 0x24, 0x12, 0x07, 0x35,
918/*1B40*/0xE5, 0x40, 0xF0, 0x12, 0x07, 0x2A, 0x75, 0x83,
919 0x8E, 0xE4, 0x12, 0x07, 0x29, 0x74, 0x01, 0x12,
920/*1B50*/0x07, 0x29, 0xE4, 0xF0, 0x22, 0xE4, 0xF5, 0x26,
921 0xF5, 0x27, 0x53, 0xE1, 0xFE, 0xF5, 0x2A, 0x75,
922/*1B60*/0x2B, 0x01, 0xF5, 0x08, 0x7F, 0x01, 0x12, 0x17,
923 0x31, 0x30, 0x30, 0x1C, 0x90, 0x1A, 0xA9, 0xE4,
924/*1B70*/0x93, 0xF5, 0x10, 0x90, 0x1F, 0xF9, 0xE4, 0x93,
925 0xF5, 0x10, 0x90, 0x00, 0x41, 0xE4, 0x93, 0xF5,
926/*1B80*/0x10, 0x90, 0x1E, 0xCA, 0xE4, 0x93, 0xF5, 0x10,
927 0x7F, 0x02, 0x12, 0x17, 0x31, 0x12, 0x0F, 0x54,
928/*1B90*/0x7F, 0x03, 0x12, 0x17, 0x31, 0x12, 0x00, 0x06,
929 0xE5, 0xE2, 0x30, 0xE7, 0x09, 0x12, 0x10, 0x00,
930/*1BA0*/0x30, 0x30, 0x03, 0x12, 0x11, 0x00, 0x02, 0x00,
931 0x47, 0x12, 0x08, 0x1F, 0x75, 0x83, 0xD0, 0xE0,
932/*1BB0*/0xC4, 0x54, 0x0F, 0xFD, 0x75, 0x43, 0x01, 0x75,
933 0x44, 0xFF, 0x12, 0x08, 0xAA, 0x74, 0x04, 0xF0,
934/*1BC0*/0x75, 0x3B, 0x01, 0xED, 0x14, 0x60, 0x0C, 0x14,
935 0x60, 0x0B, 0x14, 0x60, 0x0F, 0x24, 0x03, 0x70,
936/*1BD0*/0x0B, 0x80, 0x09, 0x80, 0x00, 0x12, 0x08, 0xA7,
937 0x04, 0xF0, 0x80, 0x06, 0x12, 0x08, 0xA7, 0x74,
938/*1BE0*/0x04, 0xF0, 0xEE, 0x44, 0x82, 0xFE, 0xEF, 0x44,
939 0x07, 0xF5, 0x82, 0x8E, 0x83, 0xE5, 0x45, 0x12,
940/*1BF0*/0x08, 0xBE, 0x75, 0x83, 0x82, 0xE5, 0x31, 0xF0,
941 0x02, 0x11, 0x4C, 0x8E, 0x60, 0x8F, 0x61, 0x12,
942/*1C00*/0x1E, 0xA5, 0xE4, 0xFF, 0xCE, 0xED, 0xCE, 0xEE,
943 0xD3, 0x95, 0x61, 0xE5, 0x60, 0x12, 0x07, 0x6B,
944/*1C10*/0x40, 0x39, 0x74, 0x20, 0x2E, 0xF5, 0x82, 0xE4,
945 0x34, 0x03, 0xF5, 0x83, 0xE0, 0x70, 0x03, 0xFF,
946/*1C20*/0x80, 0x26, 0x12, 0x08, 0xE2, 0xFD, 0xC3, 0x9F,
947 0x40, 0x1E, 0xCF, 0xED, 0xCF, 0xEB, 0x4A, 0x70,
948/*1C30*/0x0B, 0x8D, 0x42, 0x12, 0x08, 0xEE, 0xF5, 0x41,
949 0x8E, 0x40, 0x80, 0x0C, 0x12, 0x08, 0xE2, 0xF5,
950/*1C40*/0x38, 0x12, 0x08, 0xEE, 0xF5, 0x39, 0x8E, 0x3A,
951 0x1E, 0x80, 0xBC, 0x22, 0x75, 0x58, 0x01, 0xE5,
952/*1C50*/0x35, 0x70, 0x0C, 0x12, 0x07, 0xCC, 0xE0, 0xF5,
953 0x4A, 0x12, 0x07, 0xD8, 0xE0, 0xF5, 0x4C, 0xE5,
954/*1C60*/0x35, 0xB4, 0x04, 0x0C, 0x12, 0x07, 0xE4, 0xE0,
955 0xF5, 0x4A, 0x12, 0x07, 0xF0, 0xE0, 0xF5, 0x4C,
956/*1C70*/0xE5, 0x35, 0xB4, 0x01, 0x04, 0x7F, 0x01, 0x80,
957 0x02, 0x7F, 0x00, 0xE5, 0x35, 0xB4, 0x02, 0x04,
958/*1C80*/0x7E, 0x01, 0x80, 0x02, 0x7E, 0x00, 0xEE, 0x4F,
959 0x60, 0x0C, 0x12, 0x07, 0xFC, 0xE0, 0xF5, 0x4A,
960/*1C90*/0x12, 0x08, 0x08, 0xE0, 0xF5, 0x4C, 0x85, 0x41,
961 0x49, 0x85, 0x40, 0x4B, 0x22, 0x75, 0x5B, 0x01,
962/*1CA0*/0x90, 0x07, 0x24, 0x12, 0x07, 0x35, 0xE0, 0x54,
963 0x1F, 0xFF, 0xD3, 0x94, 0x02, 0x50, 0x04, 0x8F,
964/*1CB0*/0x58, 0x80, 0x05, 0xEF, 0x24, 0xFE, 0xF5, 0x58,
965 0xEF, 0xC3, 0x94, 0x18, 0x40, 0x05, 0x75, 0x59,
966/*1CC0*/0x18, 0x80, 0x04, 0xEF, 0x04, 0xF5, 0x59, 0x85,
967 0x43, 0x5A, 0xAF, 0x58, 0x7E, 0x00, 0xAD, 0x59,
968/*1CD0*/0x7C, 0x00, 0xAB, 0x5B, 0x7A, 0x00, 0x12, 0x15,
969 0x41, 0xAF, 0x5A, 0x7E, 0x00, 0x12, 0x18, 0x0A,
970/*1CE0*/0xAF, 0x5B, 0x7E, 0x00, 0x02, 0x1A, 0xFF, 0xE5,
971 0xE2, 0x30, 0xE7, 0x0E, 0x12, 0x10, 0x03, 0xC2,
972/*1CF0*/0x30, 0x30, 0x30, 0x03, 0x12, 0x10, 0xFF, 0x20,
973 0x33, 0x28, 0xE5, 0xE7, 0x30, 0xE7, 0x05, 0x12,
974/*1D00*/0x0E, 0xA2, 0x80, 0x0D, 0xE5, 0xFE, 0xC3, 0x94,
975 0x20, 0x50, 0x06, 0x12, 0x0E, 0xA2, 0x43, 0xF9,
976/*1D10*/0x08, 0xE5, 0xF2, 0x30, 0xE7, 0x03, 0x53, 0xF9,
977 0x7F, 0xE5, 0xF1, 0x54, 0x70, 0xD3, 0x94, 0x00,
978/*1D20*/0x50, 0xD8, 0x22, 0x12, 0x0E, 0x04, 0x75, 0x83,
979 0x80, 0xE4, 0xF0, 0xE5, 0x08, 0x44, 0x07, 0x12,
980/*1D30*/0x0D, 0xFD, 0x75, 0x83, 0x84, 0x12, 0x0E, 0x02,
981 0x75, 0x83, 0x86, 0x12, 0x0E, 0x02, 0x75, 0x83,
982/*1D40*/0x8C, 0xE0, 0x54, 0xF3, 0x12, 0x0E, 0x03, 0x75,
983 0x83, 0x8E, 0x12, 0x0E, 0x02, 0x75, 0x83, 0x94,
984/*1D50*/0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x12, 0x07, 0x2A,
985 0x75, 0x83, 0x8E, 0xE4, 0x12, 0x07, 0x29, 0x74,
986/*1D60*/0x01, 0x12, 0x07, 0x29, 0xE4, 0x12, 0x08, 0xBE,
987 0x75, 0x83, 0x8C, 0xE0, 0x44, 0x20, 0x12, 0x08,
988/*1D70*/0xBE, 0xE0, 0x54, 0xDF, 0xF0, 0x74, 0x84, 0x85,
989 0x08, 0x82, 0xF5, 0x83, 0xE0, 0x54, 0x7F, 0xF0,
990/*1D80*/0xE0, 0x44, 0x80, 0xF0, 0x22, 0x75, 0x56, 0x01,
991 0xE4, 0xFD, 0xF5, 0x57, 0xAF, 0x35, 0xFE, 0xFC,
992/*1D90*/0x12, 0x09, 0x15, 0x12, 0x1C, 0x9D, 0x12, 0x1E,
993 0x7A, 0x12, 0x1C, 0x4C, 0xAF, 0x57, 0x7E, 0x00,
994/*1DA0*/0xAD, 0x56, 0x7C, 0x00, 0x12, 0x04, 0x44, 0xAF,
995 0x56, 0x7E, 0x00, 0x02, 0x11, 0xEE, 0x75, 0x56,
996/*1DB0*/0x01, 0xE4, 0xFD, 0xF5, 0x57, 0xAF, 0x35, 0xFE,
997 0xFC, 0x12, 0x09, 0x15, 0x12, 0x1C, 0x9D, 0x12,
998/*1DC0*/0x1E, 0x7A, 0x12, 0x1C, 0x4C, 0xAF, 0x57, 0x7E,
999 0x00, 0xAD, 0x56, 0x7C, 0x00, 0x12, 0x04, 0x44,
1000/*1DD0*/0xAF, 0x56, 0x7E, 0x00, 0x02, 0x11, 0xEE, 0xE4,
1001 0xF5, 0x16, 0x12, 0x0E, 0x44, 0xFE, 0xE5, 0x08,
1002/*1DE0*/0x44, 0x05, 0xFF, 0x12, 0x0E, 0x65, 0x8F, 0x82,
1003 0x8E, 0x83, 0xF0, 0x05, 0x16, 0xE5, 0x16, 0xC3,
1004/*1DF0*/0x94, 0x14, 0x40, 0xE6, 0xE5, 0x08, 0x12, 0x0E,
1005 0x2B, 0xE4, 0xF0, 0x22, 0xE4, 0xF5, 0x58, 0xF5,
1006/*1E00*/0x59, 0xF5, 0x5A, 0xFF, 0xFE, 0xAD, 0x58, 0xFC,
1007 0x12, 0x09, 0x15, 0x7F, 0x04, 0x7E, 0x00, 0xAD,
1008/*1E10*/0x58, 0x7C, 0x00, 0x12, 0x09, 0x15, 0x7F, 0x02,
1009 0x7E, 0x00, 0xAD, 0x58, 0x7C, 0x00, 0x02, 0x09,
1010/*1E20*/0x15, 0xE5, 0x3C, 0x25, 0x3E, 0xFC, 0xE5, 0x42,
1011 0x24, 0x00, 0xFB, 0xE4, 0x33, 0xFA, 0xEC, 0xC3,
1012/*1E30*/0x9B, 0xEA, 0x12, 0x07, 0x6B, 0x40, 0x0B, 0x8C,
1013 0x42, 0xE5, 0x3D, 0x25, 0x3F, 0xF5, 0x41, 0x8F,
1014/*1E40*/0x40, 0x22, 0x12, 0x09, 0x0B, 0x22, 0x74, 0x84,
1015 0xF5, 0x18, 0x85, 0x08, 0x19, 0x85, 0x19, 0x82,
1016/*1E50*/0x85, 0x18, 0x83, 0xE0, 0x54, 0x7F, 0xF0, 0xE0,
1017 0x44, 0x80, 0xF0, 0xE0, 0x44, 0x80, 0xF0, 0x22,
1018/*1E60*/0xEF, 0x4E, 0x70, 0x0B, 0x12, 0x07, 0x2A, 0x75,
1019 0x83, 0xD2, 0xE0, 0x54, 0xDF, 0xF0, 0x22, 0x12,
1020/*1E70*/0x07, 0x2A, 0x75, 0x83, 0xD2, 0xE0, 0x44, 0x20,
1021 0xF0, 0x22, 0x75, 0x58, 0x01, 0x90, 0x07, 0x26,
1022/*1E80*/0x12, 0x07, 0x35, 0xE0, 0x54, 0x3F, 0xF5, 0x41,
1023 0x12, 0x07, 0x32, 0xE0, 0x54, 0x3F, 0xF5, 0x40,
1024/*1E90*/0x22, 0x75, 0x56, 0x02, 0xE4, 0xF5, 0x57, 0x12,
1025 0x1D, 0xFC, 0xAF, 0x57, 0x7E, 0x00, 0xAD, 0x56,
1026/*1EA0*/0x7C, 0x00, 0x02, 0x04, 0x44, 0xE4, 0xF5, 0x42,
1027 0xF5, 0x41, 0xF5, 0x40, 0xF5, 0x38, 0xF5, 0x39,
1028/*1EB0*/0xF5, 0x3A, 0x22, 0xEF, 0x54, 0x07, 0xFF, 0xE5,
1029 0xF9, 0x54, 0xF8, 0x4F, 0xF5, 0xF9, 0x22, 0x7F,
1030/*1EC0*/0x01, 0xE4, 0xFE, 0x0F, 0x0E, 0xBE, 0xFF, 0xFB,
1031 0x22, 0x01, 0x20, 0x00, 0x01, 0x04, 0x20, 0x00,
1032/*1ED0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1033 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1034/*1EE0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1036/*1EF0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1037 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1038/*1F00*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1039 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1040/*1F10*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1041 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1042/*1F20*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1043 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1044/*1F30*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1045 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1046/*1F40*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1047 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1048/*1F50*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1049 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1050/*1F60*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1051 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1052/*1F70*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1053 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1054/*1F80*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1056/*1F90*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1058/*1FA0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1059 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1060/*1FB0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1061 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1062/*1FC0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1063 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1064/*1FD0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1066/*1FE0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1067 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1068/*1FF0*/0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1069 0x01, 0x20, 0x11, 0x00, 0x04, 0x20, 0x00, 0x81
1070};
1071
1072int ipath_sd7220_ib_load(struct ipath_devdata *dd)
1073{
1074 return ipath_sd7220_prog_ld(dd, IB_7220_SERDES, ipath_sd7220_ib_img,
1075 sizeof(ipath_sd7220_ib_img), 0);
1076}
1077
1078int ipath_sd7220_ib_vfy(struct ipath_devdata *dd)
1079{
1080 return ipath_sd7220_prog_vfy(dd, IB_7220_SERDES, ipath_sd7220_ib_img,
1081 sizeof(ipath_sd7220_ib_img), 0);
1082}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 22:26:15 -0500