diff options
author | Len Brown <len.brown@intel.com> | 2010-07-07 00:12:03 -0400 |
---|---|---|
committer | Len Brown <len.brown@intel.com> | 2010-10-23 02:32:08 -0400 |
commit | d13780d439d08a57c87c1a07b6e76ddde61da1aa (patch) | |
tree | b172c1f43a206a22539d60782c3f28b1265e5c18 /drivers/idle | |
parent | 815c4163b6c8ebf8152f42b0a5fd015cfdcedc78 (diff) |
intel_idle: add initial Sandy Bridge support
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'drivers/idle')
-rwxr-xr-x | drivers/idle/intel_idle.c | 44 |
1 files changed, 43 insertions, 1 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index 54f0fb4cd5d..84476be69b3 100755 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c | |||
@@ -83,7 +83,7 @@ static unsigned int substates; | |||
83 | static int (*choose_substate)(int); | 83 | static int (*choose_substate)(int); |
84 | 84 | ||
85 | /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ | 85 | /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ |
86 | static unsigned int lapic_timer_reliable_states; | 86 | static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ |
87 | 87 | ||
88 | static struct cpuidle_device *intel_idle_cpuidle_devices; | 88 | static struct cpuidle_device *intel_idle_cpuidle_devices; |
89 | static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state); | 89 | static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state); |
@@ -126,6 +126,42 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = { | |||
126 | .enter = &intel_idle }, | 126 | .enter = &intel_idle }, |
127 | }; | 127 | }; |
128 | 128 | ||
129 | static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = { | ||
130 | { /* MWAIT C0 */ }, | ||
131 | { /* MWAIT C1 */ | ||
132 | .name = "SNB-C1", | ||
133 | .desc = "MWAIT 0x00", | ||
134 | .driver_data = (void *) 0x00, | ||
135 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
136 | .exit_latency = 1, | ||
137 | .target_residency = 4, | ||
138 | .enter = &intel_idle }, | ||
139 | { /* MWAIT C2 */ | ||
140 | .name = "SNB-C3", | ||
141 | .desc = "MWAIT 0x10", | ||
142 | .driver_data = (void *) 0x10, | ||
143 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
144 | .exit_latency = 80, | ||
145 | .target_residency = 160, | ||
146 | .enter = &intel_idle }, | ||
147 | { /* MWAIT C3 */ | ||
148 | .name = "SNB-C6", | ||
149 | .desc = "MWAIT 0x20", | ||
150 | .driver_data = (void *) 0x20, | ||
151 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
152 | .exit_latency = 104, | ||
153 | .target_residency = 208, | ||
154 | .enter = &intel_idle }, | ||
155 | { /* MWAIT C4 */ | ||
156 | .name = "SNB-C7", | ||
157 | .desc = "MWAIT 0x30", | ||
158 | .driver_data = (void *) 0x30, | ||
159 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
160 | .exit_latency = 109, | ||
161 | .target_residency = 300, | ||
162 | .enter = &intel_idle }, | ||
163 | }; | ||
164 | |||
129 | static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { | 165 | static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { |
130 | { /* MWAIT C0 */ }, | 166 | { /* MWAIT C0 */ }, |
131 | { /* MWAIT C1 */ | 167 | { /* MWAIT C1 */ |
@@ -312,6 +348,12 @@ static int intel_idle_probe(void) | |||
312 | cpuidle_state_table = atom_cstates; | 348 | cpuidle_state_table = atom_cstates; |
313 | choose_substate = choose_zero_substate; | 349 | choose_substate = choose_zero_substate; |
314 | break; | 350 | break; |
351 | |||
352 | case 0x2A: /* SNB */ | ||
353 | case 0x2D: /* SNB Xeon */ | ||
354 | cpuidle_state_table = snb_cstates; | ||
355 | choose_substate = choose_zero_substate; | ||
356 | break; | ||
315 | #ifdef FUTURE_USE | 357 | #ifdef FUTURE_USE |
316 | case 0x17: /* 23 - Core 2 Duo */ | 358 | case 0x17: /* 23 - Core 2 Duo */ |
317 | lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */ | 359 | lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */ |