aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/ide/pci/hpt366.c
diff options
context:
space:
mode:
authorSergei Shtylyov <sshtylyov@ru.mvista.com>2006-12-13 03:35:49 -0500
committerLinus Torvalds <torvalds@woody.osdl.org>2006-12-13 12:05:55 -0500
commit471a0bda5a2de5b0fd3b58255791eb831517a52c (patch)
tree6ddbac9495ae7a45a07aa511b957bb8488303e97 /drivers/ide/pci/hpt366.c
parent9448732f6c9ef4932b226056338d1084f3669752 (diff)
[PATCH] ide: optimize HPT37x timing tables
Save some space on the timing tables by introducing the separate transfer mode table in which the mode lookup is done to get the index into the timing table itself. Get rid of the rest of the obsolete/duplicate tables and use one set of tables for the whole HPT37x chip family like the HighPoint open-source drivers do. Documnent the different timing register layout for the HPT36x chip family (this is my guesswork based on the timing values). Have been tested and works fine on HPT370/302/371N. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/ide/pci/hpt366.c')
-rw-r--r--drivers/ide/pci/hpt366.c404
1 files changed, 174 insertions, 230 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index 51f40f2db77..787efd35db2 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -67,10 +67,9 @@
67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N) 67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
68 * - HPT371/N are single channel chips, so avoid touching the primary channel 68 * - HPT371/N are single channel chips, so avoid touching the primary channel
69 * which exists only virtually (there's no pins for it) 69 * which exists only virtually (there's no pins for it)
70 * - fix/remove bad/unused timing tables: HPT370/A 66 MHz tables weren't really 70 * - fix/remove bad/unused timing tables and use one set of tables for the whole
71 * needed and had many modes over- and underclocked, HPT372 33 MHz table was 71 * HPT37x chip family; save space by introducing the separate transfer mode
72 * for 66 MHz and 50 MHz table missed UltraDMA mode 6, HPT374 33 MHz table was 72 * table in which the mode lookup is done
73 * really for 50 MHz; switch to using HPT372 tables for HPT374...
74 * <source@mvista.com> 73 * <source@mvista.com>
75 * 74 *
76 */ 75 */
@@ -162,214 +161,168 @@ static const char *bad_ata33[] = {
162 NULL 161 NULL
163}; 162};
164 163
165struct chipset_bus_clock_list_entry { 164static u8 xfer_speeds[] = {
166 u8 xfer_speed; 165 XFER_UDMA_6,
167 unsigned int chipset_settings; 166 XFER_UDMA_5,
167 XFER_UDMA_4,
168 XFER_UDMA_3,
169 XFER_UDMA_2,
170 XFER_UDMA_1,
171 XFER_UDMA_0,
172
173 XFER_MW_DMA_2,
174 XFER_MW_DMA_1,
175 XFER_MW_DMA_0,
176
177 XFER_PIO_4,
178 XFER_PIO_3,
179 XFER_PIO_2,
180 XFER_PIO_1,
181 XFER_PIO_0
168}; 182};
169 183
170/* key for bus clock timings 184/* Key for bus clock timings
171 * bit 185 * 36x 37x
172 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW 186 * bits bits
173 * DMA. cycles = value + 1 187 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
174 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW 188 * cycles = value + 1
175 * DMA. cycles = value + 1 189 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
176 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file 190 * cycles = value + 1
177 * register access. 191 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
178 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file 192 * register access.
179 * register access. 193 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
180 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. 194 * register access.
181 * during task file register access. 195 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
182 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA 196 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
183 * xfer. 197 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
184 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task 198 * MW DMA xfer.
185 * register access. 199 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
186 * 28 UDMA enable 200 * task file register access.
187 * 29 DMA enable 201 * 28 28 UDMA enable.
188 * 30 PIO_MST enable. if set, the chip is in bus master mode during 202 * 29 29 DMA enable.
189 * PIO. 203 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
190 * 31 FIFO enable. 204 * PIO xfer.
205 * 31 31 FIFO enable.
191 */ 206 */
192static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
193 { XFER_UDMA_4, 0x900fd943 },
194 { XFER_UDMA_3, 0x900ad943 },
195 { XFER_UDMA_2, 0x900bd943 },
196 { XFER_UDMA_1, 0x9008d943 },
197 { XFER_UDMA_0, 0x9008d943 },
198
199 { XFER_MW_DMA_2, 0xa008d943 },
200 { XFER_MW_DMA_1, 0xa010d955 },
201 { XFER_MW_DMA_0, 0xa010d9fc },
202
203 { XFER_PIO_4, 0xc008d963 },
204 { XFER_PIO_3, 0xc010d974 },
205 { XFER_PIO_2, 0xc010d997 },
206 { XFER_PIO_1, 0xc010d9c7 },
207 { XFER_PIO_0, 0xc018d9d9 },
208 { 0, 0x0120d9d9 }
209};
210
211static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
212 { XFER_UDMA_4, 0x90c9a731 },
213 { XFER_UDMA_3, 0x90cfa731 },
214 { XFER_UDMA_2, 0x90caa731 },
215 { XFER_UDMA_1, 0x90cba731 },
216 { XFER_UDMA_0, 0x90c8a731 },
217
218 { XFER_MW_DMA_2, 0xa0c8a731 },
219 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
220 { XFER_MW_DMA_0, 0xa0c8a797 },
221
222 { XFER_PIO_4, 0xc0c8a731 },
223 { XFER_PIO_3, 0xc0c8a742 },
224 { XFER_PIO_2, 0xc0d0a753 },
225 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
226 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
227 { 0, 0x0120a7a7 }
228};
229 207
230static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = { 208static u32 forty_base_hpt36x[] = {
231 { XFER_UDMA_4, 0x90c98521 }, 209 /* XFER_UDMA_6 */ 0x900fd943,
232 { XFER_UDMA_3, 0x90cf8521 }, 210 /* XFER_UDMA_5 */ 0x900fd943,
233 { XFER_UDMA_2, 0x90cf8521 }, 211 /* XFER_UDMA_4 */ 0x900fd943,
234 { XFER_UDMA_1, 0x90cb8521 }, 212 /* XFER_UDMA_3 */ 0x900ad943,
235 { XFER_UDMA_0, 0x90cb8521 }, 213 /* XFER_UDMA_2 */ 0x900bd943,
236 214 /* XFER_UDMA_1 */ 0x9008d943,
237 { XFER_MW_DMA_2, 0xa0ca8521 }, 215 /* XFER_UDMA_0 */ 0x9008d943,
238 { XFER_MW_DMA_1, 0xa0ca8532 }, 216
239 { XFER_MW_DMA_0, 0xa0ca8575 }, 217 /* XFER_MW_DMA_2 */ 0xa008d943,
240 218 /* XFER_MW_DMA_1 */ 0xa010d955,
241 { XFER_PIO_4, 0xc0ca8521 }, 219 /* XFER_MW_DMA_0 */ 0xa010d9fc,
242 { XFER_PIO_3, 0xc0ca8532 }, 220
243 { XFER_PIO_2, 0xc0ca8542 }, 221 /* XFER_PIO_4 */ 0xc008d963,
244 { XFER_PIO_1, 0xc0d08572 }, 222 /* XFER_PIO_3 */ 0xc010d974,
245 { XFER_PIO_0, 0xc0d08585 }, 223 /* XFER_PIO_2 */ 0xc010d997,
246 { 0, 0x01208585 } 224 /* XFER_PIO_1 */ 0xc010d9c7,
225 /* XFER_PIO_0 */ 0xc018d9d9
247}; 226};
248 227
249/* from highpoint documentation. these are old values */ 228static u32 thirty_three_base_hpt36x[] = {
250static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = { 229 /* XFER_UDMA_6 */ 0x90c9a731,
251/* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */ 230 /* XFER_UDMA_5 */ 0x90c9a731,
252 { XFER_UDMA_5, 0x16454e31 }, 231 /* XFER_UDMA_4 */ 0x90c9a731,
253 { XFER_UDMA_4, 0x16454e31 }, 232 /* XFER_UDMA_3 */ 0x90cfa731,
254 { XFER_UDMA_3, 0x166d4e31 }, 233 /* XFER_UDMA_2 */ 0x90caa731,
255 { XFER_UDMA_2, 0x16494e31 }, 234 /* XFER_UDMA_1 */ 0x90cba731,
256 { XFER_UDMA_1, 0x164d4e31 }, 235 /* XFER_UDMA_0 */ 0x90c8a731,
257 { XFER_UDMA_0, 0x16514e31 }, 236
258 237 /* XFER_MW_DMA_2 */ 0xa0c8a731,
259 { XFER_MW_DMA_2, 0x26514e21 }, 238 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
260 { XFER_MW_DMA_1, 0x26514e33 }, 239 /* XFER_MW_DMA_0 */ 0xa0c8a797,
261 { XFER_MW_DMA_0, 0x26514e97 }, 240
262 241 /* XFER_PIO_4 */ 0xc0c8a731,
263 { XFER_PIO_4, 0x06514e21 }, 242 /* XFER_PIO_3 */ 0xc0c8a742,
264 { XFER_PIO_3, 0x06514e22 }, 243 /* XFER_PIO_2 */ 0xc0d0a753,
265 { XFER_PIO_2, 0x06514e33 }, 244 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
266 { XFER_PIO_1, 0x06914e43 }, 245 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
267 { XFER_PIO_0, 0x06914e57 },
268 { 0, 0x06514e57 }
269}; 246};
270 247
271/* these are the current (4 sep 2001) timings from highpoint */ 248static u32 twenty_five_base_hpt36x[] = {
272static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = { 249 /* XFER_UDMA_6 */ 0x90c98521,
273 { XFER_UDMA_5, 0x12446231 }, 250 /* XFER_UDMA_5 */ 0x90c98521,
274 { XFER_UDMA_4, 0x12446231 }, 251 /* XFER_UDMA_4 */ 0x90c98521,
275 { XFER_UDMA_3, 0x126c6231 }, 252 /* XFER_UDMA_3 */ 0x90cf8521,
276 { XFER_UDMA_2, 0x12486231 }, 253 /* XFER_UDMA_2 */ 0x90cf8521,
277 { XFER_UDMA_1, 0x124c6233 }, 254 /* XFER_UDMA_1 */ 0x90cb8521,
278 { XFER_UDMA_0, 0x12506297 }, 255 /* XFER_UDMA_0 */ 0x90cb8521,
279 256
280 { XFER_MW_DMA_2, 0x22406c31 }, 257 /* XFER_MW_DMA_2 */ 0xa0ca8521,
281 { XFER_MW_DMA_1, 0x22406c33 }, 258 /* XFER_MW_DMA_1 */ 0xa0ca8532,
282 { XFER_MW_DMA_0, 0x22406c97 }, 259 /* XFER_MW_DMA_0 */ 0xa0ca8575,
283 260
284 { XFER_PIO_4, 0x06414e31 }, 261 /* XFER_PIO_4 */ 0xc0ca8521,
285 { XFER_PIO_3, 0x06414e42 }, 262 /* XFER_PIO_3 */ 0xc0ca8532,
286 { XFER_PIO_2, 0x06414e53 }, 263 /* XFER_PIO_2 */ 0xc0ca8542,
287 { XFER_PIO_1, 0x06814e93 }, 264 /* XFER_PIO_1 */ 0xc0d08572,
288 { XFER_PIO_0, 0x06814ea7 }, 265 /* XFER_PIO_0 */ 0xc0d08585
289 { 0, 0x06814ea7 }
290}; 266};
291 267
292static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = { 268static u32 thirty_three_base_hpt37x[] = {
293 { XFER_UDMA_5, 0x12848242 }, 269 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
294 { XFER_UDMA_4, 0x12ac8242 }, 270 /* XFER_UDMA_5 */ 0x12446231,
295 { XFER_UDMA_3, 0x128c8242 }, 271 /* XFER_UDMA_4 */ 0x12446231,
296 { XFER_UDMA_2, 0x120c8242 }, 272 /* XFER_UDMA_3 */ 0x126c6231,
297 { XFER_UDMA_1, 0x12148254 }, 273 /* XFER_UDMA_2 */ 0x12486231,
298 { XFER_UDMA_0, 0x121882ea }, 274 /* XFER_UDMA_1 */ 0x124c6233,
299 275 /* XFER_UDMA_0 */ 0x12506297,
300 { XFER_MW_DMA_2, 0x22808242 }, 276
301 { XFER_MW_DMA_1, 0x22808254 }, 277 /* XFER_MW_DMA_2 */ 0x22406c31,
302 { XFER_MW_DMA_0, 0x228082ea }, 278 /* XFER_MW_DMA_1 */ 0x22406c33,
303 279 /* XFER_MW_DMA_0 */ 0x22406c97,
304 { XFER_PIO_4, 0x0a81f442 }, 280
305 { XFER_PIO_3, 0x0a81f443 }, 281 /* XFER_PIO_4 */ 0x06414e31,
306 { XFER_PIO_2, 0x0a81f454 }, 282 /* XFER_PIO_3 */ 0x06414e42,
307 { XFER_PIO_1, 0x0ac1f465 }, 283 /* XFER_PIO_2 */ 0x06414e53,
308 { XFER_PIO_0, 0x0ac1f48a }, 284 /* XFER_PIO_1 */ 0x06814e93,
309 { 0, 0x0ac1f48a } 285 /* XFER_PIO_0 */ 0x06814ea7
310}; 286};
311 287
312static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = { 288static u32 fifty_base_hpt37x[] = {
313 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ 289 /* XFER_UDMA_6 */ 0x12848242,
314 { XFER_UDMA_5, 0x12446231 }, 290 /* XFER_UDMA_5 */ 0x12848242,
315 { XFER_UDMA_4, 0x12446231 }, 291 /* XFER_UDMA_4 */ 0x12ac8242,
316 { XFER_UDMA_3, 0x126c6231 }, 292 /* XFER_UDMA_3 */ 0x128c8242,
317 { XFER_UDMA_2, 0x12486231 }, 293 /* XFER_UDMA_2 */ 0x120c8242,
318 { XFER_UDMA_1, 0x124c6233 }, 294 /* XFER_UDMA_1 */ 0x12148254,
319 { XFER_UDMA_0, 0x12506297 }, 295 /* XFER_UDMA_0 */ 0x121882ea,
320 296
321 { XFER_MW_DMA_2, 0x22406c31 }, 297 /* XFER_MW_DMA_2 */ 0x22808242,
322 { XFER_MW_DMA_1, 0x22406c33 }, 298 /* XFER_MW_DMA_1 */ 0x22808254,
323 { XFER_MW_DMA_0, 0x22406c97 }, 299 /* XFER_MW_DMA_0 */ 0x228082ea,
324 300
325 { XFER_PIO_4, 0x06414e31 }, 301 /* XFER_PIO_4 */ 0x0a81f442,
326 { XFER_PIO_3, 0x06414e42 }, 302 /* XFER_PIO_3 */ 0x0a81f443,
327 { XFER_PIO_2, 0x06414e53 }, 303 /* XFER_PIO_2 */ 0x0a81f454,
328 { XFER_PIO_1, 0x06814e93 }, 304 /* XFER_PIO_1 */ 0x0ac1f465,
329 { XFER_PIO_0, 0x06814ea7 }, 305 /* XFER_PIO_0 */ 0x0ac1f48a
330 { 0, 0x06814ea7 }
331}; 306};
332 307
333static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = { 308static u32 sixty_six_base_hpt37x[] = {
334 { XFER_UDMA_6, 0x12848242 }, 309 /* XFER_UDMA_6 */ 0x1c869c62,
335 { XFER_UDMA_5, 0x12848242 }, 310 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
336 { XFER_UDMA_4, 0x12ac8242 }, 311 /* XFER_UDMA_4 */ 0x1c8a9c62,
337 { XFER_UDMA_3, 0x128c8242 }, 312 /* XFER_UDMA_3 */ 0x1c8e9c62,
338 { XFER_UDMA_2, 0x120c8242 }, 313 /* XFER_UDMA_2 */ 0x1c929c62,
339 { XFER_UDMA_1, 0x12148254 }, 314 /* XFER_UDMA_1 */ 0x1c9a9c62,
340 { XFER_UDMA_0, 0x121882ea }, 315 /* XFER_UDMA_0 */ 0x1c829c62,
341 316
342 { XFER_MW_DMA_2, 0x22808242 }, 317 /* XFER_MW_DMA_2 */ 0x2c829c62,
343 { XFER_MW_DMA_1, 0x22808254 }, 318 /* XFER_MW_DMA_1 */ 0x2c829c66,
344 { XFER_MW_DMA_0, 0x228082ea }, 319 /* XFER_MW_DMA_0 */ 0x2c829d2e,
345 320
346 { XFER_PIO_4, 0x0a81f442 }, 321 /* XFER_PIO_4 */ 0x0c829c62,
347 { XFER_PIO_3, 0x0a81f443 }, 322 /* XFER_PIO_3 */ 0x0c829c84,
348 { XFER_PIO_2, 0x0a81f454 }, 323 /* XFER_PIO_2 */ 0x0c829ca6,
349 { XFER_PIO_1, 0x0ac1f465 }, 324 /* XFER_PIO_1 */ 0x0d029d26,
350 { XFER_PIO_0, 0x0ac1f48a }, 325 /* XFER_PIO_0 */ 0x0d029d5e
351 { 0, 0x0a81f443 }
352};
353
354static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
355 { XFER_UDMA_6, 0x1c869c62 },
356 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
357 { XFER_UDMA_4, 0x1c8a9c62 },
358 { XFER_UDMA_3, 0x1c8e9c62 },
359 { XFER_UDMA_2, 0x1c929c62 },
360 { XFER_UDMA_1, 0x1c9a9c62 },
361 { XFER_UDMA_0, 0x1c829c62 },
362
363 { XFER_MW_DMA_2, 0x2c829c62 },
364 { XFER_MW_DMA_1, 0x2c829c66 },
365 { XFER_MW_DMA_0, 0x2c829d2e },
366
367 { XFER_PIO_4, 0x0c829c62 },
368 { XFER_PIO_3, 0x0c829c84 },
369 { XFER_PIO_2, 0x0c829ca6 },
370 { XFER_PIO_1, 0x0d029d26 },
371 { XFER_PIO_0, 0x0d029d5e },
372 { 0, 0x0d029d26 }
373}; 326};
374 327
375#define HPT366_DEBUG_DRIVE_INFO 0 328#define HPT366_DEBUG_DRIVE_INFO 0
@@ -401,7 +354,7 @@ struct hpt_info
401#define IS_3xxN 2 354#define IS_3xxN 2
402#define PCI_66MHZ 4 355#define PCI_66MHZ 4
403 /* Speed table */ 356 /* Speed table */
404 struct chipset_bus_clock_list_entry *speed; 357 u32 *speed;
405}; 358};
406 359
407/* 360/*
@@ -538,12 +491,20 @@ static int check_in_drive_lists (ide_drive_t *drive, const char **list)
538 return 0; 491 return 0;
539} 492}
540 493
541static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table) 494static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
542{ 495{
543 for ( ; chipset_table->xfer_speed ; chipset_table++) 496 int i;
544 if (chipset_table->xfer_speed == speed) 497
545 return chipset_table->chipset_settings; 498 /*
546 return chipset_table->chipset_settings; 499 * Lookup the transfer mode table to get the index into
500 * the timing table.
501 *
502 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
503 */
504 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
505 if (xfer_speeds[i] == speed)
506 break;
507 return chipset_table[i];
547} 508}
548 509
549static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed) 510static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
@@ -1061,14 +1022,14 @@ static void __devinit hpt366_clocking(ide_hwif_t *hwif)
1061 /* detect bus speed by looking at control reg timing: */ 1022 /* detect bus speed by looking at control reg timing: */
1062 switch((reg1 >> 8) & 7) { 1023 switch((reg1 >> 8) & 7) {
1063 case 5: 1024 case 5:
1064 info->speed = forty_base_hpt366; 1025 info->speed = forty_base_hpt36x;
1065 break; 1026 break;
1066 case 9: 1027 case 9:
1067 info->speed = twenty_five_base_hpt366; 1028 info->speed = twenty_five_base_hpt36x;
1068 break; 1029 break;
1069 case 7: 1030 case 7:
1070 default: 1031 default:
1071 info->speed = thirty_three_base_hpt366; 1032 info->speed = thirty_three_base_hpt36x;
1072 break; 1033 break;
1073 } 1034 }
1074} 1035}
@@ -1131,27 +1092,16 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1131 pll = F_LOW_PCI_66; 1092 pll = F_LOW_PCI_66;
1132 1093
1133 if (pll == F_LOW_PCI_33) { 1094 if (pll == F_LOW_PCI_33) {
1134 if (info->revision >= 5) 1095 info->speed = thirty_three_base_hpt37x;
1135 info->speed = thirty_three_base_hpt372;
1136 else if (info->revision >= 4)
1137 info->speed = thirty_three_base_hpt370a;
1138 else
1139 info->speed = thirty_three_base_hpt370;
1140 printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n"); 1096 printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1141 } else if (pll == F_LOW_PCI_40) { 1097 } else if (pll == F_LOW_PCI_40) {
1142 /* Unsupported */ 1098 /* Unsupported */
1143 } else if (pll == F_LOW_PCI_50) { 1099 } else if (pll == F_LOW_PCI_50) {
1144 if (info->revision >= 5) 1100 info->speed = fifty_base_hpt37x;
1145 info->speed = fifty_base_hpt372;
1146 else
1147 info->speed = fifty_base_hpt370a;
1148 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n"); 1101 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1149 } else { 1102 } else {
1150 if (info->revision >= 5) { 1103 info->speed = sixty_six_base_hpt37x;
1151 info->speed = sixty_six_base_hpt372; 1104 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1152 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1153 } else
1154 printk(KERN_ERR "HPT37x: 66MHz timings not supported.\n");
1155 } 1105 }
1156 } 1106 }
1157 1107
@@ -1201,14 +1151,8 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1201 pci_write_config_dword(dev, 0x5c, 1151 pci_write_config_dword(dev, 0x5c,
1202 pll & ~0x100); 1152 pll & ~0x100);
1203 pci_write_config_byte(dev, 0x5b, 0x21); 1153 pci_write_config_byte(dev, 0x5b, 0x21);
1204 if (info->revision >= 8) 1154
1205 info->speed = fifty_base_hpt370a; 1155 info->speed = fifty_base_hpt37x;
1206 else if (info->revision >= 5)
1207 info->speed = fifty_base_hpt372;
1208 else if (info->revision >= 4)
1209 info->speed = fifty_base_hpt370a;
1210 else
1211 info->speed = fifty_base_hpt370a;
1212 printk("HPT37X: using 50MHz internal PLL\n"); 1156 printk("HPT37X: using 50MHz internal PLL\n");
1213 goto init_hpt37X_done; 1157 goto init_hpt37X_done;
1214 } 1158 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 20:04:57 -0400