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authorDaniel Kurtz <djkurtz@chromium.org>2012-07-24 08:13:58 -0400
committerJean Delvare <khali@endymion.delvare>2012-07-24 08:13:58 -0400
commitedbeea63839cf0ea169c3e0737d49a96b2ca8388 (patch)
tree0b62790ab16a4a7e0d081695036645786c906237 /drivers/i2c
parent70a1cc1952355404a5746c88757f5a444df52b04 (diff)
i2c-i801: Rename some SMBHSTCNT bit constants
Rename the SMBHSTCNT register bit access constants to match the style of other register bits. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Jean Delvare <khali@linux-fr.org>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/i2c-i801.c21
1 files changed, 11 insertions, 10 deletions
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 40a50f78097..016fa22f135 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -102,9 +102,6 @@
102#define SMBAUXCTL_CRC 1 102#define SMBAUXCTL_CRC 1
103#define SMBAUXCTL_E32B 2 103#define SMBAUXCTL_E32B 2
104 104
105/* kill bit for SMBHSTCNT */
106#define SMBHSTCNT_KILL 2
107
108/* Other settings */ 105/* Other settings */
109#define MAX_RETRIES 400 106#define MAX_RETRIES 400
110#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */ 107#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
@@ -117,9 +114,13 @@
117#define I801_PROC_CALL 0x10 /* unimplemented */ 114#define I801_PROC_CALL 0x10 /* unimplemented */
118#define I801_BLOCK_DATA 0x14 115#define I801_BLOCK_DATA 0x14
119#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 116#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
120#define I801_LAST_BYTE 0x20 117
121#define I801_START 0x40 118/* I801 Host Control register bits */
122#define I801_PEC_EN 0x80 /* ICH3 and later */ 119#define SMBHSTCNT_INTREN 0x01
120#define SMBHSTCNT_KILL 0x02
121#define SMBHSTCNT_LAST_BYTE 0x20
122#define SMBHSTCNT_START 0x40
123#define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
123 124
124/* I801 Hosts Status register bits */ 125/* I801 Hosts Status register bits */
125#define SMBHSTSTS_BYTE_DONE 0x80 126#define SMBHSTSTS_BYTE_DONE 0x80
@@ -271,7 +272,7 @@ static int i801_transaction(struct i801_priv *priv, int xact)
271 272
272 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 273 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
273 * INTREN, SMBSCMD are passed in xact */ 274 * INTREN, SMBSCMD are passed in xact */
274 outb_p(xact | I801_START, SMBHSTCNT(priv)); 275 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
275 276
276 /* We will always wait for a fraction of a second! */ 277 /* We will always wait for a fraction of a second! */
277 do { 278 do {
@@ -323,7 +324,7 @@ static int i801_block_transaction_by_block(struct i801_priv *priv,
323 } 324 }
324 325
325 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 | 326 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
326 I801_PEC_EN * hwpec); 327 (hwpec ? SMBHSTCNT_PEC_EN : 0));
327 if (status) 328 if (status)
328 return status; 329 return status;
329 330
@@ -374,11 +375,11 @@ static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
374 375
375 for (i = 1; i <= len; i++) { 376 for (i = 1; i <= len; i++) {
376 if (i == len && read_write == I2C_SMBUS_READ) 377 if (i == len && read_write == I2C_SMBUS_READ)
377 smbcmd |= I801_LAST_BYTE; 378 smbcmd |= SMBHSTCNT_LAST_BYTE;
378 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv)); 379 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
379 380
380 if (i == 1) 381 if (i == 1)
381 outb_p(inb(SMBHSTCNT(priv)) | I801_START, 382 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
382 SMBHSTCNT(priv)); 383 SMBHSTCNT(priv));
383 384
384 /* We will always wait for a fraction of a second! */ 385 /* We will always wait for a fraction of a second! */