diff options
author | Dirk Brandewie <dirk.brandewie@gmail.com> | 2011-10-06 14:26:34 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2011-10-29 06:03:51 -0400 |
commit | f3fa9f3da5621154323775ff0efdba99dcebcee4 (patch) | |
tree | 0d4fdd567d8f9c1f85d1de41dff8b4019e8a289e /drivers/i2c/busses/i2c-designware-core.h | |
parent | af06cf6c8cb600803951ddabe6fb034126752488 (diff) |
i2c-designware: Push all register reads/writes into the core code.
Move all register manipulation code into the core, also move register
offset definitions to i2c-designware-core.c since the bus specific
portions of the driver no longer need/use them.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'drivers/i2c/busses/i2c-designware-core.h')
-rw-r--r-- | drivers/i2c/busses/i2c-designware-core.h | 104 |
1 files changed, 5 insertions, 99 deletions
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h index 29386215fe3..dc016e2afe9 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h | |||
@@ -26,40 +26,6 @@ | |||
26 | * | 26 | * |
27 | */ | 27 | */ |
28 | 28 | ||
29 | /* | ||
30 | * Registers offset | ||
31 | */ | ||
32 | #define DW_IC_CON 0x0 | ||
33 | #define DW_IC_TAR 0x4 | ||
34 | #define DW_IC_DATA_CMD 0x10 | ||
35 | #define DW_IC_SS_SCL_HCNT 0x14 | ||
36 | #define DW_IC_SS_SCL_LCNT 0x18 | ||
37 | #define DW_IC_FS_SCL_HCNT 0x1c | ||
38 | #define DW_IC_FS_SCL_LCNT 0x20 | ||
39 | #define DW_IC_INTR_STAT 0x2c | ||
40 | #define DW_IC_INTR_MASK 0x30 | ||
41 | #define DW_IC_RAW_INTR_STAT 0x34 | ||
42 | #define DW_IC_RX_TL 0x38 | ||
43 | #define DW_IC_TX_TL 0x3c | ||
44 | #define DW_IC_CLR_INTR 0x40 | ||
45 | #define DW_IC_CLR_RX_UNDER 0x44 | ||
46 | #define DW_IC_CLR_RX_OVER 0x48 | ||
47 | #define DW_IC_CLR_TX_OVER 0x4c | ||
48 | #define DW_IC_CLR_RD_REQ 0x50 | ||
49 | #define DW_IC_CLR_TX_ABRT 0x54 | ||
50 | #define DW_IC_CLR_RX_DONE 0x58 | ||
51 | #define DW_IC_CLR_ACTIVITY 0x5c | ||
52 | #define DW_IC_CLR_STOP_DET 0x60 | ||
53 | #define DW_IC_CLR_START_DET 0x64 | ||
54 | #define DW_IC_CLR_GEN_CALL 0x68 | ||
55 | #define DW_IC_ENABLE 0x6c | ||
56 | #define DW_IC_STATUS 0x70 | ||
57 | #define DW_IC_TXFLR 0x74 | ||
58 | #define DW_IC_RXFLR 0x78 | ||
59 | #define DW_IC_TX_ABRT_SOURCE 0x80 | ||
60 | #define DW_IC_COMP_PARAM_1 0xf4 | ||
61 | #define DW_IC_COMP_TYPE 0xfc | ||
62 | #define DW_IC_COMP_TYPE_VALUE 0x44570140 | ||
63 | 29 | ||
64 | #define DW_IC_CON_MASTER 0x1 | 30 | #define DW_IC_CON_MASTER 0x1 |
65 | #define DW_IC_CON_SPEED_STD 0x2 | 31 | #define DW_IC_CON_SPEED_STD 0x2 |
@@ -68,72 +34,7 @@ | |||
68 | #define DW_IC_CON_RESTART_EN 0x20 | 34 | #define DW_IC_CON_RESTART_EN 0x20 |
69 | #define DW_IC_CON_SLAVE_DISABLE 0x40 | 35 | #define DW_IC_CON_SLAVE_DISABLE 0x40 |
70 | 36 | ||
71 | #define DW_IC_INTR_RX_UNDER 0x001 | ||
72 | #define DW_IC_INTR_RX_OVER 0x002 | ||
73 | #define DW_IC_INTR_RX_FULL 0x004 | ||
74 | #define DW_IC_INTR_TX_OVER 0x008 | ||
75 | #define DW_IC_INTR_TX_EMPTY 0x010 | ||
76 | #define DW_IC_INTR_RD_REQ 0x020 | ||
77 | #define DW_IC_INTR_TX_ABRT 0x040 | ||
78 | #define DW_IC_INTR_RX_DONE 0x080 | ||
79 | #define DW_IC_INTR_ACTIVITY 0x100 | ||
80 | #define DW_IC_INTR_STOP_DET 0x200 | ||
81 | #define DW_IC_INTR_START_DET 0x400 | ||
82 | #define DW_IC_INTR_GEN_CALL 0x800 | ||
83 | |||
84 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ | ||
85 | DW_IC_INTR_TX_EMPTY | \ | ||
86 | DW_IC_INTR_TX_ABRT | \ | ||
87 | DW_IC_INTR_STOP_DET) | ||
88 | |||
89 | #define DW_IC_STATUS_ACTIVITY 0x1 | ||
90 | |||
91 | #define DW_IC_ERR_TX_ABRT 0x1 | ||
92 | |||
93 | /* | ||
94 | * status codes | ||
95 | */ | ||
96 | #define STATUS_IDLE 0x0 | ||
97 | #define STATUS_WRITE_IN_PROGRESS 0x1 | ||
98 | #define STATUS_READ_IN_PROGRESS 0x2 | ||
99 | |||
100 | #define TIMEOUT 20 /* ms */ | ||
101 | |||
102 | /* | ||
103 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | ||
104 | * | ||
105 | * only expected abort codes are listed here | ||
106 | * refer to the datasheet for the full list | ||
107 | */ | ||
108 | #define ABRT_7B_ADDR_NOACK 0 | ||
109 | #define ABRT_10ADDR1_NOACK 1 | ||
110 | #define ABRT_10ADDR2_NOACK 2 | ||
111 | #define ABRT_TXDATA_NOACK 3 | ||
112 | #define ABRT_GCALL_NOACK 4 | ||
113 | #define ABRT_GCALL_READ 5 | ||
114 | #define ABRT_SBYTE_ACKDET 7 | ||
115 | #define ABRT_SBYTE_NORSTRT 9 | ||
116 | #define ABRT_10B_RD_NORSTRT 10 | ||
117 | #define ABRT_MASTER_DIS 11 | ||
118 | #define ARB_LOST 12 | ||
119 | |||
120 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) | ||
121 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | ||
122 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | ||
123 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | ||
124 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | ||
125 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | ||
126 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | ||
127 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | ||
128 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | ||
129 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | ||
130 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | ||
131 | 37 | ||
132 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | ||
133 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | ||
134 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | ||
135 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | ||
136 | DW_IC_TX_ABRT_GCALL_NOACK) | ||
137 | /** | 38 | /** |
138 | * struct dw_i2c_dev - private i2c-designware data | 39 | * struct dw_i2c_dev - private i2c-designware data |
139 | * @dev: driver model device node | 40 | * @dev: driver model device node |
@@ -195,3 +96,8 @@ extern int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], | |||
195 | int num); | 96 | int num); |
196 | extern u32 i2c_dw_func(struct i2c_adapter *adap); | 97 | extern u32 i2c_dw_func(struct i2c_adapter *adap); |
197 | extern irqreturn_t i2c_dw_isr(int this_irq, void *dev_id); | 98 | extern irqreturn_t i2c_dw_isr(int this_irq, void *dev_id); |
99 | extern void i2c_dw_enable(struct dw_i2c_dev *dev); | ||
100 | extern void i2c_dw_disable(struct dw_i2c_dev *dev); | ||
101 | extern void i2c_dw_clear_int(struct dw_i2c_dev *dev); | ||
102 | extern void i2c_dw_disable_int(struct dw_i2c_dev *dev); | ||
103 | extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev); | ||