diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2011-10-25 11:34:51 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-11-01 12:02:01 -0400 |
| commit | b4f15f808b9a79b6ad9032fa5f6d8b88e1e1bf11 (patch) | |
| tree | 1ce43b134b5594cd9332539bcc1d3b45143c77ce /drivers/gpu | |
| parent | 00dfb8df5bf8c3afe4c0bb8361133156b06b7a2c (diff) | |
drm/radeon/kms: cleanup atombios_adjust_pll()
The logic was messy and hard to follow.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 41 |
1 files changed, 13 insertions, 28 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index a515b2a09d8..4901179b260 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
| @@ -638,38 +638,23 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
| 638 | if (ss_enabled && ss->percentage) | 638 | if (ss_enabled && ss->percentage) |
| 639 | args.v3.sInput.ucDispPllConfig |= | 639 | args.v3.sInput.ucDispPllConfig |= |
| 640 | DISPPLL_CONFIG_SS_ENABLE; | 640 | DISPPLL_CONFIG_SS_ENABLE; |
| 641 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) || | 641 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { |
| 642 | radeon_encoder_is_dp_bridge(encoder)) { | 642 | args.v3.sInput.ucDispPllConfig |= |
| 643 | DISPPLL_CONFIG_COHERENT_MODE; | ||
| 644 | /* 16200 or 27000 */ | ||
| 645 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | ||
| 646 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | ||
| 643 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 647 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 644 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { | 648 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) |
| 649 | /* deep color support */ | ||
| 650 | args.v3.sInput.usPixelClock = | ||
| 651 | cpu_to_le16((mode->clock * bpc / 8) / 10); | ||
| 652 | if (dig->coherent_mode) | ||
| 645 | args.v3.sInput.ucDispPllConfig |= | 653 | args.v3.sInput.ucDispPllConfig |= |
| 646 | DISPPLL_CONFIG_COHERENT_MODE; | 654 | DISPPLL_CONFIG_COHERENT_MODE; |
| 647 | /* 16200 or 27000 */ | 655 | if (mode->clock > 165000) |
| 648 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | ||
| 649 | } else { | ||
| 650 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { | ||
| 651 | /* deep color support */ | ||
| 652 | args.v3.sInput.usPixelClock = | ||
| 653 | cpu_to_le16((mode->clock * bpc / 8) / 10); | ||
| 654 | } | ||
| 655 | if (dig->coherent_mode) | ||
| 656 | args.v3.sInput.ucDispPllConfig |= | ||
| 657 | DISPPLL_CONFIG_COHERENT_MODE; | ||
| 658 | if (mode->clock > 165000) | ||
| 659 | args.v3.sInput.ucDispPllConfig |= | ||
| 660 | DISPPLL_CONFIG_DUAL_LINK; | ||
| 661 | } | ||
| 662 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | ||
| 663 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { | ||
| 664 | args.v3.sInput.ucDispPllConfig |= | 656 | args.v3.sInput.ucDispPllConfig |= |
| 665 | DISPPLL_CONFIG_COHERENT_MODE; | 657 | DISPPLL_CONFIG_DUAL_LINK; |
| 666 | /* 16200 or 27000 */ | ||
| 667 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | ||
| 668 | } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) { | ||
| 669 | if (mode->clock > 165000) | ||
| 670 | args.v3.sInput.ucDispPllConfig |= | ||
| 671 | DISPPLL_CONFIG_DUAL_LINK; | ||
| 672 | } | ||
| 673 | } | 658 | } |
| 674 | if (radeon_encoder_is_dp_bridge(encoder)) { | 659 | if (radeon_encoder_is_dp_bridge(encoder)) { |
| 675 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); | 660 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |