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authorEric Anholt <eric@anholt.net>2010-03-09 02:41:55 -0500
committerEric Anholt <eric@anholt.net>2010-03-17 15:59:32 -0400
commit71cf39b117d5aa817a4693f4478397e6b04bee25 (patch)
tree7c7dd6fb84629e4fbc7b4c70f1b55889bcf0d200 /drivers/gpu
parent4967790112b284f276c5065dc724f7340a2fd7a5 (diff)
drm/i915: Enable VS timer dispatch.
This could resolve HW deadlocks where a unit downstream of the VS is waiting for more input, the VS has one vertex queued up but not dispatched because it hopes to get one more vertex for 2x4 dispatch, and software isn't handing more vertices down because it's waiting for rendering to complete. The B-Spec says you should always have this bit set. Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c5
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h4
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e52a277814c..134973f7706 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4725,6 +4725,11 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
4725 ring->space += ring->Size; 4725 ring->space += ring->Size;
4726 } 4726 }
4727 4727
4728 if (IS_I9XX(dev) && !IS_GEN3(dev)) {
4729 I915_WRITE(MI_MODE,
4730 (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
4731 }
4732
4728 return 0; 4733 return 0;
4729} 4734}
4730 4735
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fcc4c9efc0..2720bc2cd67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -298,6 +298,10 @@
298#define INSTDONE 0x02090 298#define INSTDONE 0x02090
299#define NOPID 0x02094 299#define NOPID 0x02094
300#define HWSTAM 0x02098 300#define HWSTAM 0x02098
301
302#define MI_MODE 0x0209c
303# define VS_TIMER_DISPATCH (1 << 6)
304
301#define SCPD0 0x0209c /* 915+ only */ 305#define SCPD0 0x0209c /* 915+ only */
302#define IER 0x020a0 306#define IER 0x020a0
303#define IIR 0x020a4 307#define IIR 0x020a4