drm/i915: Implement WaSetupGtModeTdRowDispatch

I'm not really sure, since the w/a entry is as thin on details as
ever, and Bspec doesn't say anything about it. But I've figured only
dispatching to rows 0&1 instead of all four should be the right thing
for GT1.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Add the missing snb server GT1 to the check, spotted by Chris
Wilson.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

3 files changed, 10 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 557843dd4b2..062a60b381b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1166,6 +1166,9 @@ struct drm_i915_file_private {
 #define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
                                  (dev)->pci_device == 0x0152 || \
                                  (dev)->pci_device == 0x015a)
+#define IS_SNB_GT1(dev)         ((dev)->pci_device == 0x0102 || \
+                                 (dev)->pci_device == 0x0106 || \
+                                 (dev)->pci_device == 0x010A)
 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e0019378f8b..186ee5c85b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -533,7 +533,8 @@
 # define MI_FLUSH_ENABLE                                (1 << 12)
 
 #define GEN6_GT_MODE    0x20d0
-#define   GEN6_GT_MODE_HI       (1 << 9)
+#define   GEN6_GT_MODE_HI                               (1 << 9)
+#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
 
 #define GFX_MODE        0x02520
 #define GFX_MODE_GEN7   0x0229c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3b85660ce4e..55f7a896a12 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3596,6 +3596,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
         I915_WRITE(_3D_CHICKEN,
                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
 
+        /* WaSetupGtModeTdRowDispatch */
+        if (IS_SNB_GT1(dev))
+                I915_WRITE(GEN6_GT_MODE,
+                           _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
+
         I915_WRITE(WM3_LP_ILK, 0);
         I915_WRITE(WM2_LP_ILK, 0);
         I915_WRITE(WM1_LP_ILK, 0);