drm/nv50: use pll type rather than register for CRTC PLL

Just in case someone, somewhere, does something difficult.  This also
removes one path that was different between fermi and non-fermi.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 14 insertions, 19 deletions

diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index d819eb935a2..1686f8291b6 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -266,15 +266,10 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
 {
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct pll_lims pll;
-        uint32_t reg, reg1, reg2;
+        uint32_t reg1, reg2;
         int ret, N1, M1, N2, M2, P;
 
-        if (dev_priv->chipset < NV_C0)
-                reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);
-        else
-                reg = 0x614140 + (head * 0x800);
-
-        ret = get_pll_limits(dev, reg, &pll);
+        ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll);
         if (ret)
                 return ret;
 
@@ -286,11 +281,11 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
                 NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
                          pclk, ret, N1, M1, N2, M2, P);
 
-                reg1 = nv_rd32(dev, reg + 4) & 0xff00ff00;
-                reg2 = nv_rd32(dev, reg + 8) & 0x8000ff00;
-                nv_wr32(dev, reg, 0x10000611);
-                nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1);
-                nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
+                reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00;
+                reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00;
+                nv_wr32(dev, pll.reg + 0, 0x10000611);
+                nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1);
+                nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
         } else
         if (dev_priv->chipset < NV_C0) {
                 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
@@ -300,10 +295,10 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
                 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
                          pclk, ret, N1, N2, M1, P);
 
-                reg1 = nv_rd32(dev, reg + 4) & 0xffc00000;
-                nv_wr32(dev, reg, 0x50000610);
-                nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
-                nv_wr32(dev, reg + 8, N2);
+                reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000;
+                nv_wr32(dev, pll.reg + 0, 0x50000610);
+                nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
+                nv_wr32(dev, pll.reg + 8, N2);
         } else {
                 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
                 if (ret <= 0)
@@ -312,9 +307,9 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
                 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
                          pclk, ret, N1, N2, M1, P);
 
-                nv_mask(dev, reg + 0x0c, 0x00000000, 0x00000100);
-                nv_wr32(dev, reg + 0x04, (P << 16) | (N1 << 8) | M1);
-                nv_wr32(dev, reg + 0x10, N2 << 16);
+                nv_mask(dev, pll.reg + 0x0c, 0x00000000, 0x00000100);
+                nv_wr32(dev, pll.reg + 0x04, (P << 16) | (N1 << 8) | M1);
+                nv_wr32(dev, pll.reg + 0x10, N2 << 16);
         }
 
         return 0;