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authorDave Airlie <airlied@redhat.com>2012-12-07 22:17:07 -0500
committerDave Airlie <airlied@redhat.com>2012-12-10 05:03:58 -0500
commit1a1494def7eacbd25db05185aa2e81ef90892460 (patch)
tree40911f075b1fe527c6d20bf8c3070d4cdca11e97 /drivers/gpu
parent8de9e417757fb9f130f55a38f4ee7027b60de1c7 (diff)
parent71bfe916ebe6d026cd3d0e41c398574fc1228e03 (diff)
Merge branch 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes: Pretty minor -next pull request. We some additional new bits waiting internally for release. Hopefully Monday we can get at least some of them out. The others will probably take a few more weeks. Highlights of the current request: - ELD registers for passing audio information to the sound hardware - Handle GPUVM page faults more gracefully - Misc fixes Merge radeon test * 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux: (483 commits) drm/radeon: bump driver version for new info ioctl requests drm/radeon: fix eDP clk and lane setup for scaled modes drm/radeon: add new INFO ioctl requests drm/radeon/dce32+: use fractional fb dividers for high clocks drm/radeon: use cached memory when evicting for vram on non agp drm/radeon: add a CS flag END_OF_FRAME drm/radeon: stop page faults from hanging the system (v2) drm/radeon/dce4/5: add registers for ELD handling drm/radeon/dce3.2: add registers for ELD handling radeon: fix pll/ctrc mapping on dce2 and dce3 hardware Linux 3.7-rc7 powerpc/eeh: Do not invalidate PE properly Revert "drm/i915: enable rc6 on ilk again" ALSA: hda - Fix build without CONFIG_PM of/address: sparc: Declare of_iomap as an extern function for sparc again PM / QoS: fix wrong error-checking condition bnx2x: remove redundant warning log vxlan: fix command usage in its doc 8139cp: revert "set ring address before enabling receiver" MPI: Fix compilation on MIPS with GCC 4.4 and newer ... Conflicts: drivers/gpu/drm/exynos/exynos_drm_encoder.c drivers/gpu/drm/exynos/exynos_drm_fbdev.c drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/drm_fops.c44
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_encoder.c10
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c11
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c11
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c12
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c39
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.c29
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c12
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv40.c8
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv40.h2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/include/core/object.h14
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/clock.h3
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c19
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_abi16.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c3
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c46
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c4
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c14
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c3
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h55
-rw-r--r--drivers/gpu/drm/radeon/ni.c16
-rw-r--r--drivers/gpu/drm/radeon/nid.h11
-rw-r--r--drivers/gpu/drm/radeon/radeon_agp.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c18
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h48
-rw-r--r--drivers/gpu/drm/radeon/si.c26
-rw-r--r--drivers/gpu/drm/radeon/sid.h15
-rw-r--r--drivers/gpu/drm/ttm/ttm_page_alloc.c5
-rw-r--r--drivers/gpu/drm/ttm/ttm_tt.c4
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c5
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c2
40 files changed, 410 insertions, 120 deletions
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 7ef1b673e1b..133b4132983 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -121,6 +121,8 @@ int drm_open(struct inode *inode, struct file *filp)
121 int minor_id = iminor(inode); 121 int minor_id = iminor(inode);
122 struct drm_minor *minor; 122 struct drm_minor *minor;
123 int retcode = 0; 123 int retcode = 0;
124 int need_setup = 0;
125 struct address_space *old_mapping;
124 126
125 minor = idr_find(&drm_minors_idr, minor_id); 127 minor = idr_find(&drm_minors_idr, minor_id);
126 if (!minor) 128 if (!minor)
@@ -132,23 +134,37 @@ int drm_open(struct inode *inode, struct file *filp)
132 if (drm_device_is_unplugged(dev)) 134 if (drm_device_is_unplugged(dev))
133 return -ENODEV; 135 return -ENODEV;
134 136
137 if (!dev->open_count++)
138 need_setup = 1;
139 mutex_lock(&dev->struct_mutex);
140 old_mapping = dev->dev_mapping;
141 if (old_mapping == NULL)
142 dev->dev_mapping = &inode->i_data;
143 /* ihold ensures nobody can remove inode with our i_data */
144 ihold(container_of(dev->dev_mapping, struct inode, i_data));
145 inode->i_mapping = dev->dev_mapping;
146 filp->f_mapping = dev->dev_mapping;
147 mutex_unlock(&dev->struct_mutex);
148
135 retcode = drm_open_helper(inode, filp, dev); 149 retcode = drm_open_helper(inode, filp, dev);
136 if (!retcode) { 150 if (retcode)
137 atomic_inc(&dev->counts[_DRM_STAT_OPENS]); 151 goto err_undo;
138 if (!dev->open_count++) 152 atomic_inc(&dev->counts[_DRM_STAT_OPENS]);
139 retcode = drm_setup(dev); 153 if (need_setup) {
140 } 154 retcode = drm_setup(dev);
141 if (!retcode) { 155 if (retcode)
142 mutex_lock(&dev->struct_mutex); 156 goto err_undo;
143 if (dev->dev_mapping == NULL)
144 dev->dev_mapping = &inode->i_data;
145 /* ihold ensures nobody can remove inode with our i_data */
146 ihold(container_of(dev->dev_mapping, struct inode, i_data));
147 inode->i_mapping = dev->dev_mapping;
148 filp->f_mapping = dev->dev_mapping;
149 mutex_unlock(&dev->struct_mutex);
150 } 157 }
158 return 0;
151 159
160err_undo:
161 mutex_lock(&dev->struct_mutex);
162 filp->f_mapping = old_mapping;
163 inode->i_mapping = old_mapping;
164 iput(container_of(dev->dev_mapping, struct inode, i_data));
165 dev->dev_mapping = old_mapping;
166 mutex_unlock(&dev->struct_mutex);
167 dev->open_count--;
152 return retcode; 168 return retcode;
153} 169}
154EXPORT_SYMBOL(drm_open); 170EXPORT_SYMBOL(drm_open);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_encoder.c b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
index d9afb11aac7..e5001dd85af 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_encoder.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
@@ -538,4 +538,14 @@ void exynos_drm_encoder_plane_disable(struct drm_encoder *encoder, void *data)
538 538
539 if (overlay_ops && overlay_ops->disable) 539 if (overlay_ops && overlay_ops->disable)
540 overlay_ops->disable(manager->dev, zpos); 540 overlay_ops->disable(manager->dev, zpos);
541
542 /*
543 * wait for vblank interrupt
544 * - this makes sure that hardware overlay is disabled to avoid
545 * for the dma accesses to memory after gem buffer was released
546 * because the setting for disabling the overlay will be updated
547 * at vsync.
548 */
549 if (overlay_ops && overlay_ops->wait_for_vblank)
550 overlay_ops->wait_for_vblank(manager->dev);
541} 551}
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 87e9b92039d..55ffba1f581 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -499,12 +499,8 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
499 499
500 edp = find_section(bdb, BDB_EDP); 500 edp = find_section(bdb, BDB_EDP);
501 if (!edp) { 501 if (!edp) {
502 if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp.support) { 502 if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp.support)
503 DRM_DEBUG_KMS("No eDP BDB found but eDP panel " 503 DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n");
504 "supported, assume %dbpp panel color "
505 "depth.\n",
506 dev_priv->edp.bpp);
507 }
508 return; 504 return;
509 } 505 }
510 506
@@ -657,9 +653,6 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
657 dev_priv->lvds_use_ssc = 1; 653 dev_priv->lvds_use_ssc = 1;
658 dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1); 654 dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
659 DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq); 655 DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);
660
661 /* eDP data */
662 dev_priv->edp.bpp = 18;
663} 656}
664 657
665static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id) 658static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 5c7774396e1..331af3bc689 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -143,7 +143,7 @@ static void intel_crt_dpms(struct drm_connector *connector, int mode)
143 int old_dpms; 143 int old_dpms;
144 144
145 /* PCH platforms and VLV only support on/off. */ 145 /* PCH platforms and VLV only support on/off. */
146 if (INTEL_INFO(dev)->gen < 5 && mode != DRM_MODE_DPMS_ON) 146 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
147 mode = DRM_MODE_DPMS_OFF; 147 mode = DRM_MODE_DPMS_OFF;
148 148
149 if (mode == connector->dpms) 149 if (mode == connector->dpms)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3f7f62d370c..de51489de23 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4150,6 +4150,17 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4150 } 4150 }
4151 } 4151 }
4152 4152
4153 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4154 /* Use VBT settings if we have an eDP panel */
4155 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4156
4157 if (edp_bpc && edp_bpc < display_bpc) {
4158 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4159 display_bpc = edp_bpc;
4160 }
4161 continue;
4162 }
4163
4153 /* 4164 /*
4154 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 4165 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4155 * through, clamp it down. (Note: >12bpc will be caught below.) 4166 * through, clamp it down. (Note: >12bpc will be caught below.)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 58c2f210154..9e619ada056 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2378,15 +2378,9 @@ int intel_enable_rc6(const struct drm_device *dev)
2378 if (i915_enable_rc6 >= 0) 2378 if (i915_enable_rc6 >= 0)
2379 return i915_enable_rc6; 2379 return i915_enable_rc6;
2380 2380
2381 if (INTEL_INFO(dev)->gen == 5) { 2381 /* Disable RC6 on Ironlake */
2382#ifdef CONFIG_INTEL_IOMMU 2382 if (INTEL_INFO(dev)->gen == 5)
2383 /* Disable rc6 on ilk if VT-d is on. */ 2383 return 0;
2384 if (intel_iommu_gfx_mapped)
2385 return false;
2386#endif
2387 DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
2388 return INTEL_RC6_ENABLE;
2389 }
2390 2384
2391 if (IS_HASWELL(dev)) { 2385 if (IS_HASWELL(dev)) {
2392 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); 2386 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index a4bee83df74..4b07401540e 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2244,7 +2244,6 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2244 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2244 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2245 intel_sdvo->is_hdmi = true; 2245 intel_sdvo->is_hdmi = true;
2246 } 2246 }
2247 intel_sdvo->base.cloneable = true;
2248 2247
2249 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2248 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2250 if (intel_sdvo->is_hdmi) 2249 if (intel_sdvo->is_hdmi)
@@ -2275,7 +2274,6 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2275 2274
2276 intel_sdvo->is_tv = true; 2275 intel_sdvo->is_tv = true;
2277 intel_sdvo->base.needs_tv_clock = true; 2276 intel_sdvo->base.needs_tv_clock = true;
2278 intel_sdvo->base.cloneable = false;
2279 2277
2280 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2278 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2281 2279
@@ -2318,8 +2316,6 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2318 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2316 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2319 } 2317 }
2320 2318
2321 intel_sdvo->base.cloneable = true;
2322
2323 intel_sdvo_connector_init(intel_sdvo_connector, 2319 intel_sdvo_connector_init(intel_sdvo_connector,
2324 intel_sdvo); 2320 intel_sdvo);
2325 return true; 2321 return true;
@@ -2350,9 +2346,6 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2350 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2346 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2351 } 2347 }
2352 2348
2353 /* SDVO LVDS is not cloneable because the input mode gets adjusted by the encoder */
2354 intel_sdvo->base.cloneable = false;
2355
2356 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2349 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
2357 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2350 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2358 goto err; 2351 goto err;
@@ -2425,6 +2418,18 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2425 return true; 2418 return true;
2426} 2419}
2427 2420
2421static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2422{
2423 struct drm_device *dev = intel_sdvo->base.base.dev;
2424 struct drm_connector *connector, *tmp;
2425
2426 list_for_each_entry_safe(connector, tmp,
2427 &dev->mode_config.connector_list, head) {
2428 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2429 intel_sdvo_destroy(connector);
2430 }
2431}
2432
2428static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2433static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2429 struct intel_sdvo_connector *intel_sdvo_connector, 2434 struct intel_sdvo_connector *intel_sdvo_connector,
2430 int type) 2435 int type)
@@ -2746,9 +2751,20 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2746 intel_sdvo->caps.output_flags) != true) { 2751 intel_sdvo->caps.output_flags) != true) {
2747 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 2752 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2748 SDVO_NAME(intel_sdvo)); 2753 SDVO_NAME(intel_sdvo));
2749 goto err; 2754 /* Output_setup can leave behind connectors! */
2755 goto err_output;
2750 } 2756 }
2751 2757
2758 /*
2759 * Cloning SDVO with anything is often impossible, since the SDVO
2760 * encoder can request a special input timing mode. And even if that's
2761 * not the case we have evidence that cloning a plain unscaled mode with
2762 * VGA doesn't really work. Furthermore the cloning flags are way too
2763 * simplistic anyway to express such constraints, so just give up on
2764 * cloning for SDVO encoders.
2765 */
2766 intel_sdvo->base.cloneable = false;
2767
2752 /* Only enable the hotplug irq if we need it, to work around noisy 2768 /* Only enable the hotplug irq if we need it, to work around noisy
2753 * hotplug lines. 2769 * hotplug lines.
2754 */ 2770 */
@@ -2759,12 +2775,12 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2759 2775
2760 /* Set the input timing to the screen. Assume always input 0. */ 2776 /* Set the input timing to the screen. Assume always input 0. */
2761 if (!intel_sdvo_set_target_input(intel_sdvo)) 2777 if (!intel_sdvo_set_target_input(intel_sdvo))
2762 goto err; 2778 goto err_output;
2763 2779
2764 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 2780 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2765 &intel_sdvo->pixel_clock_min, 2781 &intel_sdvo->pixel_clock_min,
2766 &intel_sdvo->pixel_clock_max)) 2782 &intel_sdvo->pixel_clock_max))
2767 goto err; 2783 goto err_output;
2768 2784
2769 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 2785 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2770 "clock range %dMHz - %dMHz, " 2786 "clock range %dMHz - %dMHz, "
@@ -2784,6 +2800,9 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2784 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 2800 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2785 return true; 2801 return true;
2786 2802
2803err_output:
2804 intel_sdvo_output_cleanup(intel_sdvo);
2805
2787err: 2806err:
2788 drm_encoder_cleanup(&intel_encoder->base); 2807 drm_encoder_cleanup(&intel_encoder->base);
2789 i2c_del_adapter(&intel_sdvo->ddc); 2808 i2c_del_adapter(&intel_sdvo->ddc);
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index c6f80055e98..0f09af13541 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -759,6 +759,7 @@ nv50_disp_intr_error(struct nv50_disp_priv *priv)
759static void 759static void
760nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) 760nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
761{ 761{
762 struct nouveau_bar *bar = nouveau_bar(priv);
762 struct nouveau_disp *disp = &priv->base; 763 struct nouveau_disp *disp = &priv->base;
763 struct nouveau_software_chan *chan, *temp; 764 struct nouveau_software_chan *chan, *temp;
764 unsigned long flags; 765 unsigned long flags;
@@ -768,19 +769,25 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
768 if (chan->vblank.crtc != crtc) 769 if (chan->vblank.crtc != crtc)
769 continue; 770 continue;
770 771
771 nv_wr32(priv, 0x001704, chan->vblank.channel); 772 if (nv_device(priv)->chipset >= 0xc0) {
772 nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); 773 nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
773 774 bar->flush(bar);
774 if (nv_device(priv)->chipset == 0x50) { 775 nv_wr32(priv, 0x06000c,
775 nv_wr32(priv, 0x001570, chan->vblank.offset); 776 upper_32_bits(chan->vblank.offset));
776 nv_wr32(priv, 0x001574, chan->vblank.value); 777 nv_wr32(priv, 0x060010,
778 lower_32_bits(chan->vblank.offset));
779 nv_wr32(priv, 0x060014, chan->vblank.value);
777 } else { 780 } else {
778 if (nv_device(priv)->chipset >= 0xc0) { 781 nv_wr32(priv, 0x001704, chan->vblank.channel);
779 nv_wr32(priv, 0x06000c, 782 nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
780 upper_32_bits(chan->vblank.offset)); 783 bar->flush(bar);
784 if (nv_device(priv)->chipset == 0x50) {
785 nv_wr32(priv, 0x001570, chan->vblank.offset);
786 nv_wr32(priv, 0x001574, chan->vblank.value);
787 } else {
788 nv_wr32(priv, 0x060010, chan->vblank.offset);
789 nv_wr32(priv, 0x060014, chan->vblank.value);
781 } 790 }
782 nv_wr32(priv, 0x060010, chan->vblank.offset);
783 nv_wr32(priv, 0x060014, chan->vblank.value);
784 } 791 }
785 792
786 list_del(&chan->vblank.head); 793 list_del(&chan->vblank.head);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
index e45035efb8c..7bbb1e1b7a8 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
@@ -669,21 +669,27 @@ nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
669 }); 669 });
670} 670}
671 671
672void 672int
673nv40_grctx_init(struct nouveau_device *device, u32 *size) 673nv40_grctx_init(struct nouveau_device *device, u32 *size)
674{ 674{
675 u32 ctxprog[256], i; 675 u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
676 struct nouveau_grctx ctx = { 676 struct nouveau_grctx ctx = {
677 .device = device, 677 .device = device,
678 .mode = NOUVEAU_GRCTX_PROG, 678 .mode = NOUVEAU_GRCTX_PROG,
679 .data = ctxprog, 679 .data = ctxprog,
680 .ctxprog_max = ARRAY_SIZE(ctxprog) 680 .ctxprog_max = 256,
681 }; 681 };
682 682
683 if (!ctxprog)
684 return -ENOMEM;
685
683 nv40_grctx_generate(&ctx); 686 nv40_grctx_generate(&ctx);
684 687
685 nv_wr32(device, 0x400324, 0); 688 nv_wr32(device, 0x400324, 0);
686 for (i = 0; i < ctx.ctxprog_len; i++) 689 for (i = 0; i < ctx.ctxprog_len; i++)
687 nv_wr32(device, 0x400328, ctxprog[i]); 690 nv_wr32(device, 0x400328, ctxprog[i]);
688 *size = ctx.ctxvals_pos * 4; 691 *size = ctx.ctxvals_pos * 4;
692
693 kfree(ctxprog);
694 return 0;
689} 695}
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
index 8fc1221408b..0b36dd3deeb 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
@@ -156,8 +156,8 @@ nv40_graph_context_ctor(struct nouveau_object *parent,
156static int 156static int
157nv40_graph_context_fini(struct nouveau_object *object, bool suspend) 157nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
158{ 158{
159 struct nv04_graph_priv *priv = (void *)object->engine; 159 struct nv40_graph_priv *priv = (void *)object->engine;
160 struct nv04_graph_chan *chan = (void *)object; 160 struct nv40_graph_chan *chan = (void *)object;
161 u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; 161 u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
162 int ret = 0; 162 int ret = 0;
163 163
@@ -374,7 +374,9 @@ nv40_graph_init(struct nouveau_object *object)
374 return ret; 374 return ret;
375 375
376 /* generate and upload context program */ 376 /* generate and upload context program */
377 nv40_grctx_init(nv_device(priv), &priv->size); 377 ret = nv40_grctx_init(nv_device(priv), &priv->size);
378 if (ret)
379 return ret;
378 380
379 /* No context present currently */ 381 /* No context present currently */
380 nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); 382 nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
index d2ac975afc2..7da35a4e797 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
@@ -15,7 +15,7 @@ nv44_graph_class(void *priv)
15 return !(0x0baf & (1 << (device->chipset & 0x0f))); 15 return !(0x0baf & (1 << (device->chipset & 0x0f)));
16} 16}
17 17
18void nv40_grctx_init(struct nouveau_device *, u32 *size); 18int nv40_grctx_init(struct nouveau_device *, u32 *size);
19void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); 19void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
20 20
21#endif 21#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
index 12418574efe..f7c581ad199 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
@@ -38,7 +38,7 @@ struct nv40_mpeg_priv {
38}; 38};
39 39
40struct nv40_mpeg_chan { 40struct nv40_mpeg_chan {
41 struct nouveau_mpeg base; 41 struct nouveau_mpeg_chan base;
42}; 42};
43 43
44/******************************************************************************* 44/*******************************************************************************
diff --git a/drivers/gpu/drm/nouveau/core/include/core/object.h b/drivers/gpu/drm/nouveau/core/include/core/object.h
index 27d17a9852e..5982935ee23 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/object.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/object.h
@@ -182,14 +182,18 @@ nv_mo32(void *obj, u64 addr, u32 mask, u32 data)
182 return temp; 182 return temp;
183} 183}
184 184
185static inline bool 185static inline int
186nv_strncmp(void *obj, u32 addr, u32 len, const char *str) 186nv_memcmp(void *obj, u32 addr, const char *str, u32 len)
187{ 187{
188 unsigned char c1, c2;
189
188 while (len--) { 190 while (len--) {
189 if (nv_ro08(obj, addr++) != *(str++)) 191 c1 = nv_ro08(obj, addr++);
190 return false; 192 c2 = *(str++);
193 if (c1 != c2)
194 return c1 - c2;
191 } 195 }
192 return true; 196 return 0;
193} 197}
194 198
195#endif 199#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
index 39e73b91d36..41b7a6a76f1 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
@@ -54,6 +54,7 @@ int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
54 int clk, struct nouveau_pll_vals *); 54 int clk, struct nouveau_pll_vals *);
55int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, 55int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
56 struct nouveau_pll_vals *); 56 struct nouveau_pll_vals *);
57 57int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
58 int clk, struct nouveau_pll_vals *);
58 59
59#endif 60#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
index bbd709fba0a..0fd87df99dd 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
@@ -64,7 +64,7 @@ dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
64 } 64 }
65 } else 65 } else
66 if (*ver >= 0x15) { 66 if (*ver >= 0x15) {
67 if (!nv_strncmp(bios, dcb - 7, 7, "DEV_REC")) { 67 if (!nv_memcmp(bios, dcb - 7, "DEV_REC", 7)) {
68 u16 i2c = nv_ro16(bios, dcb + 2); 68 u16 i2c = nv_ro16(bios, dcb + 2);
69 *hdr = 4; 69 *hdr = 4;
70 *cnt = (i2c - dcb) / 10; 70 *cnt = (i2c - dcb) / 10;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
index cc8d7d162d7..9068c98b96f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
@@ -66,6 +66,24 @@ nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
66 return ret; 66 return ret;
67} 67}
68 68
69int
70nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
71 int clk, struct nouveau_pll_vals *pv)
72{
73 int ret, N, M, P;
74
75 ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P);
76
77 if (ret > 0) {
78 pv->refclk = info->refclk;
79 pv->N1 = N;
80 pv->M1 = M;
81 pv->log2P = P;
82 }
83 return ret;
84}
85
86
69static int 87static int
70nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 88nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
71 struct nouveau_oclass *oclass, void *data, u32 size, 89 struct nouveau_oclass *oclass, void *data, u32 size,
@@ -80,6 +98,7 @@ nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
80 return ret; 98 return ret;
81 99
82 priv->base.pll_set = nva3_clock_pll_set; 100 priv->base.pll_set = nva3_clock_pll_set;
101 priv->base.pll_calc = nva3_clock_pll_calc;
83 return 0; 102 return 0;
84} 103}
85 104
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
index 5ccce0b17bf..f6962c9b6c3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
@@ -79,6 +79,7 @@ nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
79 return ret; 79 return ret;
80 80
81 priv->base.pll_set = nvc0_clock_pll_set; 81 priv->base.pll_set = nvc0_clock_pll_set;
82 priv->base.pll_calc = nva3_clock_pll_calc;
82 return 0; 83 return 0;
83} 84}
84 85
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
index 49050d991e7..9474cfca6e4 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
@@ -67,7 +67,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
67static void 67static void
68nv41_vm_flush(struct nouveau_vm *vm) 68nv41_vm_flush(struct nouveau_vm *vm)
69{ 69{
70 struct nv04_vm_priv *priv = (void *)vm->vmm; 70 struct nv04_vmmgr_priv *priv = (void *)vm->vmm;
71 71
72 mutex_lock(&nv_subdev(priv)->mutex); 72 mutex_lock(&nv_subdev(priv)->mutex);
73 nv_wr32(priv, 0x100810, 0x00000022); 73 nv_wr32(priv, 0x100810, 0x00000022);
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index d48c02a3652..41241922263 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -241,6 +241,10 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
241 241
242 if (unlikely(!abi16)) 242 if (unlikely(!abi16))
243 return -ENOMEM; 243 return -ENOMEM;
244
245 if (!drm->channel)
246 return nouveau_abi16_put(abi16, -ENODEV);
247
244 client = nv_client(abi16->client); 248 client = nv_client(abi16->client);
245 device = nv_device(abi16->device); 249 device = nv_device(abi16->device);
246 imem = nouveau_instmem(device); 250 imem = nouveau_instmem(device);
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 29a913460fe..ac340ba3201 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -354,7 +354,7 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force)
354 * valid - it's not (rh#613284) 354 * valid - it's not (rh#613284)
355 */ 355 */
356 if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) { 356 if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) {
357 if (!(nv_connector->edid = nouveau_acpi_edid(dev, connector))) { 357 if ((nv_connector->edid = nouveau_acpi_edid(dev, connector))) {
358 status = connector_status_connected; 358 status = connector_status_connected;
359 goto out; 359 goto out;
360 } 360 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index a7529b37238..01c403ddb99 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -127,7 +127,8 @@ nouveau_accel_init(struct nouveau_drm *drm)
127 127
128 /* initialise synchronisation routines */ 128 /* initialise synchronisation routines */
129 if (device->card_type < NV_10) ret = nv04_fence_create(drm); 129 if (device->card_type < NV_10) ret = nv04_fence_create(drm);
130 else if (device->chipset < 0x84) ret = nv10_fence_create(drm); 130 else if (device->card_type < NV_50) ret = nv10_fence_create(drm);
131 else if (device->chipset < 0x84) ret = nv50_fence_create(drm);
131 else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); 132 else if (device->card_type < NV_C0) ret = nv84_fence_create(drm);
132 else ret = nvc0_fence_create(drm); 133 else ret = nvc0_fence_create(drm);
133 if (ret) { 134 if (ret) {
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 2e566e123e9..9175615bbd8 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -561,6 +561,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
561 /* use frac fb div on APUs */ 561 /* use frac fb div on APUs */
562 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 562 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
563 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 563 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
564 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
565 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
564 } else { 566 } else {
565 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 567 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
566 568
@@ -1697,34 +1699,22 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1697 DRM_ERROR("unable to allocate a PPLL\n"); 1699 DRM_ERROR("unable to allocate a PPLL\n");
1698 return ATOM_PPLL_INVALID; 1700 return ATOM_PPLL_INVALID;
1699 } else { 1701 } else {
1700 if (ASIC_IS_AVIVO(rdev)) { 1702 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1701 /* in DP mode, the DP ref clock can come from either PPLL 1703 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1702 * depending on the asic: 1704 * the matching btw pll and crtc is done through
1703 * DCE3: PPLL1 or PPLL2 1705 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1704 */ 1706 * pll (1 or 2) to select which register to write. ie if using
1705 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1707 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1706 /* use the same PPLL for all DP monitors */ 1708 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1707 pll = radeon_get_shared_dp_ppll(crtc); 1709 * choose which value to write. Which is reverse order from
1708 if (pll != ATOM_PPLL_INVALID) 1710 * register logic. So only case that works is when pllid is
1709 return pll; 1711 * same as crtcid or when both pll and crtc are enabled and
1710 } else { 1712 * both use same clock.
1711 /* use the same PPLL for all monitors with the same clock */ 1713 *
1712 pll = radeon_get_shared_nondp_ppll(crtc); 1714 * So just return crtc id as if crtc and pll were hard linked
1713 if (pll != ATOM_PPLL_INVALID) 1715 * together even if they aren't
1714 return pll; 1716 */
1715 } 1717 return radeon_crtc->crtc_id;
1716 /* all other cases */
1717 pll_in_use = radeon_get_pll_use_mask(crtc);
1718 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1719 return ATOM_PPLL1;
1720 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1721 return ATOM_PPLL2;
1722 DRM_ERROR("unable to allocate a PPLL\n");
1723 return ATOM_PPLL_INVALID;
1724 } else {
1725 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1726 return radeon_crtc->crtc_id;
1727 }
1728 } 1718 }
1729} 1719}
1730 1720
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index ba498f8e47a..4552d4aff31 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -340,7 +340,7 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
340 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 340 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
341 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 341 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
342 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 342 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
343 radeon_dp_set_link_config(connector, mode); 343 radeon_dp_set_link_config(connector, adjusted_mode);
344 } 344 }
345 345
346 return true; 346 return true;
@@ -1625,7 +1625,7 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1625 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1625 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1626 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1626 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1627 /* some early dce3.2 boards have a bug in their transmitter control table */ 1627 /* some early dce3.2 boards have a bug in their transmitter control table */
1628 if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730)) 1628 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
1629 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1629 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1630 } 1630 }
1631 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1631 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 14313ad43b7..78de2e4097b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1330,6 +1330,8 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
1330 break; 1330 break;
1331 udelay(1); 1331 udelay(1);
1332 } 1332 }
1333 } else {
1334 save->crtc_enabled[i] = false;
1333 } 1335 }
1334 } 1336 }
1335 1337
@@ -1372,7 +1374,7 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1372 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 1374 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1373 1375
1374 for (i = 0; i < rdev->num_crtc; i++) { 1376 for (i = 0; i < rdev->num_crtc; i++) {
1375 if (save->crtc_enabled) { 1377 if (save->crtc_enabled[i]) {
1376 if (ASIC_IS_DCE6(rdev)) { 1378 if (ASIC_IS_DCE6(rdev)) {
1377 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); 1379 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1378 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; 1380 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
@@ -3091,6 +3093,16 @@ restart_ih:
3091 break; 3093 break;
3092 } 3094 }
3093 break; 3095 break;
3096 case 146:
3097 case 147:
3098 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3099 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3100 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3101 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3102 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3103 /* reset addr and status */
3104 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3105 break;
3094 case 176: /* CP_INT in ring buffer */ 3106 case 176: /* CP_INT in ring buffer */
3095 case 177: /* CP_INT in IB1 */ 3107 case 177: /* CP_INT in IB1 */
3096 case 178: /* CP_INT in IB2 */ 3108 case 178: /* CP_INT in IB2 */
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 95e6318b626..c042e497e45 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -2725,6 +2725,9 @@ static bool evergreen_vm_reg_valid(u32 reg)
2725 /* check config regs */ 2725 /* check config regs */
2726 switch (reg) { 2726 switch (reg) {
2727 case GRBM_GFX_INDEX: 2727 case GRBM_GFX_INDEX:
2728 case CP_STRMOUT_CNTL:
2729 case CP_COHER_CNTL:
2730 case CP_COHER_SIZE:
2728 case VGT_VTX_VECT_EJECT_REG: 2731 case VGT_VTX_VECT_EJECT_REG:
2729 case VGT_CACHE_INVALIDATION: 2732 case VGT_CACHE_INVALIDATION:
2730 case VGT_GS_VERTEX_REUSE: 2733 case VGT_GS_VERTEX_REUSE:
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index df542f1a5df..cae7ab4219e 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -91,6 +91,10 @@
91#define FB_READ_EN (1 << 0) 91#define FB_READ_EN (1 << 0)
92#define FB_WRITE_EN (1 << 1) 92#define FB_WRITE_EN (1 << 1)
93 93
94#define CP_STRMOUT_CNTL 0x84FC
95
96#define CP_COHER_CNTL 0x85F0
97#define CP_COHER_SIZE 0x85F4
94#define CP_COHER_BASE 0x85F8 98#define CP_COHER_BASE 0x85F8
95#define CP_STALLED_STAT1 0x8674 99#define CP_STALLED_STAT1 0x8674
96#define CP_STALLED_STAT2 0x8678 100#define CP_STALLED_STAT2 0x8678
@@ -351,6 +355,54 @@
351# define AFMT_MPEG_INFO_UPDATE (1 << 10) 355# define AFMT_MPEG_INFO_UPDATE (1 << 10)
352#define AFMT_GENERIC0_7 0x7138 356#define AFMT_GENERIC0_7 0x7138
353 357
358/* DCE4/5 ELD audio interface */
359#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */
360#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */
361#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */
362#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */
363#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */
364#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */
365#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */
366#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */
367#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */
368#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */
369#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */
370#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */
371#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */
372#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */
373# define MAX_CHANNELS(x) (((x) & 0x7) << 0)
374/* max channels minus one. 7 = 8 channels */
375# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
376# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
377# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
378/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
379 * bit0 = 32 kHz
380 * bit1 = 44.1 kHz
381 * bit2 = 48 kHz
382 * bit3 = 88.2 kHz
383 * bit4 = 96 kHz
384 * bit5 = 176.4 kHz
385 * bit6 = 192 kHz
386 */
387
388#define AZ_HOT_PLUG_CONTROL 0x5e78
389# define AZ_FORCE_CODEC_WAKE (1 << 0)
390# define PIN0_JACK_DETECTION_ENABLE (1 << 4)
391# define PIN1_JACK_DETECTION_ENABLE (1 << 5)
392# define PIN2_JACK_DETECTION_ENABLE (1 << 6)
393# define PIN3_JACK_DETECTION_ENABLE (1 << 7)
394# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)
395# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)
396# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)
397# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)
398# define CODEC_HOT_PLUG_ENABLE (1 << 12)
399# define PIN0_AUDIO_ENABLED (1 << 24)
400# define PIN1_AUDIO_ENABLED (1 << 25)
401# define PIN2_AUDIO_ENABLED (1 << 26)
402# define PIN3_AUDIO_ENABLED (1 << 27)
403# define AUDIO_ENABLED (1 << 31)
404
405
354#define GC_USER_SHADER_PIPE_CONFIG 0x8954 406#define GC_USER_SHADER_PIPE_CONFIG 0x8954
355#define INACTIVE_QD_PIPES(x) ((x) << 8) 407#define INACTIVE_QD_PIPES(x) ((x) << 8)
356#define INACTIVE_QD_PIPES_MASK 0x0000FF00 408#define INACTIVE_QD_PIPES_MASK 0x0000FF00
@@ -647,6 +699,7 @@
647#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 699#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
648#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 700#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
649#define VM_CONTEXT1_CNTL 0x1414 701#define VM_CONTEXT1_CNTL 0x1414
702#define VM_CONTEXT1_CNTL2 0x1434
650#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 703#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
651#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 704#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
652#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 705#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
@@ -668,6 +721,8 @@
668#define CACHE_UPDATE_MODE(x) ((x) << 6) 721#define CACHE_UPDATE_MODE(x) ((x) << 6)
669#define VM_L2_STATUS 0x140C 722#define VM_L2_STATUS 0x140C
670#define L2_BUSY (1 << 0) 723#define L2_BUSY (1 << 0)
724#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
725#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
671 726
672#define WAIT_UNTIL 0x8040 727#define WAIT_UNTIL 0x8040
673 728
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 81e6a568c29..30c18a6e004 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -784,10 +784,20 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
784 /* enable context1-7 */ 784 /* enable context1-7 */
785 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 785 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
786 (u32)(rdev->dummy_page.addr >> 12)); 786 (u32)(rdev->dummy_page.addr >> 12));
787 WREG32(VM_CONTEXT1_CNTL2, 0); 787 WREG32(VM_CONTEXT1_CNTL2, 4);
788 WREG32(VM_CONTEXT1_CNTL, 0);
789 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 788 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
790 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 789 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
790 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
791 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
792 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
793 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
794 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
795 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
796 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
797 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
798 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
799 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
800 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
791 801
792 cayman_pcie_gart_tlb_flush(rdev); 802 cayman_pcie_gart_tlb_flush(rdev);
793 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 803 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index cbef6815907..f5e54a7e2bf 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -80,7 +80,18 @@
80#define VM_CONTEXT0_CNTL 0x1410 80#define VM_CONTEXT0_CNTL 0x1410
81#define ENABLE_CONTEXT (1 << 0) 81#define ENABLE_CONTEXT (1 << 0)
82#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 82#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
83#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
83#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 84#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
85#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
86#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
87#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
88#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
89#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
90#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
91#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
92#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
93#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
94#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
84#define VM_CONTEXT1_CNTL 0x1414 95#define VM_CONTEXT1_CNTL 0x1414
85#define VM_CONTEXT0_CNTL2 0x1430 96#define VM_CONTEXT0_CNTL2 0x1430
86#define VM_CONTEXT1_CNTL2 0x1434 97#define VM_CONTEXT1_CNTL2 0x1434
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index 10ea17a6b2a..42433344cb1 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -69,9 +69,12 @@ static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
69 /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/ 69 /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/
70 { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59, 70 { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59,
71 PCI_VENDOR_ID_DELL, 0x00e3, 2}, 71 PCI_VENDOR_ID_DELL, 0x00e3, 2},
72 /* Intel 82852/82855 host bridge / Mobility FireGL 9000 R250 Needs AGPMode 1 (lp #296617) */ 72 /* Intel 82852/82855 host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 (lp #296617) */
73 { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66, 73 { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66,
74 PCI_VENDOR_ID_DELL, 0x0149, 1}, 74 PCI_VENDOR_ID_DELL, 0x0149, 1},
75 /* Intel 82855PM host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 for suspend/resume */
76 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66,
77 PCI_VENDOR_ID_IBM, 0x0531, 1},
75 /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */ 78 /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */
76 { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, 79 { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
77 0x1025, 0x0061, 1}, 80 0x1025, 0x0061, 1},
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 8c1a83c6eb0..91b64278c4f 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -65,9 +65,10 @@
65 * 2.22.0 - r600 only: RESOLVE_BOX allowed 65 * 2.22.0 - r600 only: RESOLVE_BOX allowed
66 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 66 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
67 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 67 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
68 * 2.25.0 - eg+: new info request for num SE and num SH
68 */ 69 */
69#define KMS_DRIVER_MAJOR 2 70#define KMS_DRIVER_MAJOR 2
70#define KMS_DRIVER_MINOR 24 71#define KMS_DRIVER_MINOR 25
71#define KMS_DRIVER_PATCHLEVEL 0 72#define KMS_DRIVER_PATCHLEVEL 0
72int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 73int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
73int radeon_driver_unload_kms(struct drm_device *dev); 74int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index dc781c49b96..9c312f9afb6 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -361,6 +361,22 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
361 return -EINVAL; 361 return -EINVAL;
362 } 362 }
363 break; 363 break;
364 case RADEON_INFO_MAX_SE:
365 if (rdev->family >= CHIP_TAHITI)
366 value = rdev->config.si.max_shader_engines;
367 else if (rdev->family >= CHIP_CAYMAN)
368 value = rdev->config.cayman.max_shader_engines;
369 else if (rdev->family >= CHIP_CEDAR)
370 value = rdev->config.evergreen.num_ses;
371 else
372 value = 1;
373 break;
374 case RADEON_INFO_MAX_SH_PER_SE:
375 if (rdev->family >= CHIP_TAHITI)
376 value = rdev->config.si.max_sh_per_se;
377 else
378 return -EINVAL;
379 break;
364 default: 380 default:
365 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 381 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
366 return -EINVAL; 382 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 7c4b4bb05a3..fe6fe2527b9 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -88,10 +88,20 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
88 if (domain & RADEON_GEM_DOMAIN_VRAM) 88 if (domain & RADEON_GEM_DOMAIN_VRAM)
89 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 89 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
90 TTM_PL_FLAG_VRAM; 90 TTM_PL_FLAG_VRAM;
91 if (domain & RADEON_GEM_DOMAIN_GTT) 91 if (domain & RADEON_GEM_DOMAIN_GTT) {
92 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 92 if (rbo->rdev->flags & RADEON_IS_AGP) {
93 if (domain & RADEON_GEM_DOMAIN_CPU) 93 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
94 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 94 } else {
95 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
96 }
97 }
98 if (domain & RADEON_GEM_DOMAIN_CPU) {
99 if (rbo->rdev->flags & RADEON_IS_AGP) {
100 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
101 } else {
102 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
103 }
104 }
95 if (!c) 105 if (!c)
96 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 106 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
97 rbo->placement.num_placement = c; 107 rbo->placement.num_placement = c;
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index b0adfc595d7..e2d9dc8e751 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -551,6 +551,54 @@
551#define HDMI_OFFSET0 (0x7400 - 0x7400) 551#define HDMI_OFFSET0 (0x7400 - 0x7400)
552#define HDMI_OFFSET1 (0x7800 - 0x7400) 552#define HDMI_OFFSET1 (0x7800 - 0x7400)
553 553
554/* DCE3.2 ELD audio interface */
555#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */
556#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */
557#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */
558#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */
559#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */
560#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */
561#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */
562#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */
563#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */
564#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */
565#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */
566#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */
567#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */
568#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */
569# define MAX_CHANNELS(x) (((x) & 0x7) << 0)
570/* max channels minus one. 7 = 8 channels */
571# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
572# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
573# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
574/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
575 * bit0 = 32 kHz
576 * bit1 = 44.1 kHz
577 * bit2 = 48 kHz
578 * bit3 = 88.2 kHz
579 * bit4 = 96 kHz
580 * bit5 = 176.4 kHz
581 * bit6 = 192 kHz
582 */
583
584#define AZ_HOT_PLUG_CONTROL 0x7300
585# define AZ_FORCE_CODEC_WAKE (1 << 0)
586# define PIN0_JACK_DETECTION_ENABLE (1 << 4)
587# define PIN1_JACK_DETECTION_ENABLE (1 << 5)
588# define PIN2_JACK_DETECTION_ENABLE (1 << 6)
589# define PIN3_JACK_DETECTION_ENABLE (1 << 7)
590# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)
591# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)
592# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)
593# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)
594# define CODEC_HOT_PLUG_ENABLE (1 << 12)
595# define PIN0_AUDIO_ENABLED (1 << 24)
596# define PIN1_AUDIO_ENABLED (1 << 25)
597# define PIN2_AUDIO_ENABLED (1 << 26)
598# define PIN3_AUDIO_ENABLED (1 << 27)
599# define AUDIO_ENABLED (1 << 31)
600
601
554#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 602#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
555#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 603#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
556#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 604#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index b0db712060f..c4d9eb623ce 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2426,9 +2426,20 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
2426 /* enable context1-15 */ 2426 /* enable context1-15 */
2427 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 2427 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2428 (u32)(rdev->dummy_page.addr >> 12)); 2428 (u32)(rdev->dummy_page.addr >> 12));
2429 WREG32(VM_CONTEXT1_CNTL2, 0); 2429 WREG32(VM_CONTEXT1_CNTL2, 4);
2430 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 2430 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
2431 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 2431 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2432 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2433 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2434 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2435 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
2436 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
2437 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
2438 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
2439 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
2440 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
2441 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2442 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
2432 2443
2433 si_pcie_gart_tlb_flush(rdev); 2444 si_pcie_gart_tlb_flush(rdev);
2434 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 2445 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
@@ -2474,6 +2485,7 @@ static bool si_vm_reg_valid(u32 reg)
2474 /* check config regs */ 2485 /* check config regs */
2475 switch (reg) { 2486 switch (reg) {
2476 case GRBM_GFX_INDEX: 2487 case GRBM_GFX_INDEX:
2488 case CP_STRMOUT_CNTL:
2477 case VGT_VTX_VECT_EJECT_REG: 2489 case VGT_VTX_VECT_EJECT_REG:
2478 case VGT_CACHE_INVALIDATION: 2490 case VGT_CACHE_INVALIDATION:
2479 case VGT_ESGS_RING_SIZE: 2491 case VGT_ESGS_RING_SIZE:
@@ -3683,6 +3695,16 @@ restart_ih:
3683 break; 3695 break;
3684 } 3696 }
3685 break; 3697 break;
3698 case 146:
3699 case 147:
3700 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3701 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3702 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3703 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3704 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3705 /* reset addr and status */
3706 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3707 break;
3686 case 176: /* RINGID0 CP_INT */ 3708 case 176: /* RINGID0 CP_INT */
3687 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3709 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3688 break; 3710 break;
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 7d2a20e5657..53b4d4535fd 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -91,7 +91,18 @@
91#define VM_CONTEXT0_CNTL 0x1410 91#define VM_CONTEXT0_CNTL 0x1410
92#define ENABLE_CONTEXT (1 << 0) 92#define ENABLE_CONTEXT (1 << 0)
93#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 93#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
94#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
94#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 95#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
96#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
97#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
98#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
99#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
100#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
101#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
102#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
103#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
104#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
105#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
95#define VM_CONTEXT1_CNTL 0x1414 106#define VM_CONTEXT1_CNTL 0x1414
96#define VM_CONTEXT0_CNTL2 0x1430 107#define VM_CONTEXT0_CNTL2 0x1430
97#define VM_CONTEXT1_CNTL2 0x1434 108#define VM_CONTEXT1_CNTL2 0x1434
@@ -104,6 +115,9 @@
104#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 115#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
105#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 116#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
106 117
118#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
119#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
120
107#define VM_INVALIDATE_REQUEST 0x1478 121#define VM_INVALIDATE_REQUEST 0x1478
108#define VM_INVALIDATE_RESPONSE 0x147c 122#define VM_INVALIDATE_RESPONSE 0x147c
109 123
@@ -424,6 +438,7 @@
424# define RDERR_INT_ENABLE (1 << 0) 438# define RDERR_INT_ENABLE (1 << 0)
425# define GUI_IDLE_INT_ENABLE (1 << 19) 439# define GUI_IDLE_INT_ENABLE (1 << 19)
426 440
441#define CP_STRMOUT_CNTL 0x84FC
427#define SCRATCH_REG0 0x8500 442#define SCRATCH_REG0 0x8500
428#define SCRATCH_REG1 0x8504 443#define SCRATCH_REG1 0x8504
429#define SCRATCH_REG2 0x8508 444#define SCRATCH_REG2 0x8508
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 860dc4813e9..bd2a3b40cd1 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -749,7 +749,10 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags,
749 /* clear the pages coming from the pool if requested */ 749 /* clear the pages coming from the pool if requested */
750 if (flags & TTM_PAGE_FLAG_ZERO_ALLOC) { 750 if (flags & TTM_PAGE_FLAG_ZERO_ALLOC) {
751 list_for_each_entry(p, &plist, lru) { 751 list_for_each_entry(p, &plist, lru) {
752 clear_page(page_address(p)); 752 if (PageHighMem(p))
753 clear_highpage(p);
754 else
755 clear_page(page_address(p));
753 } 756 }
754 } 757 }
755 758
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index bf8260133ea..7d759a43029 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -308,9 +308,7 @@ int ttm_tt_swapin(struct ttm_tt *ttm)
308 if (unlikely(to_page == NULL)) 308 if (unlikely(to_page == NULL))
309 goto out_err; 309 goto out_err;
310 310
311 preempt_disable();
312 copy_highpage(to_page, from_page); 311 copy_highpage(to_page, from_page);
313 preempt_enable();
314 page_cache_release(from_page); 312 page_cache_release(from_page);
315 } 313 }
316 314
@@ -358,9 +356,7 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage)
358 ret = PTR_ERR(to_page); 356 ret = PTR_ERR(to_page);
359 goto out_err; 357 goto out_err;
360 } 358 }
361 preempt_disable();
362 copy_highpage(to_page, from_page); 359 copy_highpage(to_page, from_page);
363 preempt_enable();
364 set_page_dirty(to_page); 360 set_page_dirty(to_page);
365 mark_page_accessed(to_page); 361 mark_page_accessed(to_page);
366 page_cache_release(to_page); 362 page_cache_release(to_page);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c
index 655d57f188d..e88b0eb1a17 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c
@@ -305,7 +305,7 @@ void vmw_bo_pin(struct ttm_buffer_object *bo, bool pin)
305 305
306 BUG_ON(!ttm_bo_is_reserved(bo)); 306 BUG_ON(!ttm_bo_is_reserved(bo));
307 BUG_ON(old_mem_type != TTM_PL_VRAM && 307 BUG_ON(old_mem_type != TTM_PL_VRAM &&
308 old_mem_type != VMW_PL_FLAG_GMR); 308 old_mem_type != VMW_PL_GMR);
309 309
310 pl_flags = TTM_PL_FLAG_VRAM | VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED; 310 pl_flags = TTM_PL_FLAG_VRAM | VMW_PL_FLAG_GMR | TTM_PL_FLAG_CACHED;
311 if (pin) 311 if (pin)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 91581fd5004..161f8b2549a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -1092,6 +1092,11 @@ static void vmw_pm_complete(struct device *kdev)
1092 struct drm_device *dev = pci_get_drvdata(pdev); 1092 struct drm_device *dev = pci_get_drvdata(pdev);
1093 struct vmw_private *dev_priv = vmw_priv(dev); 1093 struct vmw_private *dev_priv = vmw_priv(dev);
1094 1094
1095 mutex_lock(&dev_priv->hw_mutex);
1096 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1097 (void) vmw_read(dev_priv, SVGA_REG_ID);
1098 mutex_unlock(&dev_priv->hw_mutex);
1099
1095 /** 1100 /**
1096 * Reclaim 3d reference held by fbdev and potentially 1101 * Reclaim 3d reference held by fbdev and potentially
1097 * start fifo. 1102 * start fifo.
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index 2f7c08ebf56..d9fbbe19107 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -110,6 +110,8 @@ int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data,
110 memcpy_fromio(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size); 110 memcpy_fromio(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size);
111 111
112 ret = copy_to_user(buffer, bounce, size); 112 ret = copy_to_user(buffer, bounce, size);
113 if (ret)
114 ret = -EFAULT;
113 vfree(bounce); 115 vfree(bounce);
114 116
115 if (unlikely(ret != 0)) 117 if (unlikely(ret != 0))
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 21:12:12 -0500