diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-09-10 14:10:00 -0400 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-10 18:13:48 -0400 |
commit | 0e23b99d2599112a332136728e9250e688a08b0c (patch) | |
tree | 48ebd021ab04f8781753d176bce00f457d1b52ed /drivers/gpu | |
parent | c98e9dcf9023e72837c1c01251f370e2358a0de6 (diff) |
drm/i915: split Ironlake FDI enable function
Easier to read, and will pair up with a disable function.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 72 |
1 files changed, 45 insertions, 27 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ff549199c70..086df969de4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1848,47 +1848,21 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc) | |||
1848 | DRM_DEBUG_KMS("FDI train done.\n"); | 1848 | DRM_DEBUG_KMS("FDI train done.\n"); |
1849 | } | 1849 | } |
1850 | 1850 | ||
1851 | static void ironlake_crtc_enable(struct drm_crtc *crtc) | 1851 | static void ironlake_fdi_enable(struct drm_crtc *crtc) |
1852 | { | 1852 | { |
1853 | struct drm_device *dev = crtc->dev; | 1853 | struct drm_device *dev = crtc->dev; |
1854 | struct drm_i915_private *dev_priv = dev->dev_private; | 1854 | struct drm_i915_private *dev_priv = dev->dev_private; |
1855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | 1855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1856 | int pipe = intel_crtc->pipe; | 1856 | int pipe = intel_crtc->pipe; |
1857 | int plane = intel_crtc->plane; | ||
1858 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; | ||
1859 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | 1857 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
1860 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; | ||
1861 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; | ||
1862 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; | 1858 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; |
1863 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | 1859 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; |
1864 | int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; | ||
1865 | int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | ||
1866 | int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | ||
1867 | int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | ||
1868 | int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | ||
1869 | int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | ||
1870 | int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | ||
1871 | int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B; | ||
1872 | int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B; | ||
1873 | int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B; | ||
1874 | int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; | ||
1875 | int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; | ||
1876 | int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; | ||
1877 | int trans_dpll_sel = (pipe == 0) ? 0 : 1; | ||
1878 | u32 temp; | 1860 | u32 temp; |
1879 | u32 pipe_bpc; | 1861 | u32 pipe_bpc; |
1880 | 1862 | ||
1881 | temp = I915_READ(pipeconf_reg); | 1863 | temp = I915_READ(pipeconf_reg); |
1882 | pipe_bpc = temp & PIPE_BPC_MASK; | 1864 | pipe_bpc = temp & PIPE_BPC_MASK; |
1883 | 1865 | ||
1884 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | ||
1885 | temp = I915_READ(PCH_LVDS); | ||
1886 | if ((temp & LVDS_PORT_EN) == 0) { | ||
1887 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | ||
1888 | POSTING_READ(PCH_LVDS); | ||
1889 | } | ||
1890 | } | ||
1891 | |||
1892 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ | 1866 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
1893 | temp = I915_READ(fdi_rx_reg); | 1867 | temp = I915_READ(fdi_rx_reg); |
1894 | /* | 1868 | /* |
@@ -1916,6 +1890,50 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) | |||
1916 | I915_READ(fdi_tx_reg); | 1890 | I915_READ(fdi_tx_reg); |
1917 | udelay(100); | 1891 | udelay(100); |
1918 | } | 1892 | } |
1893 | } | ||
1894 | |||
1895 | static void ironlake_crtc_enable(struct drm_crtc *crtc) | ||
1896 | { | ||
1897 | struct drm_device *dev = crtc->dev; | ||
1898 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
1899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | ||
1900 | int pipe = intel_crtc->pipe; | ||
1901 | int plane = intel_crtc->plane; | ||
1902 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; | ||
1903 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | ||
1904 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; | ||
1905 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; | ||
1906 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; | ||
1907 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | ||
1908 | int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; | ||
1909 | int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | ||
1910 | int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | ||
1911 | int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | ||
1912 | int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | ||
1913 | int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | ||
1914 | int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | ||
1915 | int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B; | ||
1916 | int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B; | ||
1917 | int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B; | ||
1918 | int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; | ||
1919 | int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; | ||
1920 | int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; | ||
1921 | int trans_dpll_sel = (pipe == 0) ? 0 : 1; | ||
1922 | u32 temp; | ||
1923 | u32 pipe_bpc; | ||
1924 | |||
1925 | temp = I915_READ(pipeconf_reg); | ||
1926 | pipe_bpc = temp & PIPE_BPC_MASK; | ||
1927 | |||
1928 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | ||
1929 | temp = I915_READ(PCH_LVDS); | ||
1930 | if ((temp & LVDS_PORT_EN) == 0) { | ||
1931 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | ||
1932 | POSTING_READ(PCH_LVDS); | ||
1933 | } | ||
1934 | } | ||
1935 | |||
1936 | ironlake_fdi_enable(crtc); | ||
1919 | 1937 | ||
1920 | /* Enable panel fitting for LVDS */ | 1938 | /* Enable panel fitting for LVDS */ |
1921 | if (dev_priv->pch_pf_size && | 1939 | if (dev_priv->pch_pf_size && |