diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2011-01-06 21:19:18 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-01-06 23:11:25 -0500 |
commit | badbb57b93adda990b4e2420ddfdf834504a217e (patch) | |
tree | ef0e873ac135d9b26dcd39f3cf8f1996faaa40d7 /drivers/gpu/drm | |
parent | a001182af807e2e0e1eb497dc5418d1220406d9b (diff) |
drm/radeon/kms: DCE5 atom dig encoder updates
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_encoders.c | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index 76835b0397a..989ba26135b 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
@@ -743,6 +743,7 @@ union dig_encoder_control { | |||
743 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; | 743 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; |
744 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; | 744 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; |
745 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; | 745 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; |
746 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; | ||
746 | }; | 747 | }; |
747 | 748 | ||
748 | void | 749 | void |
@@ -758,6 +759,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
758 | uint8_t frev, crev; | 759 | uint8_t frev, crev; |
759 | int dp_clock = 0; | 760 | int dp_clock = 0; |
760 | int dp_lane_count = 0; | 761 | int dp_lane_count = 0; |
762 | int hpd_id = RADEON_HPD_NONE; | ||
761 | 763 | ||
762 | if (connector) { | 764 | if (connector) { |
763 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 765 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
@@ -766,6 +768,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
766 | 768 | ||
767 | dp_clock = dig_connector->dp_clock; | 769 | dp_clock = dig_connector->dp_clock; |
768 | dp_lane_count = dig_connector->dp_lane_count; | 770 | dp_lane_count = dig_connector->dp_lane_count; |
771 | hpd_id = radeon_connector->hpd.hpd; | ||
769 | } | 772 | } |
770 | 773 | ||
771 | /* no dig encoder assigned */ | 774 | /* no dig encoder assigned */ |
@@ -790,19 +793,36 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
790 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | 793 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
791 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); | 794 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); |
792 | 795 | ||
793 | if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { | 796 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || |
794 | if (dp_clock == 270000) | 797 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) |
795 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | ||
796 | args.v1.ucLaneNum = dp_lane_count; | 798 | args.v1.ucLaneNum = dp_lane_count; |
797 | } else if (radeon_encoder->pixel_clock > 165000) | 799 | else if (radeon_encoder->pixel_clock > 165000) |
798 | args.v1.ucLaneNum = 8; | 800 | args.v1.ucLaneNum = 8; |
799 | else | 801 | else |
800 | args.v1.ucLaneNum = 4; | 802 | args.v1.ucLaneNum = 4; |
801 | 803 | ||
802 | if (ASIC_IS_DCE4(rdev)) { | 804 | if (ASIC_IS_DCE5(rdev)) { |
805 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || | ||
806 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) { | ||
807 | if (dp_clock == 270000) | ||
808 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; | ||
809 | else if (dp_clock == 540000) | ||
810 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; | ||
811 | } | ||
812 | args.v4.acConfig.ucDigSel = dig->dig_encoder; | ||
813 | args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; | ||
814 | if (hpd_id == RADEON_HPD_NONE) | ||
815 | args.v4.ucHPD_ID = 0; | ||
816 | else | ||
817 | args.v4.ucHPD_ID = hpd_id + 1; | ||
818 | } else if (ASIC_IS_DCE4(rdev)) { | ||
819 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) | ||
820 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; | ||
803 | args.v3.acConfig.ucDigSel = dig->dig_encoder; | 821 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
804 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; | 822 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; |
805 | } else { | 823 | } else { |
824 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) | ||
825 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | ||
806 | switch (radeon_encoder->encoder_id) { | 826 | switch (radeon_encoder->encoder_id) { |
807 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | 827 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
808 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; | 828 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
@@ -1538,6 +1558,7 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) | |||
1538 | struct radeon_encoder_atom_dig *dig; | 1558 | struct radeon_encoder_atom_dig *dig; |
1539 | uint32_t dig_enc_in_use = 0; | 1559 | uint32_t dig_enc_in_use = 0; |
1540 | 1560 | ||
1561 | /* DCE4/5 */ | ||
1541 | if (ASIC_IS_DCE4(rdev)) { | 1562 | if (ASIC_IS_DCE4(rdev)) { |
1542 | dig = radeon_encoder->enc_priv; | 1563 | dig = radeon_encoder->enc_priv; |
1543 | if (ASIC_IS_DCE41(rdev)) { | 1564 | if (ASIC_IS_DCE41(rdev)) { |