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authorAlex Deucher <alexdeucher@gmail.com>2010-08-03 19:59:20 -0400
committerDave Airlie <airlied@redhat.com>2010-08-03 20:03:50 -0400
commit5b1714d386a2f0c0d270e3abe1ac39ad1b0ba010 (patch)
tree8992a96ad5edcbc60b44d3541588309d8b866293 /drivers/gpu/drm
parentd65d65b175a29bd7ea2bb69c046419329c4a5db7 (diff)
drm/radeon/kms: enable underscan option for digital connectors
This connector attribute allows you to enable or disable underscan on a digital output to compensate for panels that automatically overscan (e.g., many HDMI TVs). Valid values for the attribute are: off - forces underscan off on - forces underscan on auto - enables underscan if an HDMI TV is connected, off otherwise default value is auto. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c36
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c23
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c41
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h18
5 files changed, 98 insertions, 25 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index a2e65d9f2a1..12ad512bd3d 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -44,10 +44,6 @@ static void atombios_overscan_setup(struct drm_crtc *crtc,
44 44
45 memset(&args, 0, sizeof(args)); 45 memset(&args, 0, sizeof(args));
46 46
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id; 47 args.ucCRTC = radeon_crtc->crtc_id;
52 48
53 switch (radeon_crtc->rmx_type) { 49 switch (radeon_crtc->rmx_type) {
@@ -56,7 +52,6 @@ static void atombios_overscan_setup(struct drm_crtc *crtc,
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
60 break; 55 break;
61 case RMX_ASPECT: 56 case RMX_ASPECT:
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
@@ -69,17 +64,16 @@ static void atombios_overscan_setup(struct drm_crtc *crtc,
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
71 } 66 }
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
73 break; 67 break;
74 case RMX_FULL: 68 case RMX_FULL:
75 default: 69 default:
76 args.usOverscanRight = 0; 70 args.usOverscanRight = radeon_crtc->h_border;
77 args.usOverscanLeft = 0; 71 args.usOverscanLeft = radeon_crtc->h_border;
78 args.usOverscanBottom = 0; 72 args.usOverscanBottom = radeon_crtc->v_border;
79 args.usOverscanTop = 0; 73 args.usOverscanTop = radeon_crtc->v_border;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 break; 74 break;
82 } 75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
83} 77}
84 78
85static void atombios_scaler_setup(struct drm_crtc *crtc) 79static void atombios_scaler_setup(struct drm_crtc *crtc)
@@ -282,22 +276,22 @@ atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
282 u16 misc = 0; 276 u16 misc = 0;
283 277
284 memset(&args, 0, sizeof(args)); 278 memset(&args, 0, sizeof(args));
285 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay); 279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
286 args.usH_Blanking_Time = 280 args.usH_Blanking_Time =
287 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay); 281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
288 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay); 282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
289 args.usV_Blanking_Time = 283 args.usV_Blanking_Time =
290 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay); 284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
291 args.usH_SyncOffset = 285 args.usH_SyncOffset =
292 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay); 286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
293 args.usH_SyncWidth = 287 args.usH_SyncWidth =
294 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
295 args.usV_SyncOffset = 289 args.usV_SyncOffset =
296 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay); 290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
297 args.usV_SyncWidth = 291 args.usV_SyncWidth =
298 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
299 /*args.ucH_Border = mode->hborder;*/ 293 args.ucH_Border = radeon_crtc->h_border;
300 /*args.ucV_Border = mode->vborder;*/ 294 args.ucV_Border = radeon_crtc->v_border;
301 295
302 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
303 misc |= ATOM_VSYNC_POLARITY; 297 misc |= ATOM_VSYNC_POLARITY;
@@ -1176,10 +1170,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1176 atombios_crtc_set_pll(crtc, adjusted_mode); 1170 atombios_crtc_set_pll(crtc, adjusted_mode);
1177 atombios_enable_ss(crtc); 1171 atombios_enable_ss(crtc);
1178 1172
1179 if (ASIC_IS_DCE4(rdev)) 1173 if (ASIC_IS_AVIVO(rdev))
1180 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1174 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1181 else if (ASIC_IS_AVIVO(rdev))
1182 atombios_crtc_set_timing(crtc, adjusted_mode);
1183 else { 1175 else {
1184 atombios_crtc_set_timing(crtc, adjusted_mode); 1176 atombios_crtc_set_timing(crtc, adjusted_mode);
1185 if (radeon_crtc->crtc_id == 0) 1177 if (radeon_crtc->crtc_id == 0)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 6b9aac754f1..609eda6bcb7 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -312,6 +312,20 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
312 } 312 }
313 } 313 }
314 314
315 if (property == rdev->mode_info.underscan_property) {
316 /* need to find digital encoder on connector */
317 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
318 if (!encoder)
319 return 0;
320
321 radeon_encoder = to_radeon_encoder(encoder);
322
323 if (radeon_encoder->underscan_type != val) {
324 radeon_encoder->underscan_type = val;
325 radeon_property_change_mode(&radeon_encoder->base);
326 }
327 }
328
315 if (property == rdev->mode_info.tv_std_property) { 329 if (property == rdev->mode_info.tv_std_property) {
316 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC); 330 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC);
317 if (!encoder) { 331 if (!encoder) {
@@ -1120,6 +1134,9 @@ radeon_add_atom_connector(struct drm_device *dev,
1120 drm_connector_attach_property(&radeon_connector->base, 1134 drm_connector_attach_property(&radeon_connector->base,
1121 rdev->mode_info.coherent_mode_property, 1135 rdev->mode_info.coherent_mode_property,
1122 1); 1136 1);
1137 drm_connector_attach_property(&radeon_connector->base,
1138 rdev->mode_info.underscan_property,
1139 UNDERSCAN_AUTO);
1123 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1140 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1124 radeon_connector->dac_load_detect = true; 1141 radeon_connector->dac_load_detect = true;
1125 drm_connector_attach_property(&radeon_connector->base, 1142 drm_connector_attach_property(&radeon_connector->base,
@@ -1145,6 +1162,9 @@ radeon_add_atom_connector(struct drm_device *dev,
1145 drm_connector_attach_property(&radeon_connector->base, 1162 drm_connector_attach_property(&radeon_connector->base,
1146 rdev->mode_info.coherent_mode_property, 1163 rdev->mode_info.coherent_mode_property,
1147 1); 1164 1);
1165 drm_connector_attach_property(&radeon_connector->base,
1166 rdev->mode_info.underscan_property,
1167 UNDERSCAN_AUTO);
1148 subpixel_order = SubPixelHorizontalRGB; 1168 subpixel_order = SubPixelHorizontalRGB;
1149 break; 1169 break;
1150 case DRM_MODE_CONNECTOR_DisplayPort: 1170 case DRM_MODE_CONNECTOR_DisplayPort:
@@ -1176,6 +1196,9 @@ radeon_add_atom_connector(struct drm_device *dev,
1176 drm_connector_attach_property(&radeon_connector->base, 1196 drm_connector_attach_property(&radeon_connector->base,
1177 rdev->mode_info.coherent_mode_property, 1197 rdev->mode_info.coherent_mode_property,
1178 1); 1198 1);
1199 drm_connector_attach_property(&radeon_connector->base,
1200 rdev->mode_info.underscan_property,
1201 UNDERSCAN_AUTO);
1179 break; 1202 break;
1180 case DRM_MODE_CONNECTOR_SVIDEO: 1203 case DRM_MODE_CONNECTOR_SVIDEO:
1181 case DRM_MODE_CONNECTOR_Composite: 1204 case DRM_MODE_CONNECTOR_Composite:
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 12a54145b64..74dac9635d7 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -921,6 +921,12 @@ static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
921 { TV_STD_SECAM, "secam" }, 921 { TV_STD_SECAM, "secam" },
922}; 922};
923 923
924static struct drm_prop_enum_list radeon_underscan_enum_list[] =
925{ { UNDERSCAN_OFF, "off" },
926 { UNDERSCAN_ON, "on" },
927 { UNDERSCAN_AUTO, "auto" },
928};
929
924static int radeon_modeset_create_props(struct radeon_device *rdev) 930static int radeon_modeset_create_props(struct radeon_device *rdev)
925{ 931{
926 int i, sz; 932 int i, sz;
@@ -974,6 +980,18 @@ static int radeon_modeset_create_props(struct radeon_device *rdev)
974 radeon_tv_std_enum_list[i].name); 980 radeon_tv_std_enum_list[i].name);
975 } 981 }
976 982
983 sz = ARRAY_SIZE(radeon_underscan_enum_list);
984 rdev->mode_info.underscan_property =
985 drm_property_create(rdev->ddev,
986 DRM_MODE_PROP_ENUM,
987 "underscan", sz);
988 for (i = 0; i < sz; i++) {
989 drm_property_add_enum(rdev->mode_info.underscan_property,
990 i,
991 radeon_underscan_enum_list[i].type,
992 radeon_underscan_enum_list[i].name);
993 }
994
977 return 0; 995 return 0;
978} 996}
979 997
@@ -1069,17 +1087,26 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1069 struct drm_display_mode *adjusted_mode) 1087 struct drm_display_mode *adjusted_mode)
1070{ 1088{
1071 struct drm_device *dev = crtc->dev; 1089 struct drm_device *dev = crtc->dev;
1090 struct radeon_device *rdev = dev->dev_private;
1072 struct drm_encoder *encoder; 1091 struct drm_encoder *encoder;
1073 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1092 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1074 struct radeon_encoder *radeon_encoder; 1093 struct radeon_encoder *radeon_encoder;
1094 struct drm_connector *connector;
1095 struct radeon_connector *radeon_connector;
1075 bool first = true; 1096 bool first = true;
1076 u32 src_v = 1, dst_v = 1; 1097 u32 src_v = 1, dst_v = 1;
1077 u32 src_h = 1, dst_h = 1; 1098 u32 src_h = 1, dst_h = 1;
1078 1099
1100 radeon_crtc->h_border = 0;
1101 radeon_crtc->v_border = 0;
1102
1079 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1103 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1080 if (encoder->crtc != crtc) 1104 if (encoder->crtc != crtc)
1081 continue; 1105 continue;
1082 radeon_encoder = to_radeon_encoder(encoder); 1106 radeon_encoder = to_radeon_encoder(encoder);
1107 connector = radeon_get_connector_for_encoder(encoder);
1108 radeon_connector = to_radeon_connector(connector);
1109
1083 if (first) { 1110 if (first) {
1084 /* set scaling */ 1111 /* set scaling */
1085 if (radeon_encoder->rmx_type == RMX_OFF) 1112 if (radeon_encoder->rmx_type == RMX_OFF)
@@ -1097,6 +1124,20 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1097 memcpy(&radeon_crtc->native_mode, 1124 memcpy(&radeon_crtc->native_mode,
1098 &radeon_encoder->native_mode, 1125 &radeon_encoder->native_mode,
1099 sizeof(struct drm_display_mode)); 1126 sizeof(struct drm_display_mode));
1127
1128 /* fix up for overscan on hdmi */
1129 if (ASIC_IS_AVIVO(rdev) &&
1130 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1131 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1132 drm_detect_hdmi_monitor(radeon_connector->edid)))) {
1133 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1134 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1135 radeon_crtc->rmx_type = RMX_FULL;
1136 src_v = crtc->mode.vdisplay;
1137 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1138 src_h = crtc->mode.hdisplay;
1139 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1140 }
1100 first = false; 1141 first = false;
1101 } else { 1142 } else {
1102 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1143 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 5e7a0536c9c..4a4ff983cef 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -212,7 +212,7 @@ void radeon_encoder_set_active_device(struct drm_encoder *encoder)
212 } 212 }
213} 213}
214 214
215static struct drm_connector * 215struct drm_connector *
216radeon_get_connector_for_encoder(struct drm_encoder *encoder) 216radeon_get_connector_for_encoder(struct drm_encoder *encoder)
217{ 217{
218 struct drm_device *dev = encoder->dev; 218 struct drm_device *dev = encoder->dev;
@@ -1694,6 +1694,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1694 radeon_encoder->encoder_id = encoder_id; 1694 radeon_encoder->encoder_id = encoder_id;
1695 radeon_encoder->devices = supported_device; 1695 radeon_encoder->devices = supported_device;
1696 radeon_encoder->rmx_type = RMX_OFF; 1696 radeon_encoder->rmx_type = RMX_OFF;
1697 radeon_encoder->underscan_type = UNDERSCAN_OFF;
1697 1698
1698 switch (radeon_encoder->encoder_id) { 1699 switch (radeon_encoder->encoder_id) {
1699 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1700 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
@@ -1707,6 +1708,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1707 } else { 1708 } else {
1708 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 1709 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1709 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 1710 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1711 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1710 } 1712 }
1711 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1713 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1712 break; 1714 break;
@@ -1736,6 +1738,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1736 } else { 1738 } else {
1737 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 1739 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1738 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 1740 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1741 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1739 } 1742 }
1740 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1743 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1741 break; 1744 break;
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 95696aa57ac..71aea4037e9 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -66,6 +66,12 @@ enum radeon_tv_std {
66 TV_STD_PAL_N, 66 TV_STD_PAL_N,
67}; 67};
68 68
69enum radeon_underscan_type {
70 UNDERSCAN_OFF,
71 UNDERSCAN_ON,
72 UNDERSCAN_AUTO,
73};
74
69enum radeon_hpd_id { 75enum radeon_hpd_id {
70 RADEON_HPD_1 = 0, 76 RADEON_HPD_1 = 0,
71 RADEON_HPD_2, 77 RADEON_HPD_2,
@@ -226,10 +232,12 @@ struct radeon_mode_info {
226 struct drm_property *coherent_mode_property; 232 struct drm_property *coherent_mode_property;
227 /* DAC enable load detect */ 233 /* DAC enable load detect */
228 struct drm_property *load_detect_property; 234 struct drm_property *load_detect_property;
229 /* TV standard load detect */ 235 /* TV standard */
230 struct drm_property *tv_std_property; 236 struct drm_property *tv_std_property;
231 /* legacy TMDS PLL detect */ 237 /* legacy TMDS PLL detect */
232 struct drm_property *tmds_pll_property; 238 struct drm_property *tmds_pll_property;
239 /* underscan */
240 struct drm_property *underscan_property;
233 /* hardcoded DFP edid from BIOS */ 241 /* hardcoded DFP edid from BIOS */
234 struct edid *bios_hardcoded_edid; 242 struct edid *bios_hardcoded_edid;
235 243
@@ -266,6 +274,8 @@ struct radeon_crtc {
266 uint32_t legacy_display_base_addr; 274 uint32_t legacy_display_base_addr;
267 uint32_t legacy_cursor_offset; 275 uint32_t legacy_cursor_offset;
268 enum radeon_rmx_type rmx_type; 276 enum radeon_rmx_type rmx_type;
277 u8 h_border;
278 u8 v_border;
269 fixed20_12 vsc; 279 fixed20_12 vsc;
270 fixed20_12 hsc; 280 fixed20_12 hsc;
271 struct drm_display_mode native_mode; 281 struct drm_display_mode native_mode;
@@ -354,6 +364,7 @@ struct radeon_encoder {
354 uint32_t flags; 364 uint32_t flags;
355 uint32_t pixel_clock; 365 uint32_t pixel_clock;
356 enum radeon_rmx_type rmx_type; 366 enum radeon_rmx_type rmx_type;
367 enum radeon_underscan_type underscan_type;
357 struct drm_display_mode native_mode; 368 struct drm_display_mode native_mode;
358 void *enc_priv; 369 void *enc_priv;
359 int audio_polling_active; 370 int audio_polling_active;
@@ -392,7 +403,7 @@ struct radeon_connector {
392 uint32_t connector_id; 403 uint32_t connector_id;
393 uint32_t devices; 404 uint32_t devices;
394 struct radeon_i2c_chan *ddc_bus; 405 struct radeon_i2c_chan *ddc_bus;
395 /* some systems have a an hdmi and vga port with a shared ddc line */ 406 /* some systems have an hdmi and vga port with a shared ddc line */
396 bool shared_ddc; 407 bool shared_ddc;
397 bool use_digital; 408 bool use_digital;
398 /* we need to mind the EDID between detect 409 /* we need to mind the EDID between detect
@@ -414,6 +425,9 @@ radeon_combios_get_tv_info(struct radeon_device *rdev);
414extern enum radeon_tv_std 425extern enum radeon_tv_std
415radeon_atombios_get_tv_info(struct radeon_device *rdev); 426radeon_atombios_get_tv_info(struct radeon_device *rdev);
416 427
428extern struct drm_connector *
429radeon_get_connector_for_encoder(struct drm_encoder *encoder);
430
417extern void radeon_connector_hotplug(struct drm_connector *connector); 431extern void radeon_connector_hotplug(struct drm_connector *connector);
418extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 432extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
419extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 433extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,