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authorMark Brown <broonie@opensource.wolfsonmicro.com>2012-03-14 09:13:25 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-03-14 09:13:25 -0400
commit7d9aca39dcacd2b3f42e2e287162329f410f93e1 (patch)
tree2907b680b2b7625226f46d23d74ccc9c58ad0362 /drivers/gpu/drm/radeon
parente1c1c69c8fc7656c33460c8e085ac0d0be22ac3b (diff)
parenta0cc0209abb9fe2b9ab71aa41be70eddd0cbdd61 (diff)
Merge remote-tracking branch 'regmap/topic/drivers' into regmap-next
Resolved simple add/add conflicts: drivers/base/regmap/internal.h drivers/base/regmap/regmap.c
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c64
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c40
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c89
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c2
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h1
-rw-r--r--drivers/gpu/drm/radeon/ni.c1
-rw-r--r--drivers/gpu/drm/radeon/nid.h1
-rw-r--r--drivers/gpu/drm/radeon/r100.c4
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c35
-rw-r--r--drivers/gpu/drm/radeon/radeon.h84
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c17
-rw-r--r--drivers/gpu/drm/radeon/radeon_atpx_handler.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c12
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c77
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h8
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c37
-rw-r--r--drivers/gpu/drm/radeon/rs600.c4
22 files changed, 325 insertions, 174 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 0fda830ef80..742f17f009a 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -355,15 +355,12 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
356} 356}
357 357
358static void atombios_disable_ss(struct drm_crtc *crtc) 358static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
359{ 359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl; 360 u32 ss_cntl;
364 361
365 if (ASIC_IS_DCE4(rdev)) { 362 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) { 363 switch (pll_id) {
367 case ATOM_PPLL1: 364 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 365 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 366 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
@@ -379,7 +376,7 @@ static void atombios_disable_ss(struct drm_crtc *crtc)
379 return; 376 return;
380 } 377 }
381 } else if (ASIC_IS_AVIVO(rdev)) { 378 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) { 379 switch (pll_id) {
383 case ATOM_PPLL1: 380 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 381 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1; 382 ss_cntl &= ~1;
@@ -406,13 +403,11 @@ union atom_enable_ss {
406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 403 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
407}; 404};
408 405
409static void atombios_crtc_program_ss(struct drm_crtc *crtc, 406static void atombios_crtc_program_ss(struct radeon_device *rdev,
410 int enable, 407 int enable,
411 int pll_id, 408 int pll_id,
412 struct radeon_atom_ss *ss) 409 struct radeon_atom_ss *ss)
413{ 410{
414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 411 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
417 union atom_enable_ss args; 412 union atom_enable_ss args;
418 413
@@ -479,7 +474,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
479 } else if (ASIC_IS_AVIVO(rdev)) { 474 } else if (ASIC_IS_AVIVO(rdev)) {
480 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 475 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
481 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 476 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
482 atombios_disable_ss(crtc); 477 atombios_disable_ss(rdev, pll_id);
483 return; 478 return;
484 } 479 }
485 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
@@ -491,7 +486,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
491 } else { 486 } else {
492 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 487 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
493 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 488 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
494 atombios_disable_ss(crtc); 489 atombios_disable_ss(rdev, pll_id);
495 return; 490 return;
496 } 491 }
497 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 492 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
@@ -523,6 +518,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
523 int encoder_mode = 0; 518 int encoder_mode = 0;
524 u32 dp_clock = mode->clock; 519 u32 dp_clock = mode->clock;
525 int bpc = 8; 520 int bpc = 8;
521 bool is_duallink = false;
526 522
527 /* reset the pll flags */ 523 /* reset the pll flags */
528 pll->flags = 0; 524 pll->flags = 0;
@@ -557,6 +553,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
557 if (connector && connector->display_info.bpc) 553 if (connector && connector->display_info.bpc)
558 bpc = connector->display_info.bpc; 554 bpc = connector->display_info.bpc;
559 encoder_mode = atombios_get_encoder_mode(encoder); 555 encoder_mode = atombios_get_encoder_mode(encoder);
556 is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 557 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
561 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 558 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
562 if (connector) { 559 if (connector) {
@@ -652,7 +649,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
652 if (dig->coherent_mode) 649 if (dig->coherent_mode)
653 args.v3.sInput.ucDispPllConfig |= 650 args.v3.sInput.ucDispPllConfig |=
654 DISPPLL_CONFIG_COHERENT_MODE; 651 DISPPLL_CONFIG_COHERENT_MODE;
655 if (mode->clock > 165000) 652 if (is_duallink)
656 args.v3.sInput.ucDispPllConfig |= 653 args.v3.sInput.ucDispPllConfig |=
657 DISPPLL_CONFIG_DUAL_LINK; 654 DISPPLL_CONFIG_DUAL_LINK;
658 } 655 }
@@ -702,11 +699,9 @@ union set_pixel_clock {
702/* on DCE5, make sure the voltage is high enough to support the 699/* on DCE5, make sure the voltage is high enough to support the
703 * required disp clk. 700 * required disp clk.
704 */ 701 */
705static void atombios_crtc_set_dcpll(struct drm_crtc *crtc, 702static void atombios_crtc_set_dcpll(struct radeon_device *rdev,
706 u32 dispclk) 703 u32 dispclk)
707{ 704{
708 struct drm_device *dev = crtc->dev;
709 struct radeon_device *rdev = dev->dev_private;
710 u8 frev, crev; 705 u8 frev, crev;
711 int index; 706 int index;
712 union set_pixel_clock args; 707 union set_pixel_clock args;
@@ -996,7 +991,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
996 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 991 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
997 &ref_div, &post_div); 992 &ref_div, &post_div);
998 993
999 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss); 994 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
1000 995
1001 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 996 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1002 encoder_mode, radeon_encoder->encoder_id, mode->clock, 997 encoder_mode, radeon_encoder->encoder_id, mode->clock,
@@ -1019,7 +1014,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
1019 ss.step = step_size; 1014 ss.step = step_size;
1020 } 1015 }
1021 1016
1022 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss); 1017 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1023 } 1018 }
1024} 1019}
1025 1020
@@ -1189,7 +1184,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1189 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1184 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1190 1185
1191 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1186 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1192 crtc->mode.vdisplay); 1187 target_fb->height);
1193 x &= ~3; 1188 x &= ~3;
1194 y &= ~1; 1189 y &= ~1;
1195 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1190 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
@@ -1358,7 +1353,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1358 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1353 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1359 1354
1360 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1355 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1361 crtc->mode.vdisplay); 1356 target_fb->height);
1362 x &= ~3; 1357 x &= ~3;
1363 y &= ~1; 1358 y &= ~1;
1364 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1359 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
@@ -1494,6 +1489,24 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1494 1489
1495} 1490}
1496 1491
1492void radeon_atom_dcpll_init(struct radeon_device *rdev)
1493{
1494 /* always set DCPLL */
1495 if (ASIC_IS_DCE4(rdev)) {
1496 struct radeon_atom_ss ss;
1497 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1498 ASIC_INTERNAL_SS_ON_DCPLL,
1499 rdev->clock.default_dispclk);
1500 if (ss_enabled)
1501 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);
1502 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1503 atombios_crtc_set_dcpll(rdev, rdev->clock.default_dispclk);
1504 if (ss_enabled)
1505 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);
1506 }
1507
1508}
1509
1497int atombios_crtc_mode_set(struct drm_crtc *crtc, 1510int atombios_crtc_mode_set(struct drm_crtc *crtc,
1498 struct drm_display_mode *mode, 1511 struct drm_display_mode *mode,
1499 struct drm_display_mode *adjusted_mode, 1512 struct drm_display_mode *adjusted_mode,
@@ -1515,19 +1528,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1515 } 1528 }
1516 } 1529 }
1517 1530
1518 /* always set DCPLL */
1519 if (ASIC_IS_DCE4(rdev)) {
1520 struct radeon_atom_ss ss;
1521 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1522 ASIC_INTERNAL_SS_ON_DCPLL,
1523 rdev->clock.default_dispclk);
1524 if (ss_enabled)
1525 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1526 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1527 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
1528 if (ss_enabled)
1529 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1530 }
1531 atombios_crtc_set_pll(crtc, adjusted_mode); 1531 atombios_crtc_set_pll(crtc, adjusted_mode);
1532 1532
1533 if (ASIC_IS_DCE4(rdev)) 1533 if (ASIC_IS_DCE4(rdev))
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 6fb335a4fdd..552b436451f 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -549,8 +549,8 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
549 return false; 549 return false;
550} 550}
551 551
552static void radeon_dp_set_panel_mode(struct drm_encoder *encoder, 552int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
553 struct drm_connector *connector) 553 struct drm_connector *connector)
554{ 554{
555 struct drm_device *dev = encoder->dev; 555 struct drm_device *dev = encoder->dev;
556 struct radeon_device *rdev = dev->dev_private; 556 struct radeon_device *rdev = dev->dev_private;
@@ -558,28 +558,33 @@ static void radeon_dp_set_panel_mode(struct drm_encoder *encoder,
558 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 558 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
559 559
560 if (!ASIC_IS_DCE4(rdev)) 560 if (!ASIC_IS_DCE4(rdev))
561 return; 561 return panel_mode;
562 562
563 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 563 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
564 ENCODER_OBJECT_ID_NUTMEG) 564 ENCODER_OBJECT_ID_NUTMEG)
565 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 565 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
566 else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 566 else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
567 ENCODER_OBJECT_ID_TRAVIS) 567 ENCODER_OBJECT_ID_TRAVIS) {
568 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 568 u8 id[6];
569 else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 569 int i;
570 for (i = 0; i < 6; i++)
571 id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i);
572 if (id[0] == 0x73 &&
573 id[1] == 0x69 &&
574 id[2] == 0x76 &&
575 id[3] == 0x61 &&
576 id[4] == 0x72 &&
577 id[5] == 0x54)
578 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
579 else
580 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
581 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
570 u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 582 u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
571 if (tmp & 1) 583 if (tmp & 1)
572 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 584 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
573 } 585 }
574 586
575 atombios_dig_encoder_setup(encoder, 587 return panel_mode;
576 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
577 panel_mode);
578
579 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
580 (panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
581 radeon_write_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
582 }
583} 588}
584 589
585void radeon_dp_set_link_config(struct drm_connector *connector, 590void radeon_dp_set_link_config(struct drm_connector *connector,
@@ -717,6 +722,8 @@ static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
717 722
718static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 723static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
719{ 724{
725 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
726 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
720 u8 tmp; 727 u8 tmp;
721 728
722 /* power up the sink */ 729 /* power up the sink */
@@ -732,7 +739,10 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
732 radeon_write_dpcd_reg(dp_info->radeon_connector, 739 radeon_write_dpcd_reg(dp_info->radeon_connector,
733 DP_DOWNSPREAD_CTRL, 0); 740 DP_DOWNSPREAD_CTRL, 0);
734 741
735 radeon_dp_set_panel_mode(dp_info->encoder, dp_info->connector); 742 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
743 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
744 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
745 }
736 746
737 /* set the lane count on the sink */ 747 /* set the lane count on the sink */
738 tmp = dp_info->dp_lane_count; 748 tmp = dp_info->dp_lane_count;
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index f1f06ca9f1f..b88c4608731 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -57,22 +57,6 @@ static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
57 } 57 }
58} 58}
59 59
60static struct drm_connector *
61radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
62{
63 struct drm_device *dev = encoder->dev;
64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65 struct drm_connector *connector;
66 struct radeon_connector *radeon_connector;
67
68 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
69 radeon_connector = to_radeon_connector(connector);
70 if (radeon_encoder->devices & radeon_connector->devices)
71 return connector;
72 }
73 return NULL;
74}
75
76static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 60static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
77 struct drm_display_mode *mode, 61 struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode) 62 struct drm_display_mode *adjusted_mode)
@@ -253,7 +237,7 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action)
253 /* R4xx, R5xx */ 237 /* R4xx, R5xx */
254 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 238 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
255 239
256 if (radeon_encoder->pixel_clock > 165000) 240 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
257 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 241 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
258 242
259 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 243 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
@@ -265,7 +249,7 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action)
265 /* DFP1, CRT1, TV1 depending on the type of port */ 249 /* DFP1, CRT1, TV1 depending on the type of port */
266 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 250 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
267 251
268 if (radeon_encoder->pixel_clock > 165000) 252 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
269 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 253 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
270 break; 254 break;
271 case 3: 255 case 3:
@@ -349,7 +333,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
349 } else { 333 } else {
350 if (dig->linkb) 334 if (dig->linkb)
351 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 335 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
352 if (radeon_encoder->pixel_clock > 165000) 336 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
353 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 337 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
354 /*if (pScrn->rgbBits == 8) */ 338 /*if (pScrn->rgbBits == 8) */
355 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 339 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
@@ -388,7 +372,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
388 } else { 372 } else {
389 if (dig->linkb) 373 if (dig->linkb)
390 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 374 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
391 if (radeon_encoder->pixel_clock > 165000) 375 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
392 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 376 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
393 } 377 }
394 break; 378 break;
@@ -432,7 +416,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
432 switch (connector->connector_type) { 416 switch (connector->connector_type) {
433 case DRM_MODE_CONNECTOR_DVII: 417 case DRM_MODE_CONNECTOR_DVII:
434 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 418 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
435 if (drm_detect_monitor_audio(radeon_connector->edid) && 419 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
436 radeon_audio) 420 radeon_audio)
437 return ATOM_ENCODER_MODE_HDMI; 421 return ATOM_ENCODER_MODE_HDMI;
438 else if (radeon_connector->use_digital) 422 else if (radeon_connector->use_digital)
@@ -443,7 +427,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
443 case DRM_MODE_CONNECTOR_DVID: 427 case DRM_MODE_CONNECTOR_DVID:
444 case DRM_MODE_CONNECTOR_HDMIA: 428 case DRM_MODE_CONNECTOR_HDMIA:
445 default: 429 default:
446 if (drm_detect_monitor_audio(radeon_connector->edid) && 430 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
447 radeon_audio) 431 radeon_audio)
448 return ATOM_ENCODER_MODE_HDMI; 432 return ATOM_ENCODER_MODE_HDMI;
449 else 433 else
@@ -457,7 +441,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
457 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 441 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
458 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 442 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
459 return ATOM_ENCODER_MODE_DP; 443 return ATOM_ENCODER_MODE_DP;
460 else if (drm_detect_monitor_audio(radeon_connector->edid) && 444 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
461 radeon_audio) 445 radeon_audio)
462 return ATOM_ENCODER_MODE_HDMI; 446 return ATOM_ENCODER_MODE_HDMI;
463 else 447 else
@@ -587,7 +571,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
587 571
588 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 572 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
589 args.v1.ucLaneNum = dp_lane_count; 573 args.v1.ucLaneNum = dp_lane_count;
590 else if (radeon_encoder->pixel_clock > 165000) 574 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
591 args.v1.ucLaneNum = 8; 575 args.v1.ucLaneNum = 8;
592 else 576 else
593 args.v1.ucLaneNum = 4; 577 args.v1.ucLaneNum = 4;
@@ -622,7 +606,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
622 606
623 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 607 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
624 args.v3.ucLaneNum = dp_lane_count; 608 args.v3.ucLaneNum = dp_lane_count;
625 else if (radeon_encoder->pixel_clock > 165000) 609 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
626 args.v3.ucLaneNum = 8; 610 args.v3.ucLaneNum = 8;
627 else 611 else
628 args.v3.ucLaneNum = 4; 612 args.v3.ucLaneNum = 4;
@@ -662,7 +646,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
662 646
663 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 647 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
664 args.v4.ucLaneNum = dp_lane_count; 648 args.v4.ucLaneNum = dp_lane_count;
665 else if (radeon_encoder->pixel_clock > 165000) 649 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
666 args.v4.ucLaneNum = 8; 650 args.v4.ucLaneNum = 8;
667 else 651 else
668 args.v4.ucLaneNum = 4; 652 args.v4.ucLaneNum = 4;
@@ -806,7 +790,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
806 if (is_dp) 790 if (is_dp)
807 args.v1.usPixelClock = 791 args.v1.usPixelClock =
808 cpu_to_le16(dp_clock / 10); 792 cpu_to_le16(dp_clock / 10);
809 else if (radeon_encoder->pixel_clock > 165000) 793 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
810 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 794 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
811 else 795 else
812 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 796 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
@@ -821,7 +805,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
821 805
822 if ((rdev->flags & RADEON_IS_IGP) && 806 if ((rdev->flags & RADEON_IS_IGP) &&
823 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 807 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
824 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { 808 if (is_dp ||
809 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
825 if (igp_lane_info & 0x1) 810 if (igp_lane_info & 0x1)
826 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 811 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
827 else if (igp_lane_info & 0x2) 812 else if (igp_lane_info & 0x2)
@@ -848,7 +833,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
848 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 833 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
849 if (dig->coherent_mode) 834 if (dig->coherent_mode)
850 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 835 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
851 if (radeon_encoder->pixel_clock > 165000) 836 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
852 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 837 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
853 } 838 }
854 break; 839 break;
@@ -863,7 +848,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
863 if (is_dp) 848 if (is_dp)
864 args.v2.usPixelClock = 849 args.v2.usPixelClock =
865 cpu_to_le16(dp_clock / 10); 850 cpu_to_le16(dp_clock / 10);
866 else if (radeon_encoder->pixel_clock > 165000) 851 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
867 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 852 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
868 else 853 else
869 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 854 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
@@ -891,7 +876,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
891 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 876 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
892 if (dig->coherent_mode) 877 if (dig->coherent_mode)
893 args.v2.acConfig.fCoherentMode = 1; 878 args.v2.acConfig.fCoherentMode = 1;
894 if (radeon_encoder->pixel_clock > 165000) 879 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
895 args.v2.acConfig.fDualLinkConnector = 1; 880 args.v2.acConfig.fDualLinkConnector = 1;
896 } 881 }
897 break; 882 break;
@@ -906,7 +891,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
906 if (is_dp) 891 if (is_dp)
907 args.v3.usPixelClock = 892 args.v3.usPixelClock =
908 cpu_to_le16(dp_clock / 10); 893 cpu_to_le16(dp_clock / 10);
909 else if (radeon_encoder->pixel_clock > 165000) 894 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
910 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 895 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
911 else 896 else
912 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 897 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
@@ -914,7 +899,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
914 899
915 if (is_dp) 900 if (is_dp)
916 args.v3.ucLaneNum = dp_lane_count; 901 args.v3.ucLaneNum = dp_lane_count;
917 else if (radeon_encoder->pixel_clock > 165000) 902 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
918 args.v3.ucLaneNum = 8; 903 args.v3.ucLaneNum = 8;
919 else 904 else
920 args.v3.ucLaneNum = 4; 905 args.v3.ucLaneNum = 4;
@@ -951,7 +936,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
951 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 936 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
952 if (dig->coherent_mode) 937 if (dig->coherent_mode)
953 args.v3.acConfig.fCoherentMode = 1; 938 args.v3.acConfig.fCoherentMode = 1;
954 if (radeon_encoder->pixel_clock > 165000) 939 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
955 args.v3.acConfig.fDualLinkConnector = 1; 940 args.v3.acConfig.fDualLinkConnector = 1;
956 } 941 }
957 break; 942 break;
@@ -966,7 +951,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
966 if (is_dp) 951 if (is_dp)
967 args.v4.usPixelClock = 952 args.v4.usPixelClock =
968 cpu_to_le16(dp_clock / 10); 953 cpu_to_le16(dp_clock / 10);
969 else if (radeon_encoder->pixel_clock > 165000) 954 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
970 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 955 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
971 else 956 else
972 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 957 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
@@ -974,7 +959,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
974 959
975 if (is_dp) 960 if (is_dp)
976 args.v4.ucLaneNum = dp_lane_count; 961 args.v4.ucLaneNum = dp_lane_count;
977 else if (radeon_encoder->pixel_clock > 165000) 962 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
978 args.v4.ucLaneNum = 8; 963 args.v4.ucLaneNum = 8;
979 else 964 else
980 args.v4.ucLaneNum = 4; 965 args.v4.ucLaneNum = 4;
@@ -1014,7 +999,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
1014 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 999 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1015 if (dig->coherent_mode) 1000 if (dig->coherent_mode)
1016 args.v4.acConfig.fCoherentMode = 1; 1001 args.v4.acConfig.fCoherentMode = 1;
1017 if (radeon_encoder->pixel_clock > 165000) 1002 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1018 args.v4.acConfig.fDualLinkConnector = 1; 1003 args.v4.acConfig.fDualLinkConnector = 1;
1019 } 1004 }
1020 break; 1005 break;
@@ -1137,7 +1122,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1137 if (dp_clock == 270000) 1122 if (dp_clock == 270000)
1138 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1123 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1139 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1124 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1140 } else if (radeon_encoder->pixel_clock > 165000) 1125 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1141 args.v1.sDigEncoder.ucLaneNum = 8; 1126 args.v1.sDigEncoder.ucLaneNum = 8;
1142 else 1127 else
1143 args.v1.sDigEncoder.ucLaneNum = 4; 1128 args.v1.sDigEncoder.ucLaneNum = 4;
@@ -1156,7 +1141,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1156 else if (dp_clock == 540000) 1141 else if (dp_clock == 540000)
1157 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1142 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1158 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1143 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1159 } else if (radeon_encoder->pixel_clock > 165000) 1144 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1160 args.v3.sExtEncoder.ucLaneNum = 8; 1145 args.v3.sExtEncoder.ucLaneNum = 8;
1161 else 1146 else
1162 args.v3.sExtEncoder.ucLaneNum = 4; 1147 args.v3.sExtEncoder.ucLaneNum = 4;
@@ -1341,7 +1326,8 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1341 switch (mode) { 1326 switch (mode) {
1342 case DRM_MODE_DPMS_ON: 1327 case DRM_MODE_DPMS_ON:
1343 /* some early dce3.2 boards have a bug in their transmitter control table */ 1328 /* some early dce3.2 boards have a bug in their transmitter control table */
1344 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) 1329 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) ||
1330 ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
1345 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1331 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1346 else 1332 else
1347 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1333 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
@@ -1351,8 +1337,6 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1351 ATOM_TRANSMITTER_ACTION_POWER_ON); 1337 ATOM_TRANSMITTER_ACTION_POWER_ON);
1352 radeon_dig_connector->edp_on = true; 1338 radeon_dig_connector->edp_on = true;
1353 } 1339 }
1354 if (ASIC_IS_DCE4(rdev))
1355 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1356 radeon_dp_link_train(encoder, connector); 1340 radeon_dp_link_train(encoder, connector);
1357 if (ASIC_IS_DCE4(rdev)) 1341 if (ASIC_IS_DCE4(rdev))
1358 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1342 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
@@ -1363,7 +1347,10 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1363 case DRM_MODE_DPMS_STANDBY: 1347 case DRM_MODE_DPMS_STANDBY:
1364 case DRM_MODE_DPMS_SUSPEND: 1348 case DRM_MODE_DPMS_SUSPEND:
1365 case DRM_MODE_DPMS_OFF: 1349 case DRM_MODE_DPMS_OFF:
1366 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1350 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
1351 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1352 else
1353 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1367 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1354 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1368 if (ASIC_IS_DCE4(rdev)) 1355 if (ASIC_IS_DCE4(rdev))
1369 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1356 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
@@ -1810,7 +1797,21 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1797 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1811 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1812 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1799 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1813 if (ASIC_IS_DCE4(rdev)) { 1800 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1801 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1802 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1803
1804 if (!connector)
1805 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1806 else
1807 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1808
1809 /* setup and enable the encoder */
1810 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1811 atombios_dig_encoder_setup(encoder,
1812 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1813 dig->panel_mode);
1814 } else if (ASIC_IS_DCE4(rdev)) {
1814 /* disable the transmitter */ 1815 /* disable the transmitter */
1815 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1816 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1816 /* setup and enable the encoder */ 1817 /* setup and enable the encoder */
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 636660fca8c..9be353b894c 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1455,6 +1455,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
1455#endif 1455#endif
1456 WREG32(CP_RB_CNTL, tmp); 1456 WREG32(CP_RB_CNTL, tmp);
1457 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1457 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1458 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1458 1459
1459 /* Set the write pointer delay */ 1460 /* Set the write pointer delay */
1460 WREG32(CP_RB_WPTR_DELAY, 0); 1461 WREG32(CP_RB_WPTR_DELAY, 0);
@@ -3190,6 +3191,7 @@ static int evergreen_startup(struct radeon_device *rdev)
3190 if (r) { 3191 if (r) {
3191 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 3192 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3192 rdev->accel_working = false; 3193 rdev->accel_working = false;
3194 return r;
3193 } 3195 }
3194 3196
3195 r = r600_audio_init(rdev); 3197 r = r600_audio_init(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index b502216d42a..74713d42df2 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -108,6 +108,7 @@
108#define CP_RB_WPTR_ADDR_HI 0xC11C 108#define CP_RB_WPTR_ADDR_HI 0xC11C
109#define CP_RB_WPTR_DELAY 0x8704 109#define CP_RB_WPTR_DELAY 0x8704
110#define CP_SEM_WAIT_TIMER 0x85BC 110#define CP_SEM_WAIT_TIMER 0x85BC
111#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
111#define CP_DEBUG 0xC1FC 112#define CP_DEBUG 0xC1FC
112 113
113 114
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 32113729540..db09065e68f 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1219,6 +1219,7 @@ int cayman_cp_resume(struct radeon_device *rdev)
1219 RREG32(GRBM_SOFT_RESET); 1219 RREG32(GRBM_SOFT_RESET);
1220 1220
1221 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1221 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1222 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1222 1223
1223 /* Set the write pointer delay */ 1224 /* Set the write pointer delay */
1224 WREG32(CP_RB_WPTR_DELAY, 0); 1225 WREG32(CP_RB_WPTR_DELAY, 0);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index f9df2a645e7..9a7f3b6e02d 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -222,6 +222,7 @@
222#define SCRATCH_UMSK 0x8540 222#define SCRATCH_UMSK 0x8540
223#define SCRATCH_ADDR 0x8544 223#define SCRATCH_ADDR 0x8544
224#define CP_SEM_WAIT_TIMER 0x85BC 224#define CP_SEM_WAIT_TIMER 0x85BC
225#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
225#define CP_COHER_CNTL2 0x85E8 226#define CP_COHER_CNTL2 0x85E8
226#define CP_ME_CNTL 0x86D8 227#define CP_ME_CNTL 0x86D8
227#define CP_ME_HALT (1 << 28) 228#define CP_ME_HALT (1 << 28)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index bfd36ab643a..18cd84fae99 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -789,9 +789,7 @@ int r100_irq_process(struct radeon_device *rdev)
789 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 789 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
790 break; 790 break;
791 default: 791 default:
792 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 792 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
793 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
794 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
795 break; 793 break;
796 } 794 }
797 } 795 }
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index d996f438113..accc032c103 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -468,27 +468,42 @@ set_default_state(struct radeon_device *rdev)
468 radeon_ring_write(ring, sq_stack_resource_mgmt_2); 468 radeon_ring_write(ring, sq_stack_resource_mgmt_2);
469} 469}
470 470
471#define I2F_MAX_BITS 15
472#define I2F_MAX_INPUT ((1 << I2F_MAX_BITS) - 1)
473#define I2F_SHIFT (24 - I2F_MAX_BITS)
474
475/*
476 * Converts unsigned integer into 32-bit IEEE floating point representation.
477 * Conversion is not universal and only works for the range from 0
478 * to 2^I2F_MAX_BITS-1. Currently we only use it with inputs between
479 * 0 and 16384 (inclusive), so I2F_MAX_BITS=15 is enough. If necessary,
480 * I2F_MAX_BITS can be increased, but that will add to the loop iterations
481 * and slow us down. Conversion is done by shifting the input and counting
482 * down until the first 1 reaches bit position 23. The resulting counter
483 * and the shifted input are, respectively, the exponent and the fraction.
484 * The sign is always zero.
485 */
471static uint32_t i2f(uint32_t input) 486static uint32_t i2f(uint32_t input)
472{ 487{
473 u32 result, i, exponent, fraction; 488 u32 result, i, exponent, fraction;
474 489
475 if ((input & 0x3fff) == 0) 490 WARN_ON_ONCE(input > I2F_MAX_INPUT);
476 result = 0; /* 0 is a special case */ 491
492 if ((input & I2F_MAX_INPUT) == 0)
493 result = 0;
477 else { 494 else {
478 exponent = 140; /* exponent biased by 127; */ 495 exponent = 126 + I2F_MAX_BITS;
479 fraction = (input & 0x3fff) << 10; /* cheat and only 496 fraction = (input & I2F_MAX_INPUT) << I2F_SHIFT;
480 handle numbers below 2^^15 */ 497
481 for (i = 0; i < 14; i++) { 498 for (i = 0; i < I2F_MAX_BITS; i++) {
482 if (fraction & 0x800000) 499 if (fraction & 0x800000)
483 break; 500 break;
484 else { 501 else {
485 fraction = fraction << 1; /* keep 502 fraction = fraction << 1;
486 shifting left until top bit = 1 */
487 exponent = exponent - 1; 503 exponent = exponent - 1;
488 } 504 }
489 } 505 }
490 result = exponent << 23 | (fraction & 0x7fffff); /* mask 506 result = exponent << 23 | (fraction & 0x7fffff);
491 off top bit; assumed 1 */
492 } 507 }
493 return result; 508 return result;
494} 509}
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 73e05cb85ec..1668ec1ee77 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -157,6 +157,47 @@ bool radeon_get_bios(struct radeon_device *rdev);
157 157
158 158
159/* 159/*
160 * Mutex which allows recursive locking from the same process.
161 */
162struct radeon_mutex {
163 struct mutex mutex;
164 struct task_struct *owner;
165 int level;
166};
167
168static inline void radeon_mutex_init(struct radeon_mutex *mutex)
169{
170 mutex_init(&mutex->mutex);
171 mutex->owner = NULL;
172 mutex->level = 0;
173}
174
175static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
176{
177 if (mutex_trylock(&mutex->mutex)) {
178 /* The mutex was unlocked before, so it's ours now */
179 mutex->owner = current;
180 } else if (mutex->owner != current) {
181 /* Another process locked the mutex, take it */
182 mutex_lock(&mutex->mutex);
183 mutex->owner = current;
184 }
185 /* Otherwise the mutex was already locked by this process */
186
187 mutex->level++;
188}
189
190static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
191{
192 if (--mutex->level > 0)
193 return;
194
195 mutex->owner = NULL;
196 mutex_unlock(&mutex->mutex);
197}
198
199
200/*
160 * Dummy page 201 * Dummy page
161 */ 202 */
162struct radeon_dummy_page { 203struct radeon_dummy_page {
@@ -598,7 +639,7 @@ struct radeon_ib {
598 * mutex protects scheduled_ibs, ready, alloc_bm 639 * mutex protects scheduled_ibs, ready, alloc_bm
599 */ 640 */
600struct radeon_ib_pool { 641struct radeon_ib_pool {
601 struct mutex mutex; 642 struct radeon_mutex mutex;
602 struct radeon_sa_manager sa_manager; 643 struct radeon_sa_manager sa_manager;
603 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 644 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
604 bool ready; 645 bool ready;
@@ -1355,47 +1396,6 @@ struct r600_vram_scratch {
1355 1396
1356 1397
1357/* 1398/*
1358 * Mutex which allows recursive locking from the same process.
1359 */
1360struct radeon_mutex {
1361 struct mutex mutex;
1362 struct task_struct *owner;
1363 int level;
1364};
1365
1366static inline void radeon_mutex_init(struct radeon_mutex *mutex)
1367{
1368 mutex_init(&mutex->mutex);
1369 mutex->owner = NULL;
1370 mutex->level = 0;
1371}
1372
1373static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
1374{
1375 if (mutex_trylock(&mutex->mutex)) {
1376 /* The mutex was unlocked before, so it's ours now */
1377 mutex->owner = current;
1378 } else if (mutex->owner != current) {
1379 /* Another process locked the mutex, take it */
1380 mutex_lock(&mutex->mutex);
1381 mutex->owner = current;
1382 }
1383 /* Otherwise the mutex was already locked by this process */
1384
1385 mutex->level++;
1386}
1387
1388static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
1389{
1390 if (--mutex->level > 0)
1391 return;
1392
1393 mutex->owner = NULL;
1394 mutex_unlock(&mutex->mutex);
1395}
1396
1397
1398/*
1399 * Core structure, functions and helpers. 1399 * Core structure, functions and helpers.
1400 */ 1400 */
1401typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1401typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 5082d17d14d..9e72daeeddc 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2931,6 +2931,20 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2931 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 2931 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2932 } 2932 }
2933 } 2933 }
2934 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
2935 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
2936 if (connected) {
2937 DRM_DEBUG_KMS("DFP6 connected\n");
2938 bios_0_scratch |= ATOM_S0_DFP6;
2939 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
2940 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
2941 } else {
2942 DRM_DEBUG_KMS("DFP6 disconnected\n");
2943 bios_0_scratch &= ~ATOM_S0_DFP6;
2944 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
2945 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
2946 }
2947 }
2934 2948
2935 if (rdev->family >= CHIP_R600) { 2949 if (rdev->family >= CHIP_R600) {
2936 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 2950 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
@@ -2951,6 +2965,9 @@ radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2951 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2965 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2952 uint32_t bios_3_scratch; 2966 uint32_t bios_3_scratch;
2953 2967
2968 if (ASIC_IS_DCE4(rdev))
2969 return;
2970
2954 if (rdev->family >= CHIP_R600) 2971 if (rdev->family >= CHIP_R600)
2955 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 2972 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2956 else 2973 else
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index 9d95792bea3..98724fcb008 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -58,7 +58,8 @@ static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
58 } 58 }
59 59
60 obj = (union acpi_object *)buffer.pointer; 60 obj = (union acpi_object *)buffer.pointer;
61 memcpy(bios+offset, obj->buffer.pointer, len); 61 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
62 len = obj->buffer.length;
62 kfree(buffer.pointer); 63 kfree(buffer.pointer);
63 return len; 64 return len;
64} 65}
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 229a20f10e2..501f4881e5a 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -120,7 +120,7 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
120 ret = radeon_atrm_get_bios_chunk(rdev->bios, 120 ret = radeon_atrm_get_bios_chunk(rdev->bios,
121 (i * ATRM_BIOS_PAGE), 121 (i * ATRM_BIOS_PAGE),
122 ATRM_BIOS_PAGE); 122 ATRM_BIOS_PAGE);
123 if (ret <= 0) 123 if (ret < ATRM_BIOS_PAGE)
124 break; 124 break;
125 } 125 }
126 126
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 0afb13bd8dc..49f7cb7e226 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -720,7 +720,7 @@ int radeon_device_init(struct radeon_device *rdev,
720 /* mutex initialization are all done here so we 720 /* mutex initialization are all done here so we
721 * can recall function without having locking issues */ 721 * can recall function without having locking issues */
722 radeon_mutex_init(&rdev->cs_mutex); 722 radeon_mutex_init(&rdev->cs_mutex);
723 mutex_init(&rdev->ib_pool.mutex); 723 radeon_mutex_init(&rdev->ib_pool.mutex);
724 for (i = 0; i < RADEON_NUM_RINGS; ++i) 724 for (i = 0; i < RADEON_NUM_RINGS; ++i)
725 mutex_init(&rdev->ring[i].mutex); 725 mutex_init(&rdev->ring[i].mutex);
726 mutex_init(&rdev->dc_hw_i2c_mutex); 726 mutex_init(&rdev->dc_hw_i2c_mutex);
@@ -883,6 +883,8 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
883 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 883 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
884 return 0; 884 return 0;
885 885
886 drm_kms_helper_poll_disable(dev);
887
886 /* turn off display hw */ 888 /* turn off display hw */
887 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 889 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
888 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 890 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
@@ -959,9 +961,11 @@ int radeon_resume_kms(struct drm_device *dev)
959 radeon_fbdev_set_suspend(rdev, 0); 961 radeon_fbdev_set_suspend(rdev, 0);
960 console_unlock(); 962 console_unlock();
961 963
962 /* init dig PHYs */ 964 /* init dig PHYs, disp eng pll */
963 if (rdev->is_atom_bios) 965 if (rdev->is_atom_bios) {
964 radeon_atom_encoder_init(rdev); 966 radeon_atom_encoder_init(rdev);
967 radeon_atom_dcpll_init(rdev);
968 }
965 /* reset hpd state */ 969 /* reset hpd state */
966 radeon_hpd_init(rdev); 970 radeon_hpd_init(rdev);
967 /* blat the mode back in */ 971 /* blat the mode back in */
@@ -970,6 +974,8 @@ int radeon_resume_kms(struct drm_device *dev)
970 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 974 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
971 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 975 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
972 } 976 }
977
978 drm_kms_helper_poll_enable(dev);
973 return 0; 979 return 0;
974} 980}
975 981
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index d3ffc18774a..8c49fef1ce7 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1305,9 +1305,11 @@ int radeon_modeset_init(struct radeon_device *rdev)
1305 return ret; 1305 return ret;
1306 } 1306 }
1307 1307
1308 /* init dig PHYs */ 1308 /* init dig PHYs, disp eng pll */
1309 if (rdev->is_atom_bios) 1309 if (rdev->is_atom_bios) {
1310 radeon_atom_encoder_init(rdev); 1310 radeon_atom_encoder_init(rdev);
1311 radeon_atom_dcpll_init(rdev);
1312 }
1311 1313
1312 /* initialize hpd */ 1314 /* initialize hpd */
1313 radeon_hpd_init(rdev); 1315 radeon_hpd_init(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 4b27efa4405..9419c51bcf5 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -202,6 +202,22 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder)
202 return NULL; 202 return NULL;
203} 203}
204 204
205struct drm_connector *
206radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
207{
208 struct drm_device *dev = encoder->dev;
209 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
210 struct drm_connector *connector;
211 struct radeon_connector *radeon_connector;
212
213 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
214 radeon_connector = to_radeon_connector(connector);
215 if (radeon_encoder->devices & radeon_connector->devices)
216 return connector;
217 }
218 return NULL;
219}
220
205struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder) 221struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder)
206{ 222{
207 struct drm_device *dev = encoder->dev; 223 struct drm_device *dev = encoder->dev;
@@ -288,3 +304,64 @@ void radeon_panel_mode_fixup(struct drm_encoder *encoder,
288 304
289} 305}
290 306
307bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
308 u32 pixel_clock)
309{
310 struct drm_device *dev = encoder->dev;
311 struct radeon_device *rdev = dev->dev_private;
312 struct drm_connector *connector;
313 struct radeon_connector *radeon_connector;
314 struct radeon_connector_atom_dig *dig_connector;
315
316 connector = radeon_get_connector_for_encoder(encoder);
317 /* if we don't have an active device yet, just use one of
318 * the connectors tied to the encoder.
319 */
320 if (!connector)
321 connector = radeon_get_connector_for_encoder_init(encoder);
322 radeon_connector = to_radeon_connector(connector);
323
324 switch (connector->connector_type) {
325 case DRM_MODE_CONNECTOR_DVII:
326 case DRM_MODE_CONNECTOR_HDMIB:
327 if (radeon_connector->use_digital) {
328 /* HDMI 1.3 supports up to 340 Mhz over single link */
329 if (ASIC_IS_DCE3(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) {
330 if (pixel_clock > 340000)
331 return true;
332 else
333 return false;
334 } else {
335 if (pixel_clock > 165000)
336 return true;
337 else
338 return false;
339 }
340 } else
341 return false;
342 case DRM_MODE_CONNECTOR_DVID:
343 case DRM_MODE_CONNECTOR_HDMIA:
344 case DRM_MODE_CONNECTOR_DisplayPort:
345 dig_connector = radeon_connector->con_priv;
346 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
347 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
348 return false;
349 else {
350 /* HDMI 1.3 supports up to 340 Mhz over single link */
351 if (ASIC_IS_DCE3(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) {
352 if (pixel_clock > 340000)
353 return true;
354 else
355 return false;
356 } else {
357 if (pixel_clock > 165000)
358 return true;
359 else
360 return false;
361 }
362 }
363 default:
364 return false;
365 }
366}
367
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 64ea3dd9e6f..4bd36a354fb 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -364,8 +364,10 @@ int radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
364 int not_processed = 0; 364 int not_processed = 0;
365 365
366 read_lock_irqsave(&rdev->fence_lock, irq_flags); 366 read_lock_irqsave(&rdev->fence_lock, irq_flags);
367 if (!rdev->fence_drv[ring].initialized) 367 if (!rdev->fence_drv[ring].initialized) {
368 read_unlock_irqrestore(&rdev->fence_lock, irq_flags);
368 return 0; 369 return 0;
370 }
369 371
370 if (!list_empty(&rdev->fence_drv[ring].emitted)) { 372 if (!list_empty(&rdev->fence_drv[ring].emitted)) {
371 struct list_head *ptr; 373 struct list_head *ptr;
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 7bb1b079f48..98a8ad68010 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -897,6 +897,7 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
897 i2c->rec = *rec; 897 i2c->rec = *rec;
898 i2c->adapter.owner = THIS_MODULE; 898 i2c->adapter.owner = THIS_MODULE;
899 i2c->adapter.class = I2C_CLASS_DDC; 899 i2c->adapter.class = I2C_CLASS_DDC;
900 i2c->adapter.dev.parent = &dev->pdev->dev;
900 i2c->dev = dev; 901 i2c->dev = dev;
901 i2c_set_adapdata(&i2c->adapter, i2c); 902 i2c_set_adapdata(&i2c->adapter, i2c);
902 if (rec->mm_i2c || 903 if (rec->mm_i2c ||
@@ -957,6 +958,7 @@ struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
957 i2c->rec = *rec; 958 i2c->rec = *rec;
958 i2c->adapter.owner = THIS_MODULE; 959 i2c->adapter.owner = THIS_MODULE;
959 i2c->adapter.class = I2C_CLASS_DDC; 960 i2c->adapter.class = I2C_CLASS_DDC;
961 i2c->adapter.dev.parent = &dev->pdev->dev;
960 i2c->dev = dev; 962 i2c->dev = dev;
961 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 963 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
962 "Radeon aux bus %s", name); 964 "Radeon aux bus %s", name);
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index be38921bf76..66d5fe1c817 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -138,6 +138,12 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
138 /* Dell RS690 only seems to work with MSIs. */ 138 /* Dell RS690 only seems to work with MSIs. */
139 if ((rdev->pdev->device == 0x791f) && 139 if ((rdev->pdev->device == 0x791f) &&
140 (rdev->pdev->subsystem_vendor == 0x1028) && 140 (rdev->pdev->subsystem_vendor == 0x1028) &&
141 (rdev->pdev->subsystem_device == 0x01fc))
142 return true;
143
144 /* Dell RS690 only seems to work with MSIs. */
145 if ((rdev->pdev->device == 0x791f) &&
146 (rdev->pdev->subsystem_vendor == 0x1028) &&
141 (rdev->pdev->subsystem_device == 0x01fd)) 147 (rdev->pdev->subsystem_device == 0x01fd))
142 return true; 148 return true;
143 149
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 08ff857c8fd..4330e325357 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -362,6 +362,7 @@ struct radeon_encoder_atom_dig {
362 struct backlight_device *bl_dev; 362 struct backlight_device *bl_dev;
363 int dpms_mode; 363 int dpms_mode;
364 uint8_t backlight_level; 364 uint8_t backlight_level;
365 int panel_mode;
365}; 366};
366 367
367struct radeon_encoder_atom_dac { 368struct radeon_encoder_atom_dac {
@@ -466,6 +467,10 @@ radeon_atombios_get_tv_info(struct radeon_device *rdev);
466 467
467extern struct drm_connector * 468extern struct drm_connector *
468radeon_get_connector_for_encoder(struct drm_encoder *encoder); 469radeon_get_connector_for_encoder(struct drm_encoder *encoder);
470extern struct drm_connector *
471radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
472extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
473 u32 pixel_clock);
469 474
470extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 475extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
471extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 476extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
@@ -482,8 +487,11 @@ extern void radeon_dp_link_train(struct drm_encoder *encoder,
482extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 487extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
483extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 488extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
484extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 489extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
490extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
491 struct drm_connector *connector);
485extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 492extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
486extern void radeon_atom_encoder_init(struct radeon_device *rdev); 493extern void radeon_atom_encoder_init(struct radeon_device *rdev);
494extern void radeon_atom_dcpll_init(struct radeon_device *rdev);
487extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 495extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
488 int action, uint8_t lane_num, 496 int action, uint8_t lane_num,
489 uint8_t lane_set); 497 uint8_t lane_set);
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index e8bc70933d1..30a4c5014c8 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -109,12 +109,12 @@ int radeon_ib_get(struct radeon_device *rdev, int ring,
109 return r; 109 return r;
110 } 110 }
111 111
112 mutex_lock(&rdev->ib_pool.mutex); 112 radeon_mutex_lock(&rdev->ib_pool.mutex);
113 idx = rdev->ib_pool.head_id; 113 idx = rdev->ib_pool.head_id;
114retry: 114retry:
115 if (cretry > 5) { 115 if (cretry > 5) {
116 dev_err(rdev->dev, "failed to get an ib after 5 retry\n"); 116 dev_err(rdev->dev, "failed to get an ib after 5 retry\n");
117 mutex_unlock(&rdev->ib_pool.mutex); 117 radeon_mutex_unlock(&rdev->ib_pool.mutex);
118 radeon_fence_unref(&fence); 118 radeon_fence_unref(&fence);
119 return -ENOMEM; 119 return -ENOMEM;
120 } 120 }
@@ -139,7 +139,7 @@ retry:
139 */ 139 */
140 rdev->ib_pool.head_id = (1 + idx); 140 rdev->ib_pool.head_id = (1 + idx);
141 rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1); 141 rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1);
142 mutex_unlock(&rdev->ib_pool.mutex); 142 radeon_mutex_unlock(&rdev->ib_pool.mutex);
143 return 0; 143 return 0;
144 } 144 }
145 } 145 }
@@ -158,7 +158,7 @@ retry:
158 } 158 }
159 idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1); 159 idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
160 } 160 }
161 mutex_unlock(&rdev->ib_pool.mutex); 161 radeon_mutex_unlock(&rdev->ib_pool.mutex);
162 radeon_fence_unref(&fence); 162 radeon_fence_unref(&fence);
163 return r; 163 return r;
164} 164}
@@ -171,12 +171,12 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
171 if (tmp == NULL) { 171 if (tmp == NULL) {
172 return; 172 return;
173 } 173 }
174 mutex_lock(&rdev->ib_pool.mutex); 174 radeon_mutex_lock(&rdev->ib_pool.mutex);
175 if (tmp->fence && !tmp->fence->emitted) { 175 if (tmp->fence && !tmp->fence->emitted) {
176 radeon_sa_bo_free(rdev, &tmp->sa_bo); 176 radeon_sa_bo_free(rdev, &tmp->sa_bo);
177 radeon_fence_unref(&tmp->fence); 177 radeon_fence_unref(&tmp->fence);
178 } 178 }
179 mutex_unlock(&rdev->ib_pool.mutex); 179 radeon_mutex_unlock(&rdev->ib_pool.mutex);
180} 180}
181 181
182int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) 182int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
@@ -204,22 +204,25 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
204 204
205int radeon_ib_pool_init(struct radeon_device *rdev) 205int radeon_ib_pool_init(struct radeon_device *rdev)
206{ 206{
207 struct radeon_sa_manager tmp;
207 int i, r; 208 int i, r;
208 209
209 mutex_lock(&rdev->ib_pool.mutex); 210 r = radeon_sa_bo_manager_init(rdev, &tmp,
210 if (rdev->ib_pool.ready) {
211 mutex_unlock(&rdev->ib_pool.mutex);
212 return 0;
213 }
214
215 r = radeon_sa_bo_manager_init(rdev, &rdev->ib_pool.sa_manager,
216 RADEON_IB_POOL_SIZE*64*1024, 211 RADEON_IB_POOL_SIZE*64*1024,
217 RADEON_GEM_DOMAIN_GTT); 212 RADEON_GEM_DOMAIN_GTT);
218 if (r) { 213 if (r) {
219 mutex_unlock(&rdev->ib_pool.mutex);
220 return r; 214 return r;
221 } 215 }
222 216
217 radeon_mutex_lock(&rdev->ib_pool.mutex);
218 if (rdev->ib_pool.ready) {
219 radeon_mutex_unlock(&rdev->ib_pool.mutex);
220 radeon_sa_bo_manager_fini(rdev, &tmp);
221 return 0;
222 }
223
224 rdev->ib_pool.sa_manager = tmp;
225 INIT_LIST_HEAD(&rdev->ib_pool.sa_manager.sa_bo);
223 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { 226 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
224 rdev->ib_pool.ibs[i].fence = NULL; 227 rdev->ib_pool.ibs[i].fence = NULL;
225 rdev->ib_pool.ibs[i].idx = i; 228 rdev->ib_pool.ibs[i].idx = i;
@@ -236,7 +239,7 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
236 if (radeon_debugfs_ring_init(rdev)) { 239 if (radeon_debugfs_ring_init(rdev)) {
237 DRM_ERROR("Failed to register debugfs file for rings !\n"); 240 DRM_ERROR("Failed to register debugfs file for rings !\n");
238 } 241 }
239 mutex_unlock(&rdev->ib_pool.mutex); 242 radeon_mutex_unlock(&rdev->ib_pool.mutex);
240 return 0; 243 return 0;
241} 244}
242 245
@@ -244,7 +247,7 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
244{ 247{
245 unsigned i; 248 unsigned i;
246 249
247 mutex_lock(&rdev->ib_pool.mutex); 250 radeon_mutex_lock(&rdev->ib_pool.mutex);
248 if (rdev->ib_pool.ready) { 251 if (rdev->ib_pool.ready) {
249 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { 252 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
250 radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo); 253 radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo);
@@ -253,7 +256,7 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
253 radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager); 256 radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager);
254 rdev->ib_pool.ready = false; 257 rdev->ib_pool.ready = false;
255 } 258 }
256 mutex_unlock(&rdev->ib_pool.mutex); 259 radeon_mutex_unlock(&rdev->ib_pool.mutex);
257} 260}
258 261
259int radeon_ib_pool_start(struct radeon_device *rdev) 262int radeon_ib_pool_start(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index ec46eb45e34..c05865e5521 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -684,9 +684,7 @@ int rs600_irq_process(struct radeon_device *rdev)
684 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 684 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
685 break; 685 break;
686 default: 686 default:
687 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 687 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
688 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
689 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
690 break; 688 break;
691 } 689 }
692 } 690 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 00:51:24 -0400