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authorAdam Buchbinder <adam.buchbinder@gmail.com>2009-12-11 16:35:39 -0500
committerJiri Kosina <jkosina@suse.cz>2010-02-04 05:55:45 -0500
commitc41b20e721ea4f6f20f66a66e7f0c3c97a2ca9c2 (patch)
tree92cd1b2b1cdb871530bb07bbbcbfeaffe1170830 /drivers/gpu/drm/radeon/radeon_state.c
parenta089377f29d3af0f62f3bdc6db0c5042513fc3f3 (diff)
Fix misspellings of "truly" in comments.
Some comments misspell "truly"; this fixes them. No code changes. Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_state.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 067167cb39c..1982a87386a 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1065,7 +1065,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
1065 /* judging by the first tile offset needed, could possibly 1065 /* judging by the first tile offset needed, could possibly
1066 directly address/clear 4x4 tiles instead of 8x2 * 4x4 1066 directly address/clear 4x4 tiles instead of 8x2 * 4x4
1067 macro tiles, though would still need clear mask for 1067 macro tiles, though would still need clear mask for
1068 right/bottom if truely 4x4 granularity is desired ? */ 1068 right/bottom if truly 4x4 granularity is desired ? */
1069 OUT_RING(tileoffset * 16); 1069 OUT_RING(tileoffset * 16);
1070 /* the number of tiles to clear */ 1070 /* the number of tiles to clear */
1071 OUT_RING(nrtilesx + 1); 1071 OUT_RING(nrtilesx + 1);