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authorAlex Deucher <alexdeucher@gmail.com>2010-02-02 12:05:01 -0500
committerDave Airlie <airlied@redhat.com>2010-02-08 18:31:21 -0500
commit7c27f87d2bde885e9bcda74c208a7aae8bef8e76 (patch)
tree5490fe9d6ed83bc36c2ac3da7dedee4de3730806 /drivers/gpu/drm/radeon/radeon_mode.h
parent4612dc97991a09e1a9e4d5d981e16589d7cb150c (diff)
drm/radeon/kms: rework pll algo selection
Rework the pll algo selection so that the pll algo in use can be selected more easily. This allows us to select different pll divider selection algos for specific monitors that work better with one algo or the other. This is needed for the next patch which adds an LVDS pll quirk for a specific notebook. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h18
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 71439ba2fee..d1e859d1dbf 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -113,6 +113,7 @@ struct radeon_tmds_pll {
113 113
114#define RADEON_MAX_BIOS_CONNECTOR 16 114#define RADEON_MAX_BIOS_CONNECTOR 16
115 115
116/* pll flags */
116#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 117#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
117#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 118#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
118#define RADEON_PLL_USE_REF_DIV (1 << 2) 119#define RADEON_PLL_USE_REF_DIV (1 << 2)
@@ -127,6 +128,12 @@ struct radeon_tmds_pll {
127#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 128#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
128#define RADEON_PLL_USE_POST_DIV (1 << 12) 129#define RADEON_PLL_USE_POST_DIV (1 << 12)
129 130
131/* pll algo */
132enum radeon_pll_algo {
133 PLL_ALGO_LEGACY,
134 PLL_ALGO_AVIVO
135};
136
130struct radeon_pll { 137struct radeon_pll {
131 /* reference frequency */ 138 /* reference frequency */
132 uint32_t reference_freq; 139 uint32_t reference_freq;
@@ -157,6 +164,8 @@ struct radeon_pll {
157 164
158 /* pll id */ 165 /* pll id */
159 uint32_t id; 166 uint32_t id;
167 /* pll algo */
168 enum radeon_pll_algo algo;
160}; 169};
161 170
162struct i2c_algo_radeon_data { 171struct i2c_algo_radeon_data {
@@ -309,6 +318,7 @@ struct radeon_encoder_atom_dig {
309 /* atom lvds */ 318 /* atom lvds */
310 uint32_t lvds_misc; 319 uint32_t lvds_misc;
311 uint16_t panel_pwr_delay; 320 uint16_t panel_pwr_delay;
321 enum radeon_pll_algo pll_algo;
312 struct radeon_atom_ss *ss; 322 struct radeon_atom_ss *ss;
313 /* panel mode */ 323 /* panel mode */
314 struct drm_display_mode native_mode; 324 struct drm_display_mode native_mode;
@@ -439,14 +449,6 @@ extern void radeon_compute_pll(struct radeon_pll *pll,
439 uint32_t *ref_div_p, 449 uint32_t *ref_div_p,
440 uint32_t *post_div_p); 450 uint32_t *post_div_p);
441 451
442extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
443 uint64_t freq,
444 uint32_t *dot_clock_p,
445 uint32_t *fb_div_p,
446 uint32_t *frac_fb_div_p,
447 uint32_t *ref_div_p,
448 uint32_t *post_div_p);
449
450extern void radeon_setup_encoder_clones(struct drm_device *dev); 452extern void radeon_setup_encoder_clones(struct drm_device *dev);
451 453
452struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 454struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);