diff options
author | Dave Airlie <airlied@redhat.com> | 2010-02-24 22:44:04 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-02-26 01:23:23 -0500 |
commit | eb6b6d7cdd5548fa03a919d14615195600013be2 (patch) | |
tree | c499472ef28a903f94b09da9a24f66b021412813 /drivers/gpu/drm/radeon/radeon_cursor.c | |
parent | 30d6c72c4a760cfc9069ee100786e4d6cf6de59d (diff) | |
parent | 383be5d1789d9a7a2e77dca1cb0aca89507d069e (diff) |
Merge remote branch 'korg/drm-radeon-testing' into drm-next-stage
* korg/drm-radeon-testing: (62 commits)
drm/radeon/kms: update new pll algo
drm/radeon/kms: add support for square microtiles on r3xx-r5xx
drm/radeon/kms: force pinning buffer into visible VRAM
drm/radeon/kms/evergreen: fix typo in cursor code
drm/radeon/kms: implement reading active PCIE lanes on R600+
drm/radeon/kms: for downclocking non-mobility check PERFORMANCE state
drm/radeon/kms: simplify storing current and requested PM mode
drm/radeon: fixes for r6xx/r7xx gfx init
drm/radeon/rv740: fix backend setup
drm/radeon/kms: fix R3XX/R4XX memory controller initialization
[rfc] drm/radeon/kms: pm debugging check for vbl.
drm/radeon: Fix memory allocation failures in the preKMS command stream checking.
drm: Add generic multipart buffer.
drm/radeon/kms: simplify memory controller setup V2
drm/radeon: Add asic hook for dma copy to r200 cards.
drm/radeon/kms: Create asic structure for r300 pcie cards.
drm/radeon/kms: remove unused r600_gart_clear_page
drm/radeon/kms: remove HDP flushes from fence emit (v2)
drm/radeon/kms: add LVDS pll quirk for Dell Studio 15
drm/radeon/kms: simplify picking power state
...
Conflicts:
drivers/gpu/drm/radeon/atom.c
drivers/gpu/drm/radeon/atombios.h
drivers/gpu/drm/radeon/atombios_dp.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600_audio.c
drivers/gpu/drm/radeon/r600_cp.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_connectors.c
drivers/gpu/drm/radeon/radeon_ring.c
drivers/gpu/drm/radeon/rv770.c
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_cursor.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_cursor.c | 42 |
1 files changed, 36 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c index 6f4a5534a99..b7023fff89e 100644 --- a/drivers/gpu/drm/radeon/radeon_cursor.c +++ b/drivers/gpu/drm/radeon/radeon_cursor.c | |||
@@ -36,7 +36,14 @@ static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) | |||
36 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 36 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
37 | uint32_t cur_lock; | 37 | uint32_t cur_lock; |
38 | 38 | ||
39 | if (ASIC_IS_AVIVO(rdev)) { | 39 | if (ASIC_IS_DCE4(rdev)) { |
40 | cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); | ||
41 | if (lock) | ||
42 | cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; | ||
43 | else | ||
44 | cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; | ||
45 | WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); | ||
46 | } else if (ASIC_IS_AVIVO(rdev)) { | ||
40 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); | 47 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
41 | if (lock) | 48 | if (lock) |
42 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; | 49 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
@@ -58,7 +65,10 @@ static void radeon_hide_cursor(struct drm_crtc *crtc) | |||
58 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 65 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
59 | struct radeon_device *rdev = crtc->dev->dev_private; | 66 | struct radeon_device *rdev = crtc->dev->dev_private; |
60 | 67 | ||
61 | if (ASIC_IS_AVIVO(rdev)) { | 68 | if (ASIC_IS_DCE4(rdev)) { |
69 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); | ||
70 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); | ||
71 | } else if (ASIC_IS_AVIVO(rdev)) { | ||
62 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); | 72 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
63 | WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); | 73 | WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
64 | } else { | 74 | } else { |
@@ -81,10 +91,14 @@ static void radeon_show_cursor(struct drm_crtc *crtc) | |||
81 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 91 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
82 | struct radeon_device *rdev = crtc->dev->dev_private; | 92 | struct radeon_device *rdev = crtc->dev->dev_private; |
83 | 93 | ||
84 | if (ASIC_IS_AVIVO(rdev)) { | 94 | if (ASIC_IS_DCE4(rdev)) { |
95 | WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); | ||
96 | WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | | ||
97 | EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); | ||
98 | } else if (ASIC_IS_AVIVO(rdev)) { | ||
85 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); | 99 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
86 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | | 100 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
87 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); | 101 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
88 | } else { | 102 | } else { |
89 | switch (radeon_crtc->crtc_id) { | 103 | switch (radeon_crtc->crtc_id) { |
90 | case 0: | 104 | case 0: |
@@ -109,7 +123,10 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, | |||
109 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | 123 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
110 | struct radeon_device *rdev = crtc->dev->dev_private; | 124 | struct radeon_device *rdev = crtc->dev->dev_private; |
111 | 125 | ||
112 | if (ASIC_IS_AVIVO(rdev)) { | 126 | if (ASIC_IS_DCE4(rdev)) { |
127 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); | ||
128 | WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); | ||
129 | } else if (ASIC_IS_AVIVO(rdev)) { | ||
113 | if (rdev->family >= CHIP_RV770) { | 130 | if (rdev->family >= CHIP_RV770) { |
114 | if (radeon_crtc->crtc_id) | 131 | if (radeon_crtc->crtc_id) |
115 | WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); | 132 | WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); |
@@ -197,7 +214,20 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, | |||
197 | yorigin = CURSOR_HEIGHT - 1; | 214 | yorigin = CURSOR_HEIGHT - 1; |
198 | 215 | ||
199 | radeon_lock_cursor(crtc, true); | 216 | radeon_lock_cursor(crtc, true); |
200 | if (ASIC_IS_AVIVO(rdev)) { | 217 | if (ASIC_IS_DCE4(rdev)) { |
218 | /* cursors are offset into the total surface */ | ||
219 | x += crtc->x; | ||
220 | y += crtc->y; | ||
221 | DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); | ||
222 | |||
223 | /* XXX: check if evergreen has the same issues as avivo chips */ | ||
224 | WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, | ||
225 | ((xorigin ? 0 : x) << 16) | | ||
226 | (yorigin ? 0 : y)); | ||
227 | WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); | ||
228 | WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, | ||
229 | ((radeon_crtc->cursor_width - 1) << 16) | (radeon_crtc->cursor_height - 1)); | ||
230 | } else if (ASIC_IS_AVIVO(rdev)) { | ||
201 | int w = radeon_crtc->cursor_width; | 231 | int w = radeon_crtc->cursor_width; |
202 | int i = 0; | 232 | int i = 0; |
203 | struct drm_crtc *crtc_p; | 233 | struct drm_crtc *crtc_p; |