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authorDave Airlie <airlied@redhat.com>2009-02-19 22:28:59 -0500
committerDave Airlie <airlied@redhat.com>2009-03-13 00:24:06 -0400
commitdd8d7cb49e6e61da96ca44174b063081892c4dc6 (patch)
treea518dab29f159697d4df52696c8f16acee52018c /drivers/gpu/drm/radeon/radeon_cp.c
parent4247ca942a16745da3d09c58996b276d02655a72 (diff)
drm/radeon: split busmaster enable out to a separate function
this is just a code cleanup from the kms tree. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_cp.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c35
1 files changed, 20 insertions, 15 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 78a058fc039..8338353e505 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -191,6 +191,25 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
191 } 191 }
192} 192}
193 193
194static void radeon_enable_bm(struct drm_radeon_private *dev_priv)
195{
196 u32 tmp;
197 /* Turn on bus mastering */
198 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
199 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
200 /* rs600/rs690/rs740 */
201 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
202 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
203 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
204 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
205 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
206 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
207 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
208 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
209 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
210 } /* PCIE cards appears to not need this */
211}
212
194static int RADEON_READ_PLL(struct drm_device * dev, int addr) 213static int RADEON_READ_PLL(struct drm_device * dev, int addr)
195{ 214{
196 drm_radeon_private_t *dev_priv = dev->dev_private; 215 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -608,7 +627,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
608{ 627{
609 struct drm_radeon_master_private *master_priv; 628 struct drm_radeon_master_private *master_priv;
610 u32 ring_start, cur_read_ptr; 629 u32 ring_start, cur_read_ptr;
611 u32 tmp;
612 630
613 /* Initialize the memory controller. With new memory map, the fb location 631 /* Initialize the memory controller. With new memory map, the fb location
614 * is not changed, it should have been properly initialized already. Part 632 * is not changed, it should have been properly initialized already. Part
@@ -690,20 +708,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
690 708
691 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 709 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
692 710
693 /* Turn on bus mastering */ 711 radeon_enable_bm(dev_priv);
694 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
695 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
696 /* rs600/rs690/rs740 */
697 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
698 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
699 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
700 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
701 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
702 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
703 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
704 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
705 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
706 } /* PCIE cards appears to not need this */
707 712
708 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0); 713 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
709 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0); 714 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);