diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2011-01-06 21:19:15 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-01-06 23:11:22 -0500 |
commit | f82b3ddc5fac044a28ab841bfd4ae48e2e43a21b (patch) | |
tree | dd435132ebe52bf55f68234b689e73c3f7a32547 /drivers/gpu/drm/radeon/radeon_atombios.c | |
parent | 881dd74ea731067f8fc81608e3a8914fdd66bc6d (diff) |
drm/radeon/kms: DCE5 atom SetPixelClock updates
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_atombios.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_atombios.c | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index e4f7e3e82a5..11573d085e6 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
@@ -1086,6 +1086,7 @@ union firmware_info { | |||
1086 | ATOM_FIRMWARE_INFO_V1_3 info_13; | 1086 | ATOM_FIRMWARE_INFO_V1_3 info_13; |
1087 | ATOM_FIRMWARE_INFO_V1_4 info_14; | 1087 | ATOM_FIRMWARE_INFO_V1_4 info_14; |
1088 | ATOM_FIRMWARE_INFO_V2_1 info_21; | 1088 | ATOM_FIRMWARE_INFO_V2_1 info_21; |
1089 | ATOM_FIRMWARE_INFO_V2_2 info_22; | ||
1089 | }; | 1090 | }; |
1090 | 1091 | ||
1091 | bool radeon_atom_get_clock_info(struct drm_device *dev) | 1092 | bool radeon_atom_get_clock_info(struct drm_device *dev) |
@@ -1160,8 +1161,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) | |||
1160 | *p2pll = *p1pll; | 1161 | *p2pll = *p1pll; |
1161 | 1162 | ||
1162 | /* system clock */ | 1163 | /* system clock */ |
1163 | spll->reference_freq = | 1164 | if (ASIC_IS_DCE4(rdev)) |
1164 | le16_to_cpu(firmware_info->info.usReferenceClock); | 1165 | spll->reference_freq = |
1166 | le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); | ||
1167 | else | ||
1168 | spll->reference_freq = | ||
1169 | le16_to_cpu(firmware_info->info.usReferenceClock); | ||
1165 | spll->reference_div = 0; | 1170 | spll->reference_div = 0; |
1166 | 1171 | ||
1167 | spll->pll_out_min = | 1172 | spll->pll_out_min = |
@@ -1183,8 +1188,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) | |||
1183 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); | 1188 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); |
1184 | 1189 | ||
1185 | /* memory clock */ | 1190 | /* memory clock */ |
1186 | mpll->reference_freq = | 1191 | if (ASIC_IS_DCE4(rdev)) |
1187 | le16_to_cpu(firmware_info->info.usReferenceClock); | 1192 | mpll->reference_freq = |
1193 | le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); | ||
1194 | else | ||
1195 | mpll->reference_freq = | ||
1196 | le16_to_cpu(firmware_info->info.usReferenceClock); | ||
1188 | mpll->reference_div = 0; | 1197 | mpll->reference_div = 0; |
1189 | 1198 | ||
1190 | mpll->pll_out_min = | 1199 | mpll->pll_out_min = |
@@ -1213,8 +1222,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) | |||
1213 | if (ASIC_IS_DCE4(rdev)) { | 1222 | if (ASIC_IS_DCE4(rdev)) { |
1214 | rdev->clock.default_dispclk = | 1223 | rdev->clock.default_dispclk = |
1215 | le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); | 1224 | le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); |
1216 | if (rdev->clock.default_dispclk == 0) | 1225 | if (rdev->clock.default_dispclk == 0) { |
1217 | rdev->clock.default_dispclk = 60000; /* 600 Mhz */ | 1226 | if (ASIC_IS_DCE5(rdev)) |
1227 | rdev->clock.default_dispclk = 54000; /* 540 Mhz */ | ||
1228 | else | ||
1229 | rdev->clock.default_dispclk = 60000; /* 600 Mhz */ | ||
1230 | } | ||
1218 | rdev->clock.dp_extclk = | 1231 | rdev->clock.dp_extclk = |
1219 | le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); | 1232 | le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); |
1220 | } | 1233 | } |