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authorJerome Glisse <jglisse@redhat.com>2009-06-05 08:42:42 -0400
committerDave Airlie <airlied@redhat.com>2009-06-14 22:01:53 -0400
commit771fe6b912fca54f03e8a72eb63058b582775362 (patch)
tree58aa5469ba8058c2b564d50807395ad6cd7bd7e4 /drivers/gpu/drm/radeon/radeon_atombios.c
parentba4e7d973dd09b66912ac4c0856add8b0703a997 (diff)
drm/radeon: introduce kernel modesetting for radeon hardware
Add kernel modesetting support to radeon driver, use the ttm memory manager to manage memory and DRM/GEM to provide userspace API. In order to avoid backward compatibility issue and to allow clean design and code the radeon kernel modesetting use different code path than old radeon/drm driver. When kernel modesetting is enabled the IOCTL of radeon/drm driver are considered as invalid and an error message is printed in the log and they return failure. KMS enabled userspace will use new API to talk with the radeon/drm driver. The new API provide functions to create/destroy/share/mmap buffer object which are then managed by the kernel memory manager (here TTM). In order to submit command to the GPU the userspace provide a buffer holding the command stream, along this buffer userspace have to provide a list of buffer object used by the command stream. The kernel radeon driver will then place buffer in GPU accessible memory and will update command stream to reflect the position of the different buffers. The kernel will also perform security check on command stream provided by the user, we want to catch and forbid any illegal use of the GPU such as DMA into random system memory or into memory not owned by the process supplying the command stream. This part of the code is still incomplete and this why we propose that patch as a staging driver addition, future security might forbid current experimental userspace to run. This code support the following hardware : R1XX,R2XX,R3XX,R4XX,R5XX (radeon up to X1950). Works is underway to provide support for R6XX, R7XX and newer hardware (radeon from HD2XXX to HD4XXX). Authors: Jerome Glisse <jglisse@redhat.com> Dave Airlie <airlied@redhat.com> Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_atombios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c1226
1 files changed, 1226 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
new file mode 100644
index 00000000000..98904de6387
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -0,0 +1,1226 @@
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info);
50
51/* from radeon_legacy_encoder.c */
52extern void
53radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
54 uint32_t supported_device);
55
56union atom_supported_devices {
57 struct _ATOM_SUPPORTED_DEVICES_INFO info;
58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
60};
61
62static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
63 *dev, uint8_t id)
64{
65 struct radeon_device *rdev = dev->dev_private;
66 struct atom_context *ctx = rdev->mode_info.atom_context;
67 ATOM_GPIO_I2C_ASSIGMENT gpio;
68 struct radeon_i2c_bus_rec i2c;
69 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
70 struct _ATOM_GPIO_I2C_INFO *i2c_info;
71 uint16_t data_offset;
72
73 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
74 i2c.valid = false;
75
76 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
77
78 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
79
80 gpio = i2c_info->asGPIO_Info[id];
81
82 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
83 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
84 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
85 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
86 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
87 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
88 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
89 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
90 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
91 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
92 i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
93 i2c.put_data_mask = (1 << gpio.ucDataEnShift);
94 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
95 i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
96 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
97 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
98 i2c.valid = true;
99
100 return i2c;
101}
102
103static bool radeon_atom_apply_quirks(struct drm_device *dev,
104 uint32_t supported_device,
105 int *connector_type,
106 struct radeon_i2c_bus_rec *i2c_bus)
107{
108
109 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
110 if ((dev->pdev->device == 0x791e) &&
111 (dev->pdev->subsystem_vendor == 0x1043) &&
112 (dev->pdev->subsystem_device == 0x826d)) {
113 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
114 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
115 *connector_type = DRM_MODE_CONNECTOR_DVID;
116 }
117
118 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
119 if ((dev->pdev->device == 0x7941) &&
120 (dev->pdev->subsystem_vendor == 0x147b) &&
121 (dev->pdev->subsystem_device == 0x2412)) {
122 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
123 return false;
124 }
125
126 /* Falcon NW laptop lists vga ddc line for LVDS */
127 if ((dev->pdev->device == 0x5653) &&
128 (dev->pdev->subsystem_vendor == 0x1462) &&
129 (dev->pdev->subsystem_device == 0x0291)) {
130 if (*connector_type == DRM_MODE_CONNECTOR_LVDS)
131 i2c_bus->valid = false;
132 }
133
134 /* Funky macbooks */
135 if ((dev->pdev->device == 0x71C5) &&
136 (dev->pdev->subsystem_vendor == 0x106b) &&
137 (dev->pdev->subsystem_device == 0x0080)) {
138 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
139 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
140 return false;
141 }
142
143 /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */
144 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
145 (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
146 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
147 return false;
148 }
149 }
150
151 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
152 if ((dev->pdev->device == 0x9598) &&
153 (dev->pdev->subsystem_vendor == 0x1043) &&
154 (dev->pdev->subsystem_device == 0x01da)) {
155 if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) {
156 *connector_type = DRM_MODE_CONNECTOR_DVID;
157 }
158 }
159
160 return true;
161}
162
163const int supported_devices_connector_convert[] = {
164 DRM_MODE_CONNECTOR_Unknown,
165 DRM_MODE_CONNECTOR_VGA,
166 DRM_MODE_CONNECTOR_DVII,
167 DRM_MODE_CONNECTOR_DVID,
168 DRM_MODE_CONNECTOR_DVIA,
169 DRM_MODE_CONNECTOR_SVIDEO,
170 DRM_MODE_CONNECTOR_Composite,
171 DRM_MODE_CONNECTOR_LVDS,
172 DRM_MODE_CONNECTOR_Unknown,
173 DRM_MODE_CONNECTOR_Unknown,
174 DRM_MODE_CONNECTOR_HDMIA,
175 DRM_MODE_CONNECTOR_HDMIB,
176 DRM_MODE_CONNECTOR_Unknown,
177 DRM_MODE_CONNECTOR_Unknown,
178 DRM_MODE_CONNECTOR_9PinDIN,
179 DRM_MODE_CONNECTOR_DisplayPort
180};
181
182const int object_connector_convert[] = {
183 DRM_MODE_CONNECTOR_Unknown,
184 DRM_MODE_CONNECTOR_DVII,
185 DRM_MODE_CONNECTOR_DVII,
186 DRM_MODE_CONNECTOR_DVID,
187 DRM_MODE_CONNECTOR_DVID,
188 DRM_MODE_CONNECTOR_VGA,
189 DRM_MODE_CONNECTOR_Composite,
190 DRM_MODE_CONNECTOR_SVIDEO,
191 DRM_MODE_CONNECTOR_Unknown,
192 DRM_MODE_CONNECTOR_9PinDIN,
193 DRM_MODE_CONNECTOR_Unknown,
194 DRM_MODE_CONNECTOR_HDMIA,
195 DRM_MODE_CONNECTOR_HDMIB,
196 DRM_MODE_CONNECTOR_HDMIB,
197 DRM_MODE_CONNECTOR_LVDS,
198 DRM_MODE_CONNECTOR_9PinDIN,
199 DRM_MODE_CONNECTOR_Unknown,
200 DRM_MODE_CONNECTOR_Unknown,
201 DRM_MODE_CONNECTOR_Unknown,
202 DRM_MODE_CONNECTOR_DisplayPort
203};
204
205bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
206{
207 struct radeon_device *rdev = dev->dev_private;
208 struct radeon_mode_info *mode_info = &rdev->mode_info;
209 struct atom_context *ctx = mode_info->atom_context;
210 int index = GetIndexIntoMasterTable(DATA, Object_Header);
211 uint16_t size, data_offset;
212 uint8_t frev, crev, line_mux = 0;
213 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
214 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
215 ATOM_OBJECT_HEADER *obj_header;
216 int i, j, path_size, device_support;
217 int connector_type;
218 uint16_t igp_lane_info;
219 bool linkb;
220 struct radeon_i2c_bus_rec ddc_bus;
221
222 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
223
224 if (data_offset == 0)
225 return false;
226
227 if (crev < 2)
228 return false;
229
230 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
231 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
232 (ctx->bios + data_offset +
233 le16_to_cpu(obj_header->usDisplayPathTableOffset));
234 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
235 (ctx->bios + data_offset +
236 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
237 device_support = le16_to_cpu(obj_header->usDeviceSupport);
238
239 path_size = 0;
240 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
241 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
242 ATOM_DISPLAY_OBJECT_PATH *path;
243 addr += path_size;
244 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
245 path_size += le16_to_cpu(path->usSize);
246 linkb = false;
247
248 if (device_support & le16_to_cpu(path->usDeviceTag)) {
249 uint8_t con_obj_id, con_obj_num, con_obj_type;
250
251 con_obj_id =
252 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
253 >> OBJECT_ID_SHIFT;
254 con_obj_num =
255 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
256 >> ENUM_ID_SHIFT;
257 con_obj_type =
258 (le16_to_cpu(path->usConnObjectId) &
259 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
260
261 if ((le16_to_cpu(path->usDeviceTag) ==
262 ATOM_DEVICE_TV1_SUPPORT)
263 || (le16_to_cpu(path->usDeviceTag) ==
264 ATOM_DEVICE_TV2_SUPPORT)
265 || (le16_to_cpu(path->usDeviceTag) ==
266 ATOM_DEVICE_CV_SUPPORT))
267 continue;
268
269 if ((rdev->family == CHIP_RS780) &&
270 (con_obj_id ==
271 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
272 uint16_t igp_offset = 0;
273 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
274
275 index =
276 GetIndexIntoMasterTable(DATA,
277 IntegratedSystemInfo);
278
279 atom_parse_data_header(ctx, index, &size, &frev,
280 &crev, &igp_offset);
281
282 if (crev >= 2) {
283 igp_obj =
284 (ATOM_INTEGRATED_SYSTEM_INFO_V2
285 *) (ctx->bios + igp_offset);
286
287 if (igp_obj) {
288 uint32_t slot_config, ct;
289
290 if (con_obj_num == 1)
291 slot_config =
292 igp_obj->
293 ulDDISlot1Config;
294 else
295 slot_config =
296 igp_obj->
297 ulDDISlot2Config;
298
299 ct = (slot_config >> 16) & 0xff;
300 connector_type =
301 object_connector_convert
302 [ct];
303 igp_lane_info =
304 slot_config & 0xffff;
305 } else
306 continue;
307 } else
308 continue;
309 } else {
310 igp_lane_info = 0;
311 connector_type =
312 object_connector_convert[con_obj_id];
313 }
314
315 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
316 continue;
317
318 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
319 j++) {
320 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
321
322 enc_obj_id =
323 (le16_to_cpu(path->usGraphicObjIds[j]) &
324 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
325 enc_obj_num =
326 (le16_to_cpu(path->usGraphicObjIds[j]) &
327 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
328 enc_obj_type =
329 (le16_to_cpu(path->usGraphicObjIds[j]) &
330 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
331
332 /* FIXME: add support for router objects */
333 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
334 if (enc_obj_num == 2)
335 linkb = true;
336 else
337 linkb = false;
338
339 radeon_add_atom_encoder(dev,
340 enc_obj_id,
341 le16_to_cpu
342 (path->
343 usDeviceTag));
344
345 }
346 }
347
348 /* look up gpio for ddc */
349 if ((le16_to_cpu(path->usDeviceTag) &
350 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
351 == 0) {
352 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
353 if (le16_to_cpu(path->usConnObjectId) ==
354 le16_to_cpu(con_obj->asObjects[j].
355 usObjectID)) {
356 ATOM_COMMON_RECORD_HEADER
357 *record =
358 (ATOM_COMMON_RECORD_HEADER
359 *)
360 (ctx->bios + data_offset +
361 le16_to_cpu(con_obj->
362 asObjects[j].
363 usRecordOffset));
364 ATOM_I2C_RECORD *i2c_record;
365
366 while (record->ucRecordType > 0
367 && record->
368 ucRecordType <=
369 ATOM_MAX_OBJECT_RECORD_NUMBER) {
370 DRM_ERROR
371 ("record type %d\n",
372 record->
373 ucRecordType);
374 switch (record->
375 ucRecordType) {
376 case ATOM_I2C_RECORD_TYPE:
377 i2c_record =
378 (ATOM_I2C_RECORD
379 *) record;
380 line_mux =
381 i2c_record->
382 sucI2cId.
383 bfI2C_LineMux;
384 break;
385 }
386 record =
387 (ATOM_COMMON_RECORD_HEADER
388 *) ((char *)record
389 +
390 record->
391 ucRecordSize);
392 }
393 break;
394 }
395 }
396 } else
397 line_mux = 0;
398
399 if ((le16_to_cpu(path->usDeviceTag) ==
400 ATOM_DEVICE_TV1_SUPPORT)
401 || (le16_to_cpu(path->usDeviceTag) ==
402 ATOM_DEVICE_TV2_SUPPORT)
403 || (le16_to_cpu(path->usDeviceTag) ==
404 ATOM_DEVICE_CV_SUPPORT))
405 ddc_bus.valid = false;
406 else
407 ddc_bus = radeon_lookup_gpio(dev, line_mux);
408
409 radeon_add_atom_connector(dev,
410 le16_to_cpu(path->
411 usConnObjectId),
412 le16_to_cpu(path->
413 usDeviceTag),
414 connector_type, &ddc_bus,
415 linkb, igp_lane_info);
416
417 }
418 }
419
420 radeon_link_encoder_connector(dev);
421
422 return true;
423}
424
425struct bios_connector {
426 bool valid;
427 uint8_t line_mux;
428 uint16_t devices;
429 int connector_type;
430 struct radeon_i2c_bus_rec ddc_bus;
431};
432
433bool radeon_get_atom_connector_info_from_supported_devices_table(struct
434 drm_device
435 *dev)
436{
437 struct radeon_device *rdev = dev->dev_private;
438 struct radeon_mode_info *mode_info = &rdev->mode_info;
439 struct atom_context *ctx = mode_info->atom_context;
440 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
441 uint16_t size, data_offset;
442 uint8_t frev, crev;
443 uint16_t device_support;
444 uint8_t dac;
445 union atom_supported_devices *supported_devices;
446 int i, j;
447 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
448
449 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
450
451 supported_devices =
452 (union atom_supported_devices *)(ctx->bios + data_offset);
453
454 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
455
456 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
457 ATOM_CONNECTOR_INFO_I2C ci =
458 supported_devices->info.asConnInfo[i];
459
460 bios_connectors[i].valid = false;
461
462 if (!(device_support & (1 << i))) {
463 continue;
464 }
465
466 if (i == ATOM_DEVICE_CV_INDEX) {
467 DRM_DEBUG("Skipping Component Video\n");
468 continue;
469 }
470
471 if (i == ATOM_DEVICE_TV1_INDEX) {
472 DRM_DEBUG("Skipping TV Out\n");
473 continue;
474 }
475
476 bios_connectors[i].connector_type =
477 supported_devices_connector_convert[ci.sucConnectorInfo.
478 sbfAccess.
479 bfConnectorType];
480
481 if (bios_connectors[i].connector_type ==
482 DRM_MODE_CONNECTOR_Unknown)
483 continue;
484
485 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
486
487 if ((rdev->family == CHIP_RS690) ||
488 (rdev->family == CHIP_RS740)) {
489 if ((i == ATOM_DEVICE_DFP2_INDEX)
490 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
491 bios_connectors[i].line_mux =
492 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
493 else if ((i == ATOM_DEVICE_DFP3_INDEX)
494 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
495 bios_connectors[i].line_mux =
496 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
497 else
498 bios_connectors[i].line_mux =
499 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
500 } else
501 bios_connectors[i].line_mux =
502 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
503
504 /* give tv unique connector ids */
505 if (i == ATOM_DEVICE_TV1_INDEX) {
506 bios_connectors[i].ddc_bus.valid = false;
507 bios_connectors[i].line_mux = 50;
508 } else if (i == ATOM_DEVICE_TV2_INDEX) {
509 bios_connectors[i].ddc_bus.valid = false;
510 bios_connectors[i].line_mux = 51;
511 } else if (i == ATOM_DEVICE_CV_INDEX) {
512 bios_connectors[i].ddc_bus.valid = false;
513 bios_connectors[i].line_mux = 52;
514 } else
515 bios_connectors[i].ddc_bus =
516 radeon_lookup_gpio(dev,
517 bios_connectors[i].line_mux);
518
519 /* Always set the connector type to VGA for CRT1/CRT2. if they are
520 * shared with a DVI port, we'll pick up the DVI connector when we
521 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
522 */
523 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
524 bios_connectors[i].connector_type =
525 DRM_MODE_CONNECTOR_VGA;
526
527 if (!radeon_atom_apply_quirks
528 (dev, (1 << i), &bios_connectors[i].connector_type,
529 &bios_connectors[i].ddc_bus))
530 continue;
531
532 bios_connectors[i].valid = true;
533 bios_connectors[i].devices = (1 << i);
534
535 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
536 radeon_add_atom_encoder(dev,
537 radeon_get_encoder_id(dev,
538 (1 << i),
539 dac),
540 (1 << i));
541 else
542 radeon_add_legacy_encoder(dev,
543 radeon_get_encoder_id(dev,
544 (1 <<
545 i),
546 dac),
547 (1 << i));
548 }
549
550 /* combine shared connectors */
551 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
552 if (bios_connectors[i].valid) {
553 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
554 if (bios_connectors[j].valid && (i != j)) {
555 if (bios_connectors[i].line_mux ==
556 bios_connectors[j].line_mux) {
557 if (((bios_connectors[i].
558 devices &
559 (ATOM_DEVICE_DFP_SUPPORT))
560 && (bios_connectors[j].
561 devices &
562 (ATOM_DEVICE_CRT_SUPPORT)))
563 ||
564 ((bios_connectors[j].
565 devices &
566 (ATOM_DEVICE_DFP_SUPPORT))
567 && (bios_connectors[i].
568 devices &
569 (ATOM_DEVICE_CRT_SUPPORT)))) {
570 bios_connectors[i].
571 devices |=
572 bios_connectors[j].
573 devices;
574 bios_connectors[i].
575 connector_type =
576 DRM_MODE_CONNECTOR_DVII;
577 bios_connectors[j].
578 valid = false;
579 }
580 }
581 }
582 }
583 }
584 }
585
586 /* add the connectors */
587 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
588 if (bios_connectors[i].valid)
589 radeon_add_atom_connector(dev,
590 bios_connectors[i].line_mux,
591 bios_connectors[i].devices,
592 bios_connectors[i].
593 connector_type,
594 &bios_connectors[i].ddc_bus,
595 false, 0);
596 }
597
598 radeon_link_encoder_connector(dev);
599
600 return true;
601}
602
603union firmware_info {
604 ATOM_FIRMWARE_INFO info;
605 ATOM_FIRMWARE_INFO_V1_2 info_12;
606 ATOM_FIRMWARE_INFO_V1_3 info_13;
607 ATOM_FIRMWARE_INFO_V1_4 info_14;
608};
609
610bool radeon_atom_get_clock_info(struct drm_device *dev)
611{
612 struct radeon_device *rdev = dev->dev_private;
613 struct radeon_mode_info *mode_info = &rdev->mode_info;
614 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
615 union firmware_info *firmware_info;
616 uint8_t frev, crev;
617 struct radeon_pll *p1pll = &rdev->clock.p1pll;
618 struct radeon_pll *p2pll = &rdev->clock.p2pll;
619 struct radeon_pll *spll = &rdev->clock.spll;
620 struct radeon_pll *mpll = &rdev->clock.mpll;
621 uint16_t data_offset;
622
623 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
624 &crev, &data_offset);
625
626 firmware_info =
627 (union firmware_info *)(mode_info->atom_context->bios +
628 data_offset);
629
630 if (firmware_info) {
631 /* pixel clocks */
632 p1pll->reference_freq =
633 le16_to_cpu(firmware_info->info.usReferenceClock);
634 p1pll->reference_div = 0;
635
636 p1pll->pll_out_min =
637 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
638 p1pll->pll_out_max =
639 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
640
641 if (p1pll->pll_out_min == 0) {
642 if (ASIC_IS_AVIVO(rdev))
643 p1pll->pll_out_min = 64800;
644 else
645 p1pll->pll_out_min = 20000;
646 }
647
648 p1pll->pll_in_min =
649 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
650 p1pll->pll_in_max =
651 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
652
653 *p2pll = *p1pll;
654
655 /* system clock */
656 spll->reference_freq =
657 le16_to_cpu(firmware_info->info.usReferenceClock);
658 spll->reference_div = 0;
659
660 spll->pll_out_min =
661 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
662 spll->pll_out_max =
663 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
664
665 /* ??? */
666 if (spll->pll_out_min == 0) {
667 if (ASIC_IS_AVIVO(rdev))
668 spll->pll_out_min = 64800;
669 else
670 spll->pll_out_min = 20000;
671 }
672
673 spll->pll_in_min =
674 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
675 spll->pll_in_max =
676 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
677
678 /* memory clock */
679 mpll->reference_freq =
680 le16_to_cpu(firmware_info->info.usReferenceClock);
681 mpll->reference_div = 0;
682
683 mpll->pll_out_min =
684 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
685 mpll->pll_out_max =
686 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
687
688 /* ??? */
689 if (mpll->pll_out_min == 0) {
690 if (ASIC_IS_AVIVO(rdev))
691 mpll->pll_out_min = 64800;
692 else
693 mpll->pll_out_min = 20000;
694 }
695
696 mpll->pll_in_min =
697 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
698 mpll->pll_in_max =
699 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
700
701 rdev->clock.default_sclk =
702 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
703 rdev->clock.default_mclk =
704 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
705
706 return true;
707 }
708 return false;
709}
710
711struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
712 radeon_encoder
713 *encoder)
714{
715 struct drm_device *dev = encoder->base.dev;
716 struct radeon_device *rdev = dev->dev_private;
717 struct radeon_mode_info *mode_info = &rdev->mode_info;
718 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
719 uint16_t data_offset;
720 struct _ATOM_TMDS_INFO *tmds_info;
721 uint8_t frev, crev;
722 uint16_t maxfreq;
723 int i;
724 struct radeon_encoder_int_tmds *tmds = NULL;
725
726 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
727 &crev, &data_offset);
728
729 tmds_info =
730 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
731 data_offset);
732
733 if (tmds_info) {
734 tmds =
735 kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
736
737 if (!tmds)
738 return NULL;
739
740 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
741 for (i = 0; i < 4; i++) {
742 tmds->tmds_pll[i].freq =
743 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
744 tmds->tmds_pll[i].value =
745 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
746 tmds->tmds_pll[i].value |=
747 (tmds_info->asMiscInfo[i].
748 ucPLL_VCO_Gain & 0x3f) << 6;
749 tmds->tmds_pll[i].value |=
750 (tmds_info->asMiscInfo[i].
751 ucPLL_DutyCycle & 0xf) << 12;
752 tmds->tmds_pll[i].value |=
753 (tmds_info->asMiscInfo[i].
754 ucPLL_VoltageSwing & 0xf) << 16;
755
756 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
757 tmds->tmds_pll[i].freq,
758 tmds->tmds_pll[i].value);
759
760 if (maxfreq == tmds->tmds_pll[i].freq) {
761 tmds->tmds_pll[i].freq = 0xffffffff;
762 break;
763 }
764 }
765 }
766 return tmds;
767}
768
769union lvds_info {
770 struct _ATOM_LVDS_INFO info;
771 struct _ATOM_LVDS_INFO_V12 info_12;
772};
773
774struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
775 radeon_encoder
776 *encoder)
777{
778 struct drm_device *dev = encoder->base.dev;
779 struct radeon_device *rdev = dev->dev_private;
780 struct radeon_mode_info *mode_info = &rdev->mode_info;
781 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
782 uint16_t data_offset;
783 union lvds_info *lvds_info;
784 uint8_t frev, crev;
785 struct radeon_encoder_atom_dig *lvds = NULL;
786
787 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
788 &crev, &data_offset);
789
790 lvds_info =
791 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
792
793 if (lvds_info) {
794 lvds =
795 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
796
797 if (!lvds)
798 return NULL;
799
800 lvds->native_mode.dotclock =
801 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
802 lvds->native_mode.panel_xres =
803 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
804 lvds->native_mode.panel_yres =
805 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
806 lvds->native_mode.hblank =
807 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
808 lvds->native_mode.hoverplus =
809 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
810 lvds->native_mode.hsync_width =
811 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
812 lvds->native_mode.vblank =
813 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
814 lvds->native_mode.voverplus =
815 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
816 lvds->native_mode.vsync_width =
817 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
818 lvds->panel_pwr_delay =
819 le16_to_cpu(lvds_info->info.usOffDelayInMs);
820 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
821
822 encoder->native_mode = lvds->native_mode;
823 }
824 return lvds;
825}
826
827void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
828{
829 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
830 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
831
832 args.ucEnable = enable;
833
834 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
835}
836
837void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
838{
839 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
840 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
841
842 args.ucEnable = enable;
843
844 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
845}
846
847void radeon_atom_set_engine_clock(struct radeon_device *rdev,
848 uint32_t eng_clock)
849{
850 SET_ENGINE_CLOCK_PS_ALLOCATION args;
851 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
852
853 args.ulTargetEngineClock = eng_clock; /* 10 khz */
854
855 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
856}
857
858void radeon_atom_set_memory_clock(struct radeon_device *rdev,
859 uint32_t mem_clock)
860{
861 SET_MEMORY_CLOCK_PS_ALLOCATION args;
862 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
863
864 if (rdev->flags & RADEON_IS_IGP)
865 return;
866
867 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
868
869 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
870}
871
872void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
873{
874 struct radeon_device *rdev = dev->dev_private;
875 uint32_t bios_2_scratch, bios_6_scratch;
876
877 if (rdev->family >= CHIP_R600) {
878 bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH);
879 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
880 } else {
881 bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
882 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
883 }
884
885 /* let the bios control the backlight */
886 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
887
888 /* tell the bios not to handle mode switching */
889 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
890
891 if (rdev->family >= CHIP_R600) {
892 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
893 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
894 } else {
895 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
896 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
897 }
898
899}
900
901void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
902{
903 struct drm_device *dev = encoder->dev;
904 struct radeon_device *rdev = dev->dev_private;
905 uint32_t bios_6_scratch;
906
907 if (rdev->family >= CHIP_R600)
908 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
909 else
910 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
911
912 if (lock)
913 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
914 else
915 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
916
917 if (rdev->family >= CHIP_R600)
918 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
919 else
920 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
921}
922
923/* at some point we may want to break this out into individual functions */
924void
925radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
926 struct drm_encoder *encoder,
927 bool connected)
928{
929 struct drm_device *dev = connector->dev;
930 struct radeon_device *rdev = dev->dev_private;
931 struct radeon_connector *radeon_connector =
932 to_radeon_connector(connector);
933 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
934 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
935
936 if (rdev->family >= CHIP_R600) {
937 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
938 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
939 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
940 } else {
941 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
942 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
943 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
944 }
945
946 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
947 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
948 if (connected) {
949 DRM_DEBUG("TV1 connected\n");
950 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
951 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
952 } else {
953 DRM_DEBUG("TV1 disconnected\n");
954 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
955 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
956 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
957 }
958 }
959 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
960 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
961 if (connected) {
962 DRM_DEBUG("CV connected\n");
963 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
964 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
965 } else {
966 DRM_DEBUG("CV disconnected\n");
967 bios_0_scratch &= ~ATOM_S0_CV_MASK;
968 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
969 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
970 }
971 }
972 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
973 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
974 if (connected) {
975 DRM_DEBUG("LCD1 connected\n");
976 bios_0_scratch |= ATOM_S0_LCD1;
977 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
978 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
979 } else {
980 DRM_DEBUG("LCD1 disconnected\n");
981 bios_0_scratch &= ~ATOM_S0_LCD1;
982 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
983 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
984 }
985 }
986 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
987 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
988 if (connected) {
989 DRM_DEBUG("CRT1 connected\n");
990 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
991 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
992 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
993 } else {
994 DRM_DEBUG("CRT1 disconnected\n");
995 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
996 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
997 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
998 }
999 }
1000 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1001 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1002 if (connected) {
1003 DRM_DEBUG("CRT2 connected\n");
1004 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1005 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1006 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1007 } else {
1008 DRM_DEBUG("CRT2 disconnected\n");
1009 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1010 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1011 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1012 }
1013 }
1014 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1015 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1016 if (connected) {
1017 DRM_DEBUG("DFP1 connected\n");
1018 bios_0_scratch |= ATOM_S0_DFP1;
1019 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1020 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1021 } else {
1022 DRM_DEBUG("DFP1 disconnected\n");
1023 bios_0_scratch &= ~ATOM_S0_DFP1;
1024 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1025 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1026 }
1027 }
1028 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1029 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1030 if (connected) {
1031 DRM_DEBUG("DFP2 connected\n");
1032 bios_0_scratch |= ATOM_S0_DFP2;
1033 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1034 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1035 } else {
1036 DRM_DEBUG("DFP2 disconnected\n");
1037 bios_0_scratch &= ~ATOM_S0_DFP2;
1038 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1039 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1040 }
1041 }
1042 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1043 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1044 if (connected) {
1045 DRM_DEBUG("DFP3 connected\n");
1046 bios_0_scratch |= ATOM_S0_DFP3;
1047 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1048 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1049 } else {
1050 DRM_DEBUG("DFP3 disconnected\n");
1051 bios_0_scratch &= ~ATOM_S0_DFP3;
1052 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1053 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1054 }
1055 }
1056 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1057 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1058 if (connected) {
1059 DRM_DEBUG("DFP4 connected\n");
1060 bios_0_scratch |= ATOM_S0_DFP4;
1061 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1062 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1063 } else {
1064 DRM_DEBUG("DFP4 disconnected\n");
1065 bios_0_scratch &= ~ATOM_S0_DFP4;
1066 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1067 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1068 }
1069 }
1070 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1071 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1072 if (connected) {
1073 DRM_DEBUG("DFP5 connected\n");
1074 bios_0_scratch |= ATOM_S0_DFP5;
1075 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1076 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1077 } else {
1078 DRM_DEBUG("DFP5 disconnected\n");
1079 bios_0_scratch &= ~ATOM_S0_DFP5;
1080 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1081 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1082 }
1083 }
1084
1085 if (rdev->family >= CHIP_R600) {
1086 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1087 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1088 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1089 } else {
1090 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1091 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1092 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1093 }
1094}
1095
1096void
1097radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1098{
1099 struct drm_device *dev = encoder->dev;
1100 struct radeon_device *rdev = dev->dev_private;
1101 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1102 uint32_t bios_3_scratch;
1103
1104 if (rdev->family >= CHIP_R600)
1105 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1106 else
1107 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1108
1109 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1110 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1111 bios_3_scratch |= (crtc << 18);
1112 }
1113 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1114 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1115 bios_3_scratch |= (crtc << 24);
1116 }
1117 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1118 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1119 bios_3_scratch |= (crtc << 16);
1120 }
1121 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1122 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1123 bios_3_scratch |= (crtc << 20);
1124 }
1125 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1126 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1127 bios_3_scratch |= (crtc << 17);
1128 }
1129 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1130 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1131 bios_3_scratch |= (crtc << 19);
1132 }
1133 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1134 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1135 bios_3_scratch |= (crtc << 23);
1136 }
1137 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1138 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1139 bios_3_scratch |= (crtc << 25);
1140 }
1141
1142 if (rdev->family >= CHIP_R600)
1143 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1144 else
1145 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1146}
1147
1148void
1149radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1150{
1151 struct drm_device *dev = encoder->dev;
1152 struct radeon_device *rdev = dev->dev_private;
1153 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1154 uint32_t bios_2_scratch;
1155
1156 if (rdev->family >= CHIP_R600)
1157 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1158 else
1159 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1160
1161 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1162 if (on)
1163 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1164 else
1165 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1166 }
1167 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1168 if (on)
1169 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1170 else
1171 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1172 }
1173 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1174 if (on)
1175 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1176 else
1177 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1178 }
1179 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1180 if (on)
1181 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1182 else
1183 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1184 }
1185 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1186 if (on)
1187 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1188 else
1189 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1190 }
1191 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1192 if (on)
1193 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1194 else
1195 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1196 }
1197 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1198 if (on)
1199 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1200 else
1201 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1202 }
1203 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1204 if (on)
1205 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1206 else
1207 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1208 }
1209 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1210 if (on)
1211 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1212 else
1213 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1214 }
1215 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1216 if (on)
1217 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1218 else
1219 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1220 }
1221
1222 if (rdev->family >= CHIP_R600)
1223 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1224 else
1225 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1226}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 15:32:08 -0400