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authorAlex Deucher <alexdeucher@gmail.com>2010-09-09 11:33:36 -0400
committerDave Airlie <airlied@redhat.com>2010-10-05 21:46:30 -0400
commitd7ccd8fc11700502b5a104b7bad595b492a3aa1b (patch)
treedf2a228494a959470d3efd5a7c8cde9e642aca21 /drivers/gpu/drm/radeon/radeon_asic.h
parent75fa0b08e50cb72715b58321e8259c47adfe4c6f (diff)
drm/radeon/kms: add drm blit support for evergreen
This patch implements blit support for bo moves using the 3D engine. It uses the same method as r6xx/r7xx: - store the base state in an IB - emit variable state and vertex buffers to do the blit This allows the hw to move bos using the 3D engine and allows full use of vram beyond the pci aperture size. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h8
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 6d3b055c02f..74098824414 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -254,11 +254,6 @@ void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
254int r600_cs_parse(struct radeon_cs_parser *p); 254int r600_cs_parse(struct radeon_cs_parser *p);
255void r600_fence_ring_emit(struct radeon_device *rdev, 255void r600_fence_ring_emit(struct radeon_device *rdev,
256 struct radeon_fence *fence); 256 struct radeon_fence *fence);
257int r600_copy_dma(struct radeon_device *rdev,
258 uint64_t src_offset,
259 uint64_t dst_offset,
260 unsigned num_pages,
261 struct radeon_fence *fence);
262int r600_irq_process(struct radeon_device *rdev); 257int r600_irq_process(struct radeon_device *rdev);
263int r600_irq_set(struct radeon_device *rdev); 258int r600_irq_set(struct radeon_device *rdev);
264bool r600_gpu_is_lockup(struct radeon_device *rdev); 259bool r600_gpu_is_lockup(struct radeon_device *rdev);
@@ -304,6 +299,9 @@ int evergreen_resume(struct radeon_device *rdev);
304bool evergreen_gpu_is_lockup(struct radeon_device *rdev); 299bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
305int evergreen_asic_reset(struct radeon_device *rdev); 300int evergreen_asic_reset(struct radeon_device *rdev);
306void evergreen_bandwidth_update(struct radeon_device *rdev); 301void evergreen_bandwidth_update(struct radeon_device *rdev);
302int evergreen_copy_blit(struct radeon_device *rdev,
303 uint64_t src_offset, uint64_t dst_offset,
304 unsigned num_pages, struct radeon_fence *fence);
307void evergreen_hpd_init(struct radeon_device *rdev); 305void evergreen_hpd_init(struct radeon_device *rdev);
308void evergreen_hpd_fini(struct radeon_device *rdev); 306void evergreen_hpd_fini(struct radeon_device *rdev);
309bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 307bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);