Merge remote branch 'intel/drm-intel-next' of ../drm-next into drm-core-next

* 'intel/drm-intel-next' of ../drm-next: (755 commits)
  drm/i915: Only wait on a pending flip if we intend to write to the buffer
  drm/i915/dp: Sanity check eDP existence
  drm/i915: Rebind the buffer if its alignment constraints changes with tiling
  drm/i915: Disable GPU semaphores by default
  drm/i915: Do not overflow the MMADDR write FIFO
  Revert "drm/i915: fix corruptions on i8xx due to relaxed fencing"
  drm/i915: Don't save/restore hardware status page address register
  drm/i915: don't store the reg value for HWS_PGA
  drm/i915: fix memory corruption with GM965 and >4GB RAM
  Linux 2.6.38-rc7
  Revert "TPM: Long default timeout fix"
  drm/i915: Re-enable GPU semaphores for SandyBridge mobile
  drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#"
  Revert "drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPU"
  drm/i915: Allow relocation deltas outside of target bo
  drm/i915: Silence an innocuous compiler warning for an unused variable
  fs/block_dev.c: fix new kernel-doc warning
  ACPI: Fix build for CONFIG_NET unset
  mm: <asm-generic/pgtable.h> must include <linux/mm_types.h>
  x86: Use u32 instead of long to set reset vector back to 0
  ...

Conflicts:
	drivers/gpu/drm/i915/i915_gem.c

1 files changed, 5 insertions, 4 deletions

diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index d1f598663da..b2b944bcd05 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -154,13 +154,14 @@
 #define         ROQ_IB2_START(x)                                ((x) << 8)
 #define CP_RB_BASE                                      0xC100
 #define CP_RB_CNTL                                      0xC104
-#define         RB_BUFSZ(x)                                     ((x)<<0)
-#define         RB_BLKSZ(x)                                     ((x)<<8)
-#define         RB_NO_UPDATE                                    (1<<27)
-#define         RB_RPTR_WR_ENA                                  (1<<31)
+#define         RB_BUFSZ(x)                                     ((x) << 0)
+#define         RB_BLKSZ(x)                                     ((x) << 8)
+#define         RB_NO_UPDATE                                    (1 << 27)
+#define         RB_RPTR_WR_ENA                                  (1 << 31)
 #define         BUF_SWAP_32BIT                                  (2 << 16)
 #define CP_RB_RPTR                                      0x8700
 #define CP_RB_RPTR_ADDR                                 0xC10C
+#define         RB_RPTR_SWAP(x)                                 ((x) << 0)
 #define CP_RB_RPTR_ADDR_HI                              0xC110
 #define CP_RB_RPTR_WR                                   0xC108
 #define CP_RB_WPTR                                      0xC114