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authorJerome Glisse <jglisse@redhat.com>2012-03-21 19:18:21 -0400
committerDave Airlie <airlied@redhat.com>2012-03-26 04:53:22 -0400
commit88f50c80748bf5238c88e70ee26c68ac48b94e68 (patch)
tree2b4df17fdb6c690bfdeee9dd7e5b4ed30bbf1836 /drivers/gpu/drm/radeon/r600_cs.c
parent017d213f649c6775e4a4349e50a5631a4e4c7308 (diff)
drm/radeon/kms: add htile support to the cs checker v3
For 6xx+. Required for mesa to use htile support for HiZ/HiS. Userspace will check radeon version 2.14 with is bumped either by tiling patch or stream out patch. This patch only add support for htile relocation which should be enough for any userspace to implement the hyperz (using htile buffer) feature. v2: Jerome: Fix size checking for htile buffer. v3: Jerome: Adapt on top of r600/evergreen cs checker changes, also check htile surface in case only stencil is present. Signed-off-by: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_cs.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c391
1 files changed, 273 insertions, 118 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0ec3f205f9c..b8e12af304a 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -78,6 +78,9 @@ struct r600_cs_track {
78 bool cb_dirty; 78 bool cb_dirty;
79 bool db_dirty; 79 bool db_dirty;
80 bool streamout_dirty; 80 bool streamout_dirty;
81 struct radeon_bo *htile_bo;
82 u64 htile_offset;
83 u32 htile_surface;
81}; 84};
82 85
83#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } 86#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
@@ -321,6 +324,9 @@ static void r600_cs_track_init(struct r600_cs_track *track)
321 track->db_depth_size_idx = 0; 324 track->db_depth_size_idx = 0;
322 track->db_depth_control = 0xFFFFFFFF; 325 track->db_depth_control = 0xFFFFFFFF;
323 track->db_dirty = true; 326 track->db_dirty = true;
327 track->htile_bo = NULL;
328 track->htile_offset = 0xFFFFFFFF;
329 track->htile_surface = 0;
324 330
325 for (i = 0; i < 4; i++) { 331 for (i = 0; i < 4; i++) {
326 track->vgt_strmout_size[i] = 0; 332 track->vgt_strmout_size[i] = 0;
@@ -455,12 +461,256 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
455 return 0; 461 return 0;
456} 462}
457 463
464static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
465{
466 struct r600_cs_track *track = p->track;
467 u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
468 u32 height_align, pitch_align, depth_align;
469 u32 pitch = 8192;
470 u32 height = 8192;
471 u64 base_offset, base_align;
472 struct array_mode_checker array_check;
473 int array_mode;
474 volatile u32 *ib = p->ib->ptr;
475
476
477 if (track->db_bo == NULL) {
478 dev_warn(p->dev, "z/stencil with no depth buffer\n");
479 return -EINVAL;
480 }
481 switch (G_028010_FORMAT(track->db_depth_info)) {
482 case V_028010_DEPTH_16:
483 bpe = 2;
484 break;
485 case V_028010_DEPTH_X8_24:
486 case V_028010_DEPTH_8_24:
487 case V_028010_DEPTH_X8_24_FLOAT:
488 case V_028010_DEPTH_8_24_FLOAT:
489 case V_028010_DEPTH_32_FLOAT:
490 bpe = 4;
491 break;
492 case V_028010_DEPTH_X24_8_32_FLOAT:
493 bpe = 8;
494 break;
495 default:
496 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
497 return -EINVAL;
498 }
499 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
500 if (!track->db_depth_size_idx) {
501 dev_warn(p->dev, "z/stencil buffer size not set\n");
502 return -EINVAL;
503 }
504 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
505 tmp = (tmp / bpe) >> 6;
506 if (!tmp) {
507 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
508 track->db_depth_size, bpe, track->db_offset,
509 radeon_bo_size(track->db_bo));
510 return -EINVAL;
511 }
512 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
513 } else {
514 size = radeon_bo_size(track->db_bo);
515 /* pitch in pixels */
516 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
517 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
518 slice_tile_max *= 64;
519 height = slice_tile_max / pitch;
520 if (height > 8192)
521 height = 8192;
522 base_offset = track->db_bo_mc + track->db_offset;
523 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
524 array_check.array_mode = array_mode;
525 array_check.group_size = track->group_size;
526 array_check.nbanks = track->nbanks;
527 array_check.npipes = track->npipes;
528 array_check.nsamples = track->nsamples;
529 array_check.blocksize = bpe;
530 if (r600_get_array_mode_alignment(&array_check,
531 &pitch_align, &height_align, &depth_align, &base_align)) {
532 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
533 G_028010_ARRAY_MODE(track->db_depth_info),
534 track->db_depth_info);
535 return -EINVAL;
536 }
537 switch (array_mode) {
538 case V_028010_ARRAY_1D_TILED_THIN1:
539 /* don't break userspace */
540 height &= ~0x7;
541 break;
542 case V_028010_ARRAY_2D_TILED_THIN1:
543 break;
544 default:
545 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
546 G_028010_ARRAY_MODE(track->db_depth_info),
547 track->db_depth_info);
548 return -EINVAL;
549 }
550
551 if (!IS_ALIGNED(pitch, pitch_align)) {
552 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
553 __func__, __LINE__, pitch, pitch_align, array_mode);
554 return -EINVAL;
555 }
556 if (!IS_ALIGNED(height, height_align)) {
557 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
558 __func__, __LINE__, height, height_align, array_mode);
559 return -EINVAL;
560 }
561 if (!IS_ALIGNED(base_offset, base_align)) {
562 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
563 base_offset, base_align, array_mode);
564 return -EINVAL;
565 }
566
567 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
568 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
569 tmp = ntiles * bpe * 64 * nviews;
570 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
571 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
572 array_mode,
573 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
574 radeon_bo_size(track->db_bo));
575 return -EINVAL;
576 }
577 }
578
579 /* hyperz */
580 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
581 unsigned long size;
582 unsigned nbx, nby;
583
584 if (track->htile_bo == NULL) {
585 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
586 __func__, __LINE__, track->db_depth_info);
587 return -EINVAL;
588 }
589 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
590 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
591 __func__, __LINE__, track->db_depth_size);
592 return -EINVAL;
593 }
594
595 nbx = pitch;
596 nby = height;
597 if (G_028D24_LINEAR(track->htile_surface)) {
598 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
599 nbx = round_up(nbx, 16 * 8);
600 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
601 nby = round_up(nby, track->npipes * 8);
602 } else {
603 /* htile widht & nby (8 or 4) make 2 bits number */
604 tmp = track->htile_surface & 3;
605 /* align is htile align * 8, htile align vary according to
606 * number of pipe and tile width and nby
607 */
608 switch (track->npipes) {
609 case 8:
610 switch (tmp) {
611 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
612 nbx = round_up(nbx, 64 * 8);
613 nby = round_up(nby, 64 * 8);
614 break;
615 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
616 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
617 nbx = round_up(nbx, 64 * 8);
618 nby = round_up(nby, 32 * 8);
619 break;
620 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
621 nbx = round_up(nbx, 32 * 8);
622 nby = round_up(nby, 32 * 8);
623 break;
624 default:
625 return -EINVAL;
626 }
627 break;
628 case 4:
629 switch (tmp) {
630 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
631 nbx = round_up(nbx, 64 * 8);
632 nby = round_up(nby, 32 * 8);
633 break;
634 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
635 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
636 nbx = round_up(nbx, 32 * 8);
637 nby = round_up(nby, 32 * 8);
638 break;
639 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
640 nbx = round_up(nbx, 32 * 8);
641 nby = round_up(nby, 16 * 8);
642 break;
643 default:
644 return -EINVAL;
645 }
646 break;
647 case 2:
648 switch (tmp) {
649 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
650 nbx = round_up(nbx, 32 * 8);
651 nby = round_up(nby, 32 * 8);
652 break;
653 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
654 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
655 nbx = round_up(nbx, 32 * 8);
656 nby = round_up(nby, 16 * 8);
657 break;
658 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
659 nbx = round_up(nbx, 16 * 8);
660 nby = round_up(nby, 16 * 8);
661 break;
662 default:
663 return -EINVAL;
664 }
665 break;
666 case 1:
667 switch (tmp) {
668 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
669 nbx = round_up(nbx, 32 * 8);
670 nby = round_up(nby, 16 * 8);
671 break;
672 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
673 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
674 nbx = round_up(nbx, 16 * 8);
675 nby = round_up(nby, 16 * 8);
676 break;
677 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
678 nbx = round_up(nbx, 16 * 8);
679 nby = round_up(nby, 8 * 8);
680 break;
681 default:
682 return -EINVAL;
683 }
684 break;
685 default:
686 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
687 __func__, __LINE__, track->npipes);
688 return -EINVAL;
689 }
690 }
691 /* compute number of htile */
692 nbx = G_028D24_HTILE_WIDTH(track->htile_surface) ? nbx / 8 : nbx / 4;
693 nby = G_028D24_HTILE_HEIGHT(track->htile_surface) ? nby / 8 : nby / 4;
694 size = nbx * nby * 4;
695 size += track->htile_offset;
696
697 if (size > radeon_bo_size(track->htile_bo)) {
698 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
699 __func__, __LINE__, radeon_bo_size(track->htile_bo),
700 size, nbx, nby);
701 return -EINVAL;
702 }
703 }
704
705 track->db_dirty = false;
706 return 0;
707}
708
458static int r600_cs_track_check(struct radeon_cs_parser *p) 709static int r600_cs_track_check(struct radeon_cs_parser *p)
459{ 710{
460 struct r600_cs_track *track = p->track; 711 struct r600_cs_track *track = p->track;
461 u32 tmp; 712 u32 tmp;
462 int r, i; 713 int r, i;
463 volatile u32 *ib = p->ib->ptr;
464 714
465 /* on legacy kernel we don't perform advanced check */ 715 /* on legacy kernel we don't perform advanced check */
466 if (p->rdev == NULL) 716 if (p->rdev == NULL)
@@ -513,124 +763,14 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
513 track->cb_dirty = false; 763 track->cb_dirty = false;
514 } 764 }
515 765
516 if (track->db_dirty) { 766 /* Check depth buffer */
517 /* Check depth buffer */ 767 if (track->db_dirty && (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
518 if (G_028800_STENCIL_ENABLE(track->db_depth_control) || 768 G_028800_Z_ENABLE(track->db_depth_control))) {
519 G_028800_Z_ENABLE(track->db_depth_control)) { 769 r = r600_cs_track_validate_db(p);
520 u32 nviews, bpe, ntiles, size, slice_tile_max; 770 if (r)
521 u32 height, height_align, pitch, pitch_align, depth_align; 771 return r;
522 u64 base_offset, base_align;
523 struct array_mode_checker array_check;
524 int array_mode;
525
526 if (track->db_bo == NULL) {
527 dev_warn(p->dev, "z/stencil with no depth buffer\n");
528 return -EINVAL;
529 }
530 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
531 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
532 return -EINVAL;
533 }
534 switch (G_028010_FORMAT(track->db_depth_info)) {
535 case V_028010_DEPTH_16:
536 bpe = 2;
537 break;
538 case V_028010_DEPTH_X8_24:
539 case V_028010_DEPTH_8_24:
540 case V_028010_DEPTH_X8_24_FLOAT:
541 case V_028010_DEPTH_8_24_FLOAT:
542 case V_028010_DEPTH_32_FLOAT:
543 bpe = 4;
544 break;
545 case V_028010_DEPTH_X24_8_32_FLOAT:
546 bpe = 8;
547 break;
548 default:
549 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
550 return -EINVAL;
551 }
552 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
553 if (!track->db_depth_size_idx) {
554 dev_warn(p->dev, "z/stencil buffer size not set\n");
555 return -EINVAL;
556 }
557 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
558 tmp = (tmp / bpe) >> 6;
559 if (!tmp) {
560 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
561 track->db_depth_size, bpe, track->db_offset,
562 radeon_bo_size(track->db_bo));
563 return -EINVAL;
564 }
565 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
566 } else {
567 size = radeon_bo_size(track->db_bo);
568 /* pitch in pixels */
569 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
570 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
571 slice_tile_max *= 64;
572 height = slice_tile_max / pitch;
573 if (height > 8192)
574 height = 8192;
575 base_offset = track->db_bo_mc + track->db_offset;
576 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
577 array_check.array_mode = array_mode;
578 array_check.group_size = track->group_size;
579 array_check.nbanks = track->nbanks;
580 array_check.npipes = track->npipes;
581 array_check.nsamples = track->nsamples;
582 array_check.blocksize = bpe;
583 if (r600_get_array_mode_alignment(&array_check,
584 &pitch_align, &height_align, &depth_align, &base_align)) {
585 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
586 G_028010_ARRAY_MODE(track->db_depth_info),
587 track->db_depth_info);
588 return -EINVAL;
589 }
590 switch (array_mode) {
591 case V_028010_ARRAY_1D_TILED_THIN1:
592 /* don't break userspace */
593 height &= ~0x7;
594 break;
595 case V_028010_ARRAY_2D_TILED_THIN1:
596 break;
597 default:
598 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
599 G_028010_ARRAY_MODE(track->db_depth_info),
600 track->db_depth_info);
601 return -EINVAL;
602 }
603
604 if (!IS_ALIGNED(pitch, pitch_align)) {
605 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
606 __func__, __LINE__, pitch, pitch_align, array_mode);
607 return -EINVAL;
608 }
609 if (!IS_ALIGNED(height, height_align)) {
610 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
611 __func__, __LINE__, height, height_align, array_mode);
612 return -EINVAL;
613 }
614 if (!IS_ALIGNED(base_offset, base_align)) {
615 dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i,
616 base_offset, base_align, array_mode);
617 return -EINVAL;
618 }
619
620 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
621 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
622 tmp = ntiles * bpe * 64 * nviews;
623 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
624 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
625 array_mode,
626 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
627 radeon_bo_size(track->db_bo));
628 return -EINVAL;
629 }
630 }
631 }
632 track->db_dirty = false;
633 } 772 }
773
634 return 0; 774 return 0;
635} 775}
636 776
@@ -1244,6 +1384,21 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1244 track->db_dirty = true; 1384 track->db_dirty = true;
1245 break; 1385 break;
1246 case DB_HTILE_DATA_BASE: 1386 case DB_HTILE_DATA_BASE:
1387 r = r600_cs_packet_next_reloc(p, &reloc);
1388 if (r) {
1389 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1390 "0x%04X\n", reg);
1391 return -EINVAL;
1392 }
1393 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1394 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1395 track->htile_bo = reloc->robj;
1396 track->db_dirty = true;
1397 break;
1398 case DB_HTILE_SURFACE:
1399 track->htile_surface = radeon_get_ib_value(p, idx);
1400 track->db_dirty = true;
1401 break;
1247 case SQ_PGM_START_FS: 1402 case SQ_PGM_START_FS:
1248 case SQ_PGM_START_ES: 1403 case SQ_PGM_START_ES:
1249 case SQ_PGM_START_VS: 1404 case SQ_PGM_START_VS:
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 04:23:15 -0400