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authorMarek Olšák <maraeo@gmail.com>2012-03-18 22:09:38 -0400
committerDave Airlie <airlied@redhat.com>2012-03-20 04:44:53 -0400
commit3c12513d2f5f0e9abb65be3d422d43ebee5f17d7 (patch)
treed914e122bd8a80cf410549c733743a7568dcf753 /drivers/gpu/drm/radeon/r600_cs.c
parent6333003be6a3944ef90e9c451a3e0bc9c2b7a312 (diff)
drm/radeon/kms: skip db/cb/streamout checking when possible on r600
Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_cs.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c270
1 files changed, 150 insertions, 120 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index d9ebec322a6..0ec3f205f9c 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -52,18 +52,18 @@ struct r600_cs_track {
52 struct radeon_bo *cb_color_bo[8]; 52 struct radeon_bo *cb_color_bo[8];
53 u64 cb_color_bo_mc[8]; 53 u64 cb_color_bo_mc[8];
54 u32 cb_color_bo_offset[8]; 54 u32 cb_color_bo_offset[8];
55 struct radeon_bo *cb_color_frag_bo[8]; 55 struct radeon_bo *cb_color_frag_bo[8]; /* unused */
56 struct radeon_bo *cb_color_tile_bo[8]; 56 struct radeon_bo *cb_color_tile_bo[8]; /* unused */
57 u32 cb_color_info[8]; 57 u32 cb_color_info[8];
58 u32 cb_color_view[8]; 58 u32 cb_color_view[8];
59 u32 cb_color_size_idx[8]; 59 u32 cb_color_size_idx[8]; /* unused */
60 u32 cb_target_mask; 60 u32 cb_target_mask;
61 u32 cb_shader_mask; 61 u32 cb_shader_mask; /* unused */
62 u32 cb_color_size[8]; 62 u32 cb_color_size[8];
63 u32 vgt_strmout_en; 63 u32 vgt_strmout_en;
64 u32 vgt_strmout_buffer_en; 64 u32 vgt_strmout_buffer_en;
65 struct radeon_bo *vgt_strmout_bo[4]; 65 struct radeon_bo *vgt_strmout_bo[4];
66 u64 vgt_strmout_bo_mc[4]; 66 u64 vgt_strmout_bo_mc[4]; /* unused */
67 u32 vgt_strmout_bo_offset[4]; 67 u32 vgt_strmout_bo_offset[4];
68 u32 vgt_strmout_size[4]; 68 u32 vgt_strmout_size[4];
69 u32 db_depth_control; 69 u32 db_depth_control;
@@ -75,6 +75,9 @@ struct r600_cs_track {
75 struct radeon_bo *db_bo; 75 struct radeon_bo *db_bo;
76 u64 db_bo_mc; 76 u64 db_bo_mc;
77 bool sx_misc_kill_all_prims; 77 bool sx_misc_kill_all_prims;
78 bool cb_dirty;
79 bool db_dirty;
80 bool streamout_dirty;
78}; 81};
79 82
80#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } 83#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
@@ -308,6 +311,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
308 } 311 }
309 track->cb_target_mask = 0xFFFFFFFF; 312 track->cb_target_mask = 0xFFFFFFFF;
310 track->cb_shader_mask = 0xFFFFFFFF; 313 track->cb_shader_mask = 0xFFFFFFFF;
314 track->cb_dirty = true;
311 track->db_bo = NULL; 315 track->db_bo = NULL;
312 track->db_bo_mc = 0xFFFFFFFF; 316 track->db_bo_mc = 0xFFFFFFFF;
313 /* assume the biggest format and that htile is enabled */ 317 /* assume the biggest format and that htile is enabled */
@@ -316,6 +320,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
316 track->db_depth_size = 0xFFFFFFFF; 320 track->db_depth_size = 0xFFFFFFFF;
317 track->db_depth_size_idx = 0; 321 track->db_depth_size_idx = 0;
318 track->db_depth_control = 0xFFFFFFFF; 322 track->db_depth_control = 0xFFFFFFFF;
323 track->db_dirty = true;
319 324
320 for (i = 0; i < 4; i++) { 325 for (i = 0; i < 4; i++) {
321 track->vgt_strmout_size[i] = 0; 326 track->vgt_strmout_size[i] = 0;
@@ -323,6 +328,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
323 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; 328 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
324 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; 329 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
325 } 330 }
331 track->streamout_dirty = true;
326 track->sx_misc_kill_all_prims = false; 332 track->sx_misc_kill_all_prims = false;
327} 333}
328 334
@@ -461,7 +467,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
461 return 0; 467 return 0;
462 468
463 /* check streamout */ 469 /* check streamout */
464 if (track->vgt_strmout_en) { 470 if (track->streamout_dirty && track->vgt_strmout_en) {
465 for (i = 0; i < 4; i++) { 471 for (i = 0; i < 4; i++) {
466 if (track->vgt_strmout_buffer_en & (1 << i)) { 472 if (track->vgt_strmout_buffer_en & (1 << i)) {
467 if (track->vgt_strmout_bo[i]) { 473 if (track->vgt_strmout_bo[i]) {
@@ -479,6 +485,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
479 } 485 }
480 } 486 }
481 } 487 }
488 track->streamout_dirty = false;
482 } 489 }
483 490
484 if (track->sx_misc_kill_all_prims) 491 if (track->sx_misc_kill_all_prims)
@@ -487,135 +494,142 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
487 /* check that we have a cb for each enabled target, we don't check 494 /* check that we have a cb for each enabled target, we don't check
488 * shader_mask because it seems mesa isn't always setting it :( 495 * shader_mask because it seems mesa isn't always setting it :(
489 */ 496 */
490 tmp = track->cb_target_mask; 497 if (track->cb_dirty) {
491 for (i = 0; i < 8; i++) { 498 tmp = track->cb_target_mask;
492 if ((tmp >> (i * 4)) & 0xF) { 499 for (i = 0; i < 8; i++) {
493 /* at least one component is enabled */ 500 if ((tmp >> (i * 4)) & 0xF) {
494 if (track->cb_color_bo[i] == NULL) { 501 /* at least one component is enabled */
495 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 502 if (track->cb_color_bo[i] == NULL) {
496 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 503 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
497 return -EINVAL; 504 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
505 return -EINVAL;
506 }
507 /* perform rewrite of CB_COLOR[0-7]_SIZE */
508 r = r600_cs_track_validate_cb(p, i);
509 if (r)
510 return r;
498 } 511 }
499 /* perform rewrite of CB_COLOR[0-7]_SIZE */
500 r = r600_cs_track_validate_cb(p, i);
501 if (r)
502 return r;
503 } 512 }
513 track->cb_dirty = false;
504 } 514 }
505 /* Check depth buffer */ 515
506 if (G_028800_STENCIL_ENABLE(track->db_depth_control) || 516 if (track->db_dirty) {
507 G_028800_Z_ENABLE(track->db_depth_control)) { 517 /* Check depth buffer */
508 u32 nviews, bpe, ntiles, size, slice_tile_max; 518 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
509 u32 height, height_align, pitch, pitch_align, depth_align; 519 G_028800_Z_ENABLE(track->db_depth_control)) {
510 u64 base_offset, base_align; 520 u32 nviews, bpe, ntiles, size, slice_tile_max;
511 struct array_mode_checker array_check; 521 u32 height, height_align, pitch, pitch_align, depth_align;
512 int array_mode; 522 u64 base_offset, base_align;
513 523 struct array_mode_checker array_check;
514 if (track->db_bo == NULL) { 524 int array_mode;
515 dev_warn(p->dev, "z/stencil with no depth buffer\n"); 525
516 return -EINVAL; 526 if (track->db_bo == NULL) {
517 } 527 dev_warn(p->dev, "z/stencil with no depth buffer\n");
518 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
519 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
520 return -EINVAL;
521 }
522 switch (G_028010_FORMAT(track->db_depth_info)) {
523 case V_028010_DEPTH_16:
524 bpe = 2;
525 break;
526 case V_028010_DEPTH_X8_24:
527 case V_028010_DEPTH_8_24:
528 case V_028010_DEPTH_X8_24_FLOAT:
529 case V_028010_DEPTH_8_24_FLOAT:
530 case V_028010_DEPTH_32_FLOAT:
531 bpe = 4;
532 break;
533 case V_028010_DEPTH_X24_8_32_FLOAT:
534 bpe = 8;
535 break;
536 default:
537 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
538 return -EINVAL;
539 }
540 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
541 if (!track->db_depth_size_idx) {
542 dev_warn(p->dev, "z/stencil buffer size not set\n");
543 return -EINVAL;
544 }
545 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
546 tmp = (tmp / bpe) >> 6;
547 if (!tmp) {
548 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
549 track->db_depth_size, bpe, track->db_offset,
550 radeon_bo_size(track->db_bo));
551 return -EINVAL; 528 return -EINVAL;
552 } 529 }
553 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); 530 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
554 } else { 531 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
555 size = radeon_bo_size(track->db_bo);
556 /* pitch in pixels */
557 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
558 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
559 slice_tile_max *= 64;
560 height = slice_tile_max / pitch;
561 if (height > 8192)
562 height = 8192;
563 base_offset = track->db_bo_mc + track->db_offset;
564 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
565 array_check.array_mode = array_mode;
566 array_check.group_size = track->group_size;
567 array_check.nbanks = track->nbanks;
568 array_check.npipes = track->npipes;
569 array_check.nsamples = track->nsamples;
570 array_check.blocksize = bpe;
571 if (r600_get_array_mode_alignment(&array_check,
572 &pitch_align, &height_align, &depth_align, &base_align)) {
573 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
574 G_028010_ARRAY_MODE(track->db_depth_info),
575 track->db_depth_info);
576 return -EINVAL; 532 return -EINVAL;
577 } 533 }
578 switch (array_mode) { 534 switch (G_028010_FORMAT(track->db_depth_info)) {
579 case V_028010_ARRAY_1D_TILED_THIN1: 535 case V_028010_DEPTH_16:
580 /* don't break userspace */ 536 bpe = 2;
581 height &= ~0x7; 537 break;
538 case V_028010_DEPTH_X8_24:
539 case V_028010_DEPTH_8_24:
540 case V_028010_DEPTH_X8_24_FLOAT:
541 case V_028010_DEPTH_8_24_FLOAT:
542 case V_028010_DEPTH_32_FLOAT:
543 bpe = 4;
582 break; 544 break;
583 case V_028010_ARRAY_2D_TILED_THIN1: 545 case V_028010_DEPTH_X24_8_32_FLOAT:
546 bpe = 8;
584 break; 547 break;
585 default: 548 default:
586 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 549 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
587 G_028010_ARRAY_MODE(track->db_depth_info),
588 track->db_depth_info);
589 return -EINVAL; 550 return -EINVAL;
590 } 551 }
552 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
553 if (!track->db_depth_size_idx) {
554 dev_warn(p->dev, "z/stencil buffer size not set\n");
555 return -EINVAL;
556 }
557 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
558 tmp = (tmp / bpe) >> 6;
559 if (!tmp) {
560 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
561 track->db_depth_size, bpe, track->db_offset,
562 radeon_bo_size(track->db_bo));
563 return -EINVAL;
564 }
565 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
566 } else {
567 size = radeon_bo_size(track->db_bo);
568 /* pitch in pixels */
569 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
570 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
571 slice_tile_max *= 64;
572 height = slice_tile_max / pitch;
573 if (height > 8192)
574 height = 8192;
575 base_offset = track->db_bo_mc + track->db_offset;
576 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
577 array_check.array_mode = array_mode;
578 array_check.group_size = track->group_size;
579 array_check.nbanks = track->nbanks;
580 array_check.npipes = track->npipes;
581 array_check.nsamples = track->nsamples;
582 array_check.blocksize = bpe;
583 if (r600_get_array_mode_alignment(&array_check,
584 &pitch_align, &height_align, &depth_align, &base_align)) {
585 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
586 G_028010_ARRAY_MODE(track->db_depth_info),
587 track->db_depth_info);
588 return -EINVAL;
589 }
590 switch (array_mode) {
591 case V_028010_ARRAY_1D_TILED_THIN1:
592 /* don't break userspace */
593 height &= ~0x7;
594 break;
595 case V_028010_ARRAY_2D_TILED_THIN1:
596 break;
597 default:
598 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
599 G_028010_ARRAY_MODE(track->db_depth_info),
600 track->db_depth_info);
601 return -EINVAL;
602 }
591 603
592 if (!IS_ALIGNED(pitch, pitch_align)) { 604 if (!IS_ALIGNED(pitch, pitch_align)) {
593 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", 605 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
594 __func__, __LINE__, pitch, pitch_align, array_mode); 606 __func__, __LINE__, pitch, pitch_align, array_mode);
595 return -EINVAL; 607 return -EINVAL;
596 } 608 }
597 if (!IS_ALIGNED(height, height_align)) { 609 if (!IS_ALIGNED(height, height_align)) {
598 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", 610 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
599 __func__, __LINE__, height, height_align, array_mode); 611 __func__, __LINE__, height, height_align, array_mode);
600 return -EINVAL; 612 return -EINVAL;
601 } 613 }
602 if (!IS_ALIGNED(base_offset, base_align)) { 614 if (!IS_ALIGNED(base_offset, base_align)) {
603 dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i, 615 dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i,
604 base_offset, base_align, array_mode); 616 base_offset, base_align, array_mode);
605 return -EINVAL; 617 return -EINVAL;
606 } 618 }
607 619
608 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 620 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
609 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 621 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
610 tmp = ntiles * bpe * 64 * nviews; 622 tmp = ntiles * bpe * 64 * nviews;
611 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { 623 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
612 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", 624 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
613 array_mode, 625 array_mode,
614 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, 626 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
615 radeon_bo_size(track->db_bo)); 627 radeon_bo_size(track->db_bo));
616 return -EINVAL; 628 return -EINVAL;
629 }
617 } 630 }
618 } 631 }
632 track->db_dirty = false;
619 } 633 }
620 return 0; 634 return 0;
621} 635}
@@ -988,6 +1002,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
988 break; 1002 break;
989 case R_028800_DB_DEPTH_CONTROL: 1003 case R_028800_DB_DEPTH_CONTROL:
990 track->db_depth_control = radeon_get_ib_value(p, idx); 1004 track->db_depth_control = radeon_get_ib_value(p, idx);
1005 track->db_dirty = true;
991 break; 1006 break;
992 case R_028010_DB_DEPTH_INFO: 1007 case R_028010_DB_DEPTH_INFO:
993 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1008 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
@@ -1008,21 +1023,27 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1008 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); 1023 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1009 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); 1024 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1010 } 1025 }
1011 } else 1026 } else {
1012 track->db_depth_info = radeon_get_ib_value(p, idx); 1027 track->db_depth_info = radeon_get_ib_value(p, idx);
1028 }
1029 track->db_dirty = true;
1013 break; 1030 break;
1014 case R_028004_DB_DEPTH_VIEW: 1031 case R_028004_DB_DEPTH_VIEW:
1015 track->db_depth_view = radeon_get_ib_value(p, idx); 1032 track->db_depth_view = radeon_get_ib_value(p, idx);
1033 track->db_dirty = true;
1016 break; 1034 break;
1017 case R_028000_DB_DEPTH_SIZE: 1035 case R_028000_DB_DEPTH_SIZE:
1018 track->db_depth_size = radeon_get_ib_value(p, idx); 1036 track->db_depth_size = radeon_get_ib_value(p, idx);
1019 track->db_depth_size_idx = idx; 1037 track->db_depth_size_idx = idx;
1038 track->db_dirty = true;
1020 break; 1039 break;
1021 case R_028AB0_VGT_STRMOUT_EN: 1040 case R_028AB0_VGT_STRMOUT_EN:
1022 track->vgt_strmout_en = radeon_get_ib_value(p, idx); 1041 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1042 track->streamout_dirty = true;
1023 break; 1043 break;
1024 case R_028B20_VGT_STRMOUT_BUFFER_EN: 1044 case R_028B20_VGT_STRMOUT_BUFFER_EN:
1025 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); 1045 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1046 track->streamout_dirty = true;
1026 break; 1047 break;
1027 case VGT_STRMOUT_BUFFER_BASE_0: 1048 case VGT_STRMOUT_BUFFER_BASE_0:
1028 case VGT_STRMOUT_BUFFER_BASE_1: 1049 case VGT_STRMOUT_BUFFER_BASE_1:
@@ -1039,6 +1060,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1039 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1060 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1040 track->vgt_strmout_bo[tmp] = reloc->robj; 1061 track->vgt_strmout_bo[tmp] = reloc->robj;
1041 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset; 1062 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1063 track->streamout_dirty = true;
1042 break; 1064 break;
1043 case VGT_STRMOUT_BUFFER_SIZE_0: 1065 case VGT_STRMOUT_BUFFER_SIZE_0:
1044 case VGT_STRMOUT_BUFFER_SIZE_1: 1066 case VGT_STRMOUT_BUFFER_SIZE_1:
@@ -1047,6 +1069,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1047 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; 1069 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1048 /* size in register is DWs, convert to bytes */ 1070 /* size in register is DWs, convert to bytes */
1049 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; 1071 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1072 track->streamout_dirty = true;
1050 break; 1073 break;
1051 case CP_COHER_BASE: 1074 case CP_COHER_BASE:
1052 r = r600_cs_packet_next_reloc(p, &reloc); 1075 r = r600_cs_packet_next_reloc(p, &reloc);
@@ -1059,6 +1082,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1059 break; 1082 break;
1060 case R_028238_CB_TARGET_MASK: 1083 case R_028238_CB_TARGET_MASK:
1061 track->cb_target_mask = radeon_get_ib_value(p, idx); 1084 track->cb_target_mask = radeon_get_ib_value(p, idx);
1085 track->cb_dirty = true;
1062 break; 1086 break;
1063 case R_02823C_CB_SHADER_MASK: 1087 case R_02823C_CB_SHADER_MASK:
1064 track->cb_shader_mask = radeon_get_ib_value(p, idx); 1088 track->cb_shader_mask = radeon_get_ib_value(p, idx);
@@ -1066,6 +1090,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1066 case R_028C04_PA_SC_AA_CONFIG: 1090 case R_028C04_PA_SC_AA_CONFIG:
1067 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); 1091 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1068 track->nsamples = 1 << tmp; 1092 track->nsamples = 1 << tmp;
1093 track->cb_dirty = true;
1069 break; 1094 break;
1070 case R_0280A0_CB_COLOR0_INFO: 1095 case R_0280A0_CB_COLOR0_INFO:
1071 case R_0280A4_CB_COLOR1_INFO: 1096 case R_0280A4_CB_COLOR1_INFO:
@@ -1095,6 +1120,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1095 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; 1120 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1096 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1121 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1097 } 1122 }
1123 track->cb_dirty = true;
1098 break; 1124 break;
1099 case R_028080_CB_COLOR0_VIEW: 1125 case R_028080_CB_COLOR0_VIEW:
1100 case R_028084_CB_COLOR1_VIEW: 1126 case R_028084_CB_COLOR1_VIEW:
@@ -1106,6 +1132,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1106 case R_02809C_CB_COLOR7_VIEW: 1132 case R_02809C_CB_COLOR7_VIEW:
1107 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4; 1133 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1108 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); 1134 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1135 track->cb_dirty = true;
1109 break; 1136 break;
1110 case R_028060_CB_COLOR0_SIZE: 1137 case R_028060_CB_COLOR0_SIZE:
1111 case R_028064_CB_COLOR1_SIZE: 1138 case R_028064_CB_COLOR1_SIZE:
@@ -1118,6 +1145,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1118 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4; 1145 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1119 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); 1146 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1120 track->cb_color_size_idx[tmp] = idx; 1147 track->cb_color_size_idx[tmp] = idx;
1148 track->cb_dirty = true;
1121 break; 1149 break;
1122 /* This register were added late, there is userspace 1150 /* This register were added late, there is userspace
1123 * which does provide relocation for those but set 1151 * which does provide relocation for those but set
@@ -1200,6 +1228,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1200 track->cb_color_base_last[tmp] = ib[idx]; 1228 track->cb_color_base_last[tmp] = ib[idx];
1201 track->cb_color_bo[tmp] = reloc->robj; 1229 track->cb_color_bo[tmp] = reloc->robj;
1202 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; 1230 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1231 track->cb_dirty = true;
1203 break; 1232 break;
1204 case DB_DEPTH_BASE: 1233 case DB_DEPTH_BASE:
1205 r = r600_cs_packet_next_reloc(p, &reloc); 1234 r = r600_cs_packet_next_reloc(p, &reloc);
@@ -1212,6 +1241,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1212 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1241 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1213 track->db_bo = reloc->robj; 1242 track->db_bo = reloc->robj;
1214 track->db_bo_mc = reloc->lobj.gpu_offset; 1243 track->db_bo_mc = reloc->lobj.gpu_offset;
1244 track->db_dirty = true;
1215 break; 1245 break;
1216 case DB_HTILE_DATA_BASE: 1246 case DB_HTILE_DATA_BASE:
1217 case SQ_PGM_START_FS: 1247 case SQ_PGM_START_FS:
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 04:28:32 -0400