drm/radeon/kms: don't require up to 64k allocations. (v2)

This avoids needing to do a kmalloc > PAGE_SIZE for the main
indirect buffer chunk, it adds an accessor for all reads from
the chunk and caches a single page at a time for subsequent
reads.

changes since v1:
Use a two page pool which should be the most common case
a single packet spanning > PAGE_SIZE will be hit, but I'm
having trouble seeing anywhere we currently generate anything like that.
hopefully proper short page copying at end
added parser_error flag to set deep errors instead of having to test
every ib value fetch.
fixed bug in patch that went to list.

Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 39 insertions, 40 deletions

diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 568c74bfba3..cf7fea5ff2e 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -96,7 +96,6 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                        struct radeon_cs_packet *pkt,
                        unsigned idx, unsigned reg)
 {
-        struct radeon_cs_chunk *ib_chunk;
         struct radeon_cs_reloc *reloc;
         struct r100_cs_track *track;
         volatile uint32_t *ib;
@@ -105,11 +104,11 @@ int r200_packet0_check(struct radeon_cs_parser *p,
         int i;
         int face;
         u32 tile_flags = 0;
+        u32 idx_value;
 
         ib = p->ib->ptr;
-        ib_chunk = &p->chunks[p->chunk_ib_idx];
         track = (struct r100_cs_track *)p->track;
-
+        idx_value = radeon_get_ib_value(p, idx);
         switch (reg) {
         case RADEON_CRTC_GUI_TRIG_VLINE:
                 r = r100_cs_packet_parse_vline(p);
@@ -137,8 +136,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                         return r;
                 }
                 track->zb.robj = reloc->robj;
-                track->zb.offset = ib_chunk->kdata[idx];
-                ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                track->zb.offset = idx_value;
+                ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                 break;
         case RADEON_RB3D_COLOROFFSET:
                 r = r100_cs_packet_next_reloc(p, &reloc);
@@ -149,8 +148,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                         return r;
                 }
                 track->cb[0].robj = reloc->robj;
-                track->cb[0].offset = ib_chunk->kdata[idx];
-                ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                track->cb[0].offset = idx_value;
+                ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                 break;
         case R200_PP_TXOFFSET_0:
         case R200_PP_TXOFFSET_1:
@@ -166,7 +165,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                         r100_cs_dump_packet(p, pkt);
                         return r;
                 }
-                ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                 track->textures[i].robj = reloc->robj;
                 break;
         case R200_PP_CUBIC_OFFSET_F1_0:
@@ -208,12 +207,12 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                         r100_cs_dump_packet(p, pkt);
                         return r;
                 }
-                track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx];
-                ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                track->textures[i].cube_info[face - 1].offset = idx_value;
+                ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                 track->textures[i].cube_info[face - 1].robj = reloc->robj;
                 break;
         case RADEON_RE_WIDTH_HEIGHT:
-                track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
+                track->maxy = ((idx_value >> 16) & 0x7FF);
                 break;
         case RADEON_RB3D_COLORPITCH:
                 r = r100_cs_packet_next_reloc(p, &reloc);
@@ -229,17 +228,17 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
 
-                tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
+                tmp = idx_value & ~(0x7 << 16);
                 tmp |= tile_flags;
                 ib[idx] = tmp;
 
-                track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
+                track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
                 break;
         case RADEON_RB3D_DEPTHPITCH:
-                track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
+                track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
                 break;
         case RADEON_RB3D_CNTL:
-                switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
+                switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
                 case 7:
                 case 8:
                 case 9:
@@ -257,18 +256,18 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                         break;
                 default:
                         DRM_ERROR("Invalid color buffer format (%d) !\n",
-                                  ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
+                                  ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
                         return -EINVAL;
                 }
-                if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) {
+                if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
                         DRM_ERROR("No support for depth xy offset in kms\n");
                         return -EINVAL;
                 }
 
-                track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
+                track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
                 break;
         case RADEON_RB3D_ZSTENCILCNTL:
-                switch (ib_chunk->kdata[idx] & 0xf) {
+                switch (idx_value & 0xf) {
                 case 0:
                         track->zb.cpp = 2;
                         break;
@@ -292,27 +291,27 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                         r100_cs_dump_packet(p, pkt);
                         return r;
                 }
-                ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                 break;
         case RADEON_PP_CNTL:
                 {
-                        uint32_t temp = ib_chunk->kdata[idx] >> 4;
+                        uint32_t temp = idx_value >> 4;
                         for (i = 0; i < track->num_texture; i++)
                                 track->textures[i].enabled = !!(temp & (1 << i));
                 }
                 break;
         case RADEON_SE_VF_CNTL:
-                track->vap_vf_cntl = ib_chunk->kdata[idx];
+                track->vap_vf_cntl = idx_value;
                 break;
         case 0x210c:
                 /* VAP_VF_MAX_VTX_INDX */
-                track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
+                track->max_indx = idx_value & 0x00FFFFFFUL;
                 break;
         case R200_SE_VTX_FMT_0:
-                track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]);
+                track->vtx_size = r200_get_vtx_size_0(idx_value);
                 break;
         case R200_SE_VTX_FMT_1:
-                track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]);
+                track->vtx_size += r200_get_vtx_size_1(idx_value);
                 break;
         case R200_PP_TXSIZE_0:
         case R200_PP_TXSIZE_1:
@@ -321,8 +320,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
         case R200_PP_TXSIZE_4:
         case R200_PP_TXSIZE_5:
                 i = (reg - R200_PP_TXSIZE_0) / 32;
-                track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
-                track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
+                track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
+                track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
                 break;
         case R200_PP_TXPITCH_0:
         case R200_PP_TXPITCH_1:
@@ -331,7 +330,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
         case R200_PP_TXPITCH_4:
         case R200_PP_TXPITCH_5:
                 i = (reg - R200_PP_TXPITCH_0) / 32;
-                track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
+                track->textures[i].pitch = idx_value + 32;
                 break;
         case R200_PP_TXFILTER_0:
         case R200_PP_TXFILTER_1:
@@ -340,12 +339,12 @@ int r200_packet0_check(struct radeon_cs_parser *p,
         case R200_PP_TXFILTER_4:
         case R200_PP_TXFILTER_5:
                 i = (reg - R200_PP_TXFILTER_0) / 32;
-                track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK)
+                track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
                                                  >> R200_MAX_MIP_LEVEL_SHIFT);
-                tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
+                tmp = (idx_value >> 23) & 0x7;
                 if (tmp == 2 || tmp == 6)
                         track->textures[i].roundup_w = false;
-                tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
+                tmp = (idx_value >> 27) & 0x7;
                 if (tmp == 2 || tmp == 6)
                         track->textures[i].roundup_h = false;
                 break;
@@ -364,8 +363,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
         case R200_PP_TXFORMAT_X_4:
         case R200_PP_TXFORMAT_X_5:
                 i = (reg - R200_PP_TXFORMAT_X_0) / 32;
-                track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7;
-                tmp = (ib_chunk->kdata[idx] >> 16) & 0x3;
+                track->textures[i].txdepth = idx_value & 0x7;
+                tmp = (idx_value >> 16) & 0x3;
                 /* 2D, 3D, CUBE */
                 switch (tmp) {
                 case 0:
@@ -389,14 +388,14 @@ int r200_packet0_check(struct radeon_cs_parser *p,
         case R200_PP_TXFORMAT_4:
         case R200_PP_TXFORMAT_5:
                 i = (reg - R200_PP_TXFORMAT_0) / 32;
-                if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) {
+                if (idx_value & R200_TXFORMAT_NON_POWER2) {
                         track->textures[i].use_pitch = 1;
                 } else {
                         track->textures[i].use_pitch = 0;
-                        track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
-                        track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
+                        track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
+                        track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
                 }
-                switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
+                switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
                 case R200_TXFORMAT_I8:
                 case R200_TXFORMAT_RGB332:
                 case R200_TXFORMAT_Y8:
@@ -424,8 +423,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                         track->textures[i].cpp = 4;
                         break;
                 }
-                track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
-                track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
+                track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
+                track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
                 break;
         case R200_PP_CUBIC_FACES_0:
         case R200_PP_CUBIC_FACES_1:
@@ -433,7 +432,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
         case R200_PP_CUBIC_FACES_3:
         case R200_PP_CUBIC_FACES_4:
         case R200_PP_CUBIC_FACES_5:
-                tmp = ib_chunk->kdata[idx];
+                tmp = idx_value;
                 i = (reg - R200_PP_CUBIC_FACES_0) / 32;
                 for (face = 0; face < 4; face++) {
                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);