diff options
author | David S. Miller <davem@davemloft.net> | 2011-09-22 03:23:13 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-09-22 03:23:13 -0400 |
commit | 8decf868790b48a727d7e7ca164f2bcd3c1389c0 (patch) | |
tree | b759a5f861f842af7ea76f9011b579d06e9d5508 /drivers/gpu/drm/radeon/ni.c | |
parent | 3fc72370186be2f9d4d6ef06d99e1caa5d92c564 (diff) | |
parent | d93dc5c4478c1fd5de85a3e8aece9aad7bbae044 (diff) |
Merge branch 'master' of github.com:davem330/net
Conflicts:
MAINTAINERS
drivers/net/Kconfig
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
drivers/net/ethernet/broadcom/tg3.c
drivers/net/wireless/iwlwifi/iwl-pci.c
drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
drivers/net/wireless/rt2x00/rt2800usb.c
drivers/net/wireless/wl12xx/main.c
Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 44c4750f451..99fbd793c08 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -39,6 +39,7 @@ extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); | |||
39 | extern void evergreen_mc_program(struct radeon_device *rdev); | 39 | extern void evergreen_mc_program(struct radeon_device *rdev); |
40 | extern void evergreen_irq_suspend(struct radeon_device *rdev); | 40 | extern void evergreen_irq_suspend(struct radeon_device *rdev); |
41 | extern int evergreen_mc_init(struct radeon_device *rdev); | 41 | extern int evergreen_mc_init(struct radeon_device *rdev); |
42 | extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); | ||
42 | 43 | ||
43 | #define EVERGREEN_PFP_UCODE_SIZE 1120 | 44 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
44 | #define EVERGREEN_PM4_UCODE_SIZE 1376 | 45 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
@@ -669,6 +670,8 @@ static void cayman_gpu_init(struct radeon_device *rdev) | |||
669 | 670 | ||
670 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | 671 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
671 | 672 | ||
673 | evergreen_fix_pci_max_read_req_size(rdev); | ||
674 | |||
672 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); | 675 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); |
673 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); | 676 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
674 | 677 | ||
@@ -1159,6 +1162,7 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1159 | SOFT_RESET_PA | | 1162 | SOFT_RESET_PA | |
1160 | SOFT_RESET_SH | | 1163 | SOFT_RESET_SH | |
1161 | SOFT_RESET_VGT | | 1164 | SOFT_RESET_VGT | |
1165 | SOFT_RESET_SPI | | ||
1162 | SOFT_RESET_SX)); | 1166 | SOFT_RESET_SX)); |
1163 | RREG32(GRBM_SOFT_RESET); | 1167 | RREG32(GRBM_SOFT_RESET); |
1164 | mdelay(15); | 1168 | mdelay(15); |
@@ -1183,7 +1187,8 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1183 | 1187 | ||
1184 | /* Initialize the ring buffer's read and write pointers */ | 1188 | /* Initialize the ring buffer's read and write pointers */ |
1185 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); | 1189 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); |
1186 | WREG32(CP_RB0_WPTR, 0); | 1190 | rdev->cp.wptr = 0; |
1191 | WREG32(CP_RB0_WPTR, rdev->cp.wptr); | ||
1187 | 1192 | ||
1188 | /* set the wb address wether it's enabled or not */ | 1193 | /* set the wb address wether it's enabled or not */ |
1189 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); | 1194 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
@@ -1203,7 +1208,6 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1203 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); | 1208 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); |
1204 | 1209 | ||
1205 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); | 1210 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
1206 | rdev->cp.wptr = RREG32(CP_RB0_WPTR); | ||
1207 | 1211 | ||
1208 | /* ring1 - compute only */ | 1212 | /* ring1 - compute only */ |
1209 | /* Set ring buffer size */ | 1213 | /* Set ring buffer size */ |
@@ -1216,7 +1220,8 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1216 | 1220 | ||
1217 | /* Initialize the ring buffer's read and write pointers */ | 1221 | /* Initialize the ring buffer's read and write pointers */ |
1218 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); | 1222 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); |
1219 | WREG32(CP_RB1_WPTR, 0); | 1223 | rdev->cp1.wptr = 0; |
1224 | WREG32(CP_RB1_WPTR, rdev->cp1.wptr); | ||
1220 | 1225 | ||
1221 | /* set the wb address wether it's enabled or not */ | 1226 | /* set the wb address wether it's enabled or not */ |
1222 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); | 1227 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
@@ -1228,7 +1233,6 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1228 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); | 1233 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); |
1229 | 1234 | ||
1230 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); | 1235 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); |
1231 | rdev->cp1.wptr = RREG32(CP_RB1_WPTR); | ||
1232 | 1236 | ||
1233 | /* ring2 - compute only */ | 1237 | /* ring2 - compute only */ |
1234 | /* Set ring buffer size */ | 1238 | /* Set ring buffer size */ |
@@ -1241,7 +1245,8 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1241 | 1245 | ||
1242 | /* Initialize the ring buffer's read and write pointers */ | 1246 | /* Initialize the ring buffer's read and write pointers */ |
1243 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); | 1247 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); |
1244 | WREG32(CP_RB2_WPTR, 0); | 1248 | rdev->cp2.wptr = 0; |
1249 | WREG32(CP_RB2_WPTR, rdev->cp2.wptr); | ||
1245 | 1250 | ||
1246 | /* set the wb address wether it's enabled or not */ | 1251 | /* set the wb address wether it's enabled or not */ |
1247 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); | 1252 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
@@ -1253,7 +1258,6 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1253 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); | 1258 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); |
1254 | 1259 | ||
1255 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); | 1260 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); |
1256 | rdev->cp2.wptr = RREG32(CP_RB2_WPTR); | ||
1257 | 1261 | ||
1258 | /* start the rings */ | 1262 | /* start the rings */ |
1259 | cayman_cp_start(rdev); | 1263 | cayman_cp_start(rdev); |