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authorMarek Olšák <maraeo@gmail.com>2012-08-09 10:34:16 -0400
committerAlex Deucher <alexander.deucher@amd.com>2012-08-13 10:50:56 -0400
commitb51ad12a36234c1f6707c9c54a414cfca23f3cdb (patch)
treeab10fb4d373e31a260ffe83cef525bee2345b85c /drivers/gpu/drm/radeon/evergreen_cs.c
parentf00245f182fab57c5eed28a50764600b2bf1ccdb (diff)
drm/radeon/kms: add MSAA texture support for r600-evergreen
Most of the checking seems to be in place already. As you can see, log2(number of samples) resides in LAST_LEVEL. This is required for MSAA support (namely for depth-stencil resolve and blitting between MSAA resources). Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_cs.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index f2e5c545c97..e44a62a07fe 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -788,6 +788,13 @@ static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
788 case V_030000_SQ_TEX_DIM_1D_ARRAY: 788 case V_030000_SQ_TEX_DIM_1D_ARRAY:
789 case V_030000_SQ_TEX_DIM_2D_ARRAY: 789 case V_030000_SQ_TEX_DIM_2D_ARRAY:
790 depth = 1; 790 depth = 1;
791 break;
792 case V_030000_SQ_TEX_DIM_2D_MSAA:
793 case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
794 surf.nsamples = 1 << llevel;
795 llevel = 0;
796 depth = 1;
797 break;
791 case V_030000_SQ_TEX_DIM_3D: 798 case V_030000_SQ_TEX_DIM_3D:
792 break; 799 break;
793 default: 800 default: