diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-10-08 17:46:27 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2012-10-15 13:21:02 -0400 |
commit | 3691feea9826771d853d28d37b6b6e34758fa66d (patch) | |
tree | 5000b982be2ea7b4ec4dc4290245d4a0fd4a9c2b /drivers/gpu/drm/radeon/evergreen.c | |
parent | c1a7ca0de38c23a15f652b1693afd56c9f07b16c (diff) |
drm/radeon: check if pcie gen 2 is already enabled (v2)
If so, skip enabling it to save time.
v2: coding style fixes
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index a1f49c5fd74..14313ad43b7 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -3431,9 +3431,14 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) | |||
3431 | if (!(mask & DRM_PCIE_SPEED_50)) | 3431 | if (!(mask & DRM_PCIE_SPEED_50)) |
3432 | return; | 3432 | return; |
3433 | 3433 | ||
3434 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | ||
3435 | if (speed_cntl & LC_CURRENT_DATA_RATE) { | ||
3436 | DRM_INFO("PCIE gen 2 link speeds already enabled\n"); | ||
3437 | return; | ||
3438 | } | ||
3439 | |||
3434 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); | 3440 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
3435 | 3441 | ||
3436 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | ||
3437 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || | 3442 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || |
3438 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { | 3443 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
3439 | 3444 | ||