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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-05-17 12:24:04 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-05-17 12:24:04 -0400
commitac1d426e825ab5778995f2f6f053ca2e6b45c622 (patch)
tree75b91356ca39463e0112931aa6790802fb1e07a2 /drivers/gpu/drm/nouveau/nouveau_irq.c
parentfda0e18c8a7a3e02747c2b045b4fcd2c920410b9 (diff)
parenta3685f00652af83f12b63e3b4ef48f29581ba48b (diff)
Merge branch 'devel-stable' into devel
Conflicts: arch/arm/Kconfig arch/arm/include/asm/system.h arch/arm/mm/Kconfig
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_irq.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c610
1 files changed, 562 insertions, 48 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 95220ddebb4..13e73cee4c4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -51,6 +51,7 @@ nouveau_irq_preinstall(struct drm_device *dev)
51 51
52 if (dev_priv->card_type == NV_50) { 52 if (dev_priv->card_type == NV_50) {
53 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh); 53 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
54 INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
54 INIT_LIST_HEAD(&dev_priv->vbl_waiting); 55 INIT_LIST_HEAD(&dev_priv->vbl_waiting);
55 } 56 }
56} 57}
@@ -311,6 +312,31 @@ nouveau_print_bitfield_names_(uint32_t value,
311#define nouveau_print_bitfield_names(val, namelist) \ 312#define nouveau_print_bitfield_names(val, namelist) \
312 nouveau_print_bitfield_names_((val), (namelist), ARRAY_SIZE(namelist)) 313 nouveau_print_bitfield_names_((val), (namelist), ARRAY_SIZE(namelist))
313 314
315struct nouveau_enum_names {
316 uint32_t value;
317 const char *name;
318};
319
320static void
321nouveau_print_enum_names_(uint32_t value,
322 const struct nouveau_enum_names *namelist,
323 const int namelist_len)
324{
325 /*
326 * Caller must have already printed the KERN_* log level for us.
327 * Also the caller is responsible for adding the newline.
328 */
329 int i;
330 for (i = 0; i < namelist_len; ++i) {
331 if (value == namelist[i].value) {
332 printk("%s", namelist[i].name);
333 return;
334 }
335 }
336 printk("unknown value 0x%08x", value);
337}
338#define nouveau_print_enum_names(val, namelist) \
339 nouveau_print_enum_names_((val), (namelist), ARRAY_SIZE(namelist))
314 340
315static int 341static int
316nouveau_graph_chid_from_grctx(struct drm_device *dev) 342nouveau_graph_chid_from_grctx(struct drm_device *dev)
@@ -427,14 +453,16 @@ nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
427 struct drm_nouveau_private *dev_priv = dev->dev_private; 453 struct drm_nouveau_private *dev_priv = dev->dev_private;
428 uint32_t nsource = trap->nsource, nstatus = trap->nstatus; 454 uint32_t nsource = trap->nsource, nstatus = trap->nstatus;
429 455
430 NV_INFO(dev, "%s - nSource:", id); 456 if (dev_priv->card_type < NV_50) {
431 nouveau_print_bitfield_names(nsource, nsource_names); 457 NV_INFO(dev, "%s - nSource:", id);
432 printk(", nStatus:"); 458 nouveau_print_bitfield_names(nsource, nsource_names);
433 if (dev_priv->card_type < NV_10) 459 printk(", nStatus:");
434 nouveau_print_bitfield_names(nstatus, nstatus_names); 460 if (dev_priv->card_type < NV_10)
435 else 461 nouveau_print_bitfield_names(nstatus, nstatus_names);
436 nouveau_print_bitfield_names(nstatus, nstatus_names_nv10); 462 else
437 printk("\n"); 463 nouveau_print_bitfield_names(nstatus, nstatus_names_nv10);
464 printk("\n");
465 }
438 466
439 NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x " 467 NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x "
440 "Data 0x%08x:0x%08x\n", 468 "Data 0x%08x:0x%08x\n",
@@ -578,27 +606,502 @@ nouveau_pgraph_irq_handler(struct drm_device *dev)
578} 606}
579 607
580static void 608static void
609nv50_pfb_vm_trap(struct drm_device *dev, int display, const char *name)
610{
611 struct drm_nouveau_private *dev_priv = dev->dev_private;
612 uint32_t trap[6];
613 int i, ch;
614 uint32_t idx = nv_rd32(dev, 0x100c90);
615 if (idx & 0x80000000) {
616 idx &= 0xffffff;
617 if (display) {
618 for (i = 0; i < 6; i++) {
619 nv_wr32(dev, 0x100c90, idx | i << 24);
620 trap[i] = nv_rd32(dev, 0x100c94);
621 }
622 for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
623 struct nouveau_channel *chan = dev_priv->fifos[ch];
624
625 if (!chan || !chan->ramin)
626 continue;
627
628 if (trap[1] == chan->ramin->instance >> 12)
629 break;
630 }
631 NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x %08x channel %d\n",
632 name, (trap[5]&0x100?"read":"write"),
633 trap[5]&0xff, trap[4]&0xffff,
634 trap[3]&0xffff, trap[0], trap[2], ch);
635 }
636 nv_wr32(dev, 0x100c90, idx | 0x80000000);
637 } else if (display) {
638 NV_INFO(dev, "%s - no VM fault?\n", name);
639 }
640}
641
642static struct nouveau_enum_names nv50_mp_exec_error_names[] =
643{
644 { 3, "STACK_UNDERFLOW" },
645 { 4, "QUADON_ACTIVE" },
646 { 8, "TIMEOUT" },
647 { 0x10, "INVALID_OPCODE" },
648 { 0x40, "BREAKPOINT" },
649};
650
651static void
652nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
653{
654 struct drm_nouveau_private *dev_priv = dev->dev_private;
655 uint32_t units = nv_rd32(dev, 0x1540);
656 uint32_t addr, mp10, status, pc, oplow, ophigh;
657 int i;
658 int mps = 0;
659 for (i = 0; i < 4; i++) {
660 if (!(units & 1 << (i+24)))
661 continue;
662 if (dev_priv->chipset < 0xa0)
663 addr = 0x408200 + (tpid << 12) + (i << 7);
664 else
665 addr = 0x408100 + (tpid << 11) + (i << 7);
666 mp10 = nv_rd32(dev, addr + 0x10);
667 status = nv_rd32(dev, addr + 0x14);
668 if (!status)
669 continue;
670 if (display) {
671 nv_rd32(dev, addr + 0x20);
672 pc = nv_rd32(dev, addr + 0x24);
673 oplow = nv_rd32(dev, addr + 0x70);
674 ophigh= nv_rd32(dev, addr + 0x74);
675 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
676 "TP %d MP %d: ", tpid, i);
677 nouveau_print_enum_names(status,
678 nv50_mp_exec_error_names);
679 printk(" at %06x warp %d, opcode %08x %08x\n",
680 pc&0xffffff, pc >> 24,
681 oplow, ophigh);
682 }
683 nv_wr32(dev, addr + 0x10, mp10);
684 nv_wr32(dev, addr + 0x14, 0);
685 mps++;
686 }
687 if (!mps && display)
688 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
689 "No MPs claiming errors?\n", tpid);
690}
691
692static void
693nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
694 uint32_t ustatus_new, int display, const char *name)
695{
696 struct drm_nouveau_private *dev_priv = dev->dev_private;
697 int tps = 0;
698 uint32_t units = nv_rd32(dev, 0x1540);
699 int i, r;
700 uint32_t ustatus_addr, ustatus;
701 for (i = 0; i < 16; i++) {
702 if (!(units & (1 << i)))
703 continue;
704 if (dev_priv->chipset < 0xa0)
705 ustatus_addr = ustatus_old + (i << 12);
706 else
707 ustatus_addr = ustatus_new + (i << 11);
708 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
709 if (!ustatus)
710 continue;
711 tps++;
712 switch (type) {
713 case 6: /* texture error... unknown for now */
714 nv50_pfb_vm_trap(dev, display, name);
715 if (display) {
716 NV_ERROR(dev, "magic set %d:\n", i);
717 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
718 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
719 nv_rd32(dev, r));
720 }
721 break;
722 case 7: /* MP error */
723 if (ustatus & 0x00010000) {
724 nv50_pgraph_mp_trap(dev, i, display);
725 ustatus &= ~0x00010000;
726 }
727 break;
728 case 8: /* TPDMA error */
729 {
730 uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
731 uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
732 uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
733 uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
734 uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
735 uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
736 uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
737 nv50_pfb_vm_trap(dev, display, name);
738 /* 2d engine destination */
739 if (ustatus & 0x00000010) {
740 if (display) {
741 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
742 i, e14, e10);
743 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
744 i, e0c, e18, e1c, e20, e24);
745 }
746 ustatus &= ~0x00000010;
747 }
748 /* Render target */
749 if (ustatus & 0x00000040) {
750 if (display) {
751 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
752 i, e14, e10);
753 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
754 i, e0c, e18, e1c, e20, e24);
755 }
756 ustatus &= ~0x00000040;
757 }
758 /* CUDA memory: l[], g[] or stack. */
759 if (ustatus & 0x00000080) {
760 if (display) {
761 if (e18 & 0x80000000) {
762 /* g[] read fault? */
763 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
764 i, e14, e10 | ((e18 >> 24) & 0x1f));
765 e18 &= ~0x1f000000;
766 } else if (e18 & 0xc) {
767 /* g[] write fault? */
768 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
769 i, e14, e10 | ((e18 >> 7) & 0x1f));
770 e18 &= ~0x00000f80;
771 } else {
772 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
773 i, e14, e10);
774 }
775 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
776 i, e0c, e18, e1c, e20, e24);
777 }
778 ustatus &= ~0x00000080;
779 }
780 }
781 break;
782 }
783 if (ustatus) {
784 if (display)
785 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
786 }
787 nv_wr32(dev, ustatus_addr, 0xc0000000);
788 }
789
790 if (!tps && display)
791 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
792}
793
794static void
795nv50_pgraph_trap_handler(struct drm_device *dev)
796{
797 struct nouveau_pgraph_trap trap;
798 uint32_t status = nv_rd32(dev, 0x400108);
799 uint32_t ustatus;
800 int display = nouveau_ratelimit();
801
802
803 if (!status && display) {
804 nouveau_graph_trap_info(dev, &trap);
805 nouveau_graph_dump_trap_info(dev, "PGRAPH_TRAP", &trap);
806 NV_INFO(dev, "PGRAPH_TRAP - no units reporting traps?\n");
807 }
808
809 /* DISPATCH: Relays commands to other units and handles NOTIFY,
810 * COND, QUERY. If you get a trap from it, the command is still stuck
811 * in DISPATCH and you need to do something about it. */
812 if (status & 0x001) {
813 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
814 if (!ustatus && display) {
815 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
816 }
817
818 /* Known to be triggered by screwed up NOTIFY and COND... */
819 if (ustatus & 0x00000001) {
820 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_FAULT");
821 nv_wr32(dev, 0x400500, 0);
822 if (nv_rd32(dev, 0x400808) & 0x80000000) {
823 if (display) {
824 if (nouveau_graph_trapped_channel(dev, &trap.channel))
825 trap.channel = -1;
826 trap.class = nv_rd32(dev, 0x400814);
827 trap.mthd = nv_rd32(dev, 0x400808) & 0x1ffc;
828 trap.subc = (nv_rd32(dev, 0x400808) >> 16) & 0x7;
829 trap.data = nv_rd32(dev, 0x40080c);
830 trap.data2 = nv_rd32(dev, 0x400810);
831 nouveau_graph_dump_trap_info(dev,
832 "PGRAPH_TRAP_DISPATCH_FAULT", &trap);
833 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x\n", nv_rd32(dev, 0x400808));
834 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x\n", nv_rd32(dev, 0x400848));
835 }
836 nv_wr32(dev, 0x400808, 0);
837 } else if (display) {
838 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?\n");
839 }
840 nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
841 nv_wr32(dev, 0x400848, 0);
842 ustatus &= ~0x00000001;
843 }
844 if (ustatus & 0x00000002) {
845 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_QUERY");
846 nv_wr32(dev, 0x400500, 0);
847 if (nv_rd32(dev, 0x40084c) & 0x80000000) {
848 if (display) {
849 if (nouveau_graph_trapped_channel(dev, &trap.channel))
850 trap.channel = -1;
851 trap.class = nv_rd32(dev, 0x400814);
852 trap.mthd = nv_rd32(dev, 0x40084c) & 0x1ffc;
853 trap.subc = (nv_rd32(dev, 0x40084c) >> 16) & 0x7;
854 trap.data = nv_rd32(dev, 0x40085c);
855 trap.data2 = 0;
856 nouveau_graph_dump_trap_info(dev,
857 "PGRAPH_TRAP_DISPATCH_QUERY", &trap);
858 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x\n", nv_rd32(dev, 0x40084c));
859 }
860 nv_wr32(dev, 0x40084c, 0);
861 } else if (display) {
862 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?\n");
863 }
864 ustatus &= ~0x00000002;
865 }
866 if (ustatus && display)
867 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x\n", ustatus);
868 nv_wr32(dev, 0x400804, 0xc0000000);
869 nv_wr32(dev, 0x400108, 0x001);
870 status &= ~0x001;
871 }
872
873 /* TRAPs other than dispatch use the "normal" trap regs. */
874 if (status && display) {
875 nouveau_graph_trap_info(dev, &trap);
876 nouveau_graph_dump_trap_info(dev,
877 "PGRAPH_TRAP", &trap);
878 }
879
880 /* M2MF: Memory to memory copy engine. */
881 if (status & 0x002) {
882 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
883 if (!ustatus && display) {
884 NV_INFO(dev, "PGRAPH_TRAP_M2MF - no ustatus?\n");
885 }
886 if (ustatus & 0x00000001) {
887 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_NOTIFY");
888 ustatus &= ~0x00000001;
889 }
890 if (ustatus & 0x00000002) {
891 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_IN");
892 ustatus &= ~0x00000002;
893 }
894 if (ustatus & 0x00000004) {
895 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_OUT");
896 ustatus &= ~0x00000004;
897 }
898 NV_INFO (dev, "PGRAPH_TRAP_M2MF - %08x %08x %08x %08x\n",
899 nv_rd32(dev, 0x406804),
900 nv_rd32(dev, 0x406808),
901 nv_rd32(dev, 0x40680c),
902 nv_rd32(dev, 0x406810));
903 if (ustatus && display)
904 NV_INFO(dev, "PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x\n", ustatus);
905 /* No sane way found yet -- just reset the bugger. */
906 nv_wr32(dev, 0x400040, 2);
907 nv_wr32(dev, 0x400040, 0);
908 nv_wr32(dev, 0x406800, 0xc0000000);
909 nv_wr32(dev, 0x400108, 0x002);
910 status &= ~0x002;
911 }
912
913 /* VFETCH: Fetches data from vertex buffers. */
914 if (status & 0x004) {
915 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
916 if (!ustatus && display) {
917 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - no ustatus?\n");
918 }
919 if (ustatus & 0x00000001) {
920 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_VFETCH_FAULT");
921 NV_INFO (dev, "PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x\n",
922 nv_rd32(dev, 0x400c00),
923 nv_rd32(dev, 0x400c08),
924 nv_rd32(dev, 0x400c0c),
925 nv_rd32(dev, 0x400c10));
926 ustatus &= ~0x00000001;
927 }
928 if (ustatus && display)
929 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x\n", ustatus);
930 nv_wr32(dev, 0x400c04, 0xc0000000);
931 nv_wr32(dev, 0x400108, 0x004);
932 status &= ~0x004;
933 }
934
935 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
936 if (status & 0x008) {
937 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
938 if (!ustatus && display) {
939 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - no ustatus?\n");
940 }
941 if (ustatus & 0x00000001) {
942 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_STRMOUT_FAULT");
943 NV_INFO (dev, "PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x\n",
944 nv_rd32(dev, 0x401804),
945 nv_rd32(dev, 0x401808),
946 nv_rd32(dev, 0x40180c),
947 nv_rd32(dev, 0x401810));
948 ustatus &= ~0x00000001;
949 }
950 if (ustatus && display)
951 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x\n", ustatus);
952 /* No sane way found yet -- just reset the bugger. */
953 nv_wr32(dev, 0x400040, 0x80);
954 nv_wr32(dev, 0x400040, 0);
955 nv_wr32(dev, 0x401800, 0xc0000000);
956 nv_wr32(dev, 0x400108, 0x008);
957 status &= ~0x008;
958 }
959
960 /* CCACHE: Handles code and c[] caches and fills them. */
961 if (status & 0x010) {
962 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
963 if (!ustatus && display) {
964 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - no ustatus?\n");
965 }
966 if (ustatus & 0x00000001) {
967 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_CCACHE_FAULT");
968 NV_INFO (dev, "PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x\n",
969 nv_rd32(dev, 0x405800),
970 nv_rd32(dev, 0x405804),
971 nv_rd32(dev, 0x405808),
972 nv_rd32(dev, 0x40580c),
973 nv_rd32(dev, 0x405810),
974 nv_rd32(dev, 0x405814),
975 nv_rd32(dev, 0x40581c));
976 ustatus &= ~0x00000001;
977 }
978 if (ustatus && display)
979 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x\n", ustatus);
980 nv_wr32(dev, 0x405018, 0xc0000000);
981 nv_wr32(dev, 0x400108, 0x010);
982 status &= ~0x010;
983 }
984
985 /* Unknown, not seen yet... 0x402000 is the only trap status reg
986 * remaining, so try to handle it anyway. Perhaps related to that
987 * unknown DMA slot on tesla? */
988 if (status & 0x20) {
989 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_UNKC04");
990 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
991 if (display)
992 NV_INFO(dev, "PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x\n", ustatus);
993 nv_wr32(dev, 0x402000, 0xc0000000);
994 /* no status modifiction on purpose */
995 }
996
997 /* TEXTURE: CUDA texturing units */
998 if (status & 0x040) {
999 nv50_pgraph_tp_trap (dev, 6, 0x408900, 0x408600, display,
1000 "PGRAPH_TRAP_TEXTURE");
1001 nv_wr32(dev, 0x400108, 0x040);
1002 status &= ~0x040;
1003 }
1004
1005 /* MP: CUDA execution engines. */
1006 if (status & 0x080) {
1007 nv50_pgraph_tp_trap (dev, 7, 0x408314, 0x40831c, display,
1008 "PGRAPH_TRAP_MP");
1009 nv_wr32(dev, 0x400108, 0x080);
1010 status &= ~0x080;
1011 }
1012
1013 /* TPDMA: Handles TP-initiated uncached memory accesses:
1014 * l[], g[], stack, 2d surfaces, render targets. */
1015 if (status & 0x100) {
1016 nv50_pgraph_tp_trap (dev, 8, 0x408e08, 0x408708, display,
1017 "PGRAPH_TRAP_TPDMA");
1018 nv_wr32(dev, 0x400108, 0x100);
1019 status &= ~0x100;
1020 }
1021
1022 if (status) {
1023 if (display)
1024 NV_INFO(dev, "PGRAPH_TRAP - Unknown trap 0x%08x\n",
1025 status);
1026 nv_wr32(dev, 0x400108, status);
1027 }
1028}
1029
1030/* There must be a *lot* of these. Will take some time to gather them up. */
1031static struct nouveau_enum_names nv50_data_error_names[] =
1032{
1033 { 4, "INVALID_VALUE" },
1034 { 5, "INVALID_ENUM" },
1035 { 8, "INVALID_OBJECT" },
1036 { 0xc, "INVALID_BITFIELD" },
1037 { 0x28, "MP_NO_REG_SPACE" },
1038 { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
1039};
1040
1041static void
581nv50_pgraph_irq_handler(struct drm_device *dev) 1042nv50_pgraph_irq_handler(struct drm_device *dev)
582{ 1043{
1044 struct nouveau_pgraph_trap trap;
1045 int unhandled = 0;
583 uint32_t status; 1046 uint32_t status;
584 1047
585 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) { 1048 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
586 uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE); 1049 /* NOTIFY: You've set a NOTIFY an a command and it's done. */
587
588 if (status & 0x00000001) { 1050 if (status & 0x00000001) {
589 nouveau_pgraph_intr_notify(dev, nsource); 1051 nouveau_graph_trap_info(dev, &trap);
1052 if (nouveau_ratelimit())
1053 nouveau_graph_dump_trap_info(dev,
1054 "PGRAPH_NOTIFY", &trap);
590 status &= ~0x00000001; 1055 status &= ~0x00000001;
591 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001); 1056 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
592 } 1057 }
593 1058
594 if (status & 0x00000010) { 1059 /* COMPUTE_QUERY: Purpose and exact cause unknown, happens
595 nouveau_pgraph_intr_error(dev, nsource | 1060 * when you write 0x200 to 0x50c0 method 0x31c. */
596 NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD); 1061 if (status & 0x00000002) {
1062 nouveau_graph_trap_info(dev, &trap);
1063 if (nouveau_ratelimit())
1064 nouveau_graph_dump_trap_info(dev,
1065 "PGRAPH_COMPUTE_QUERY", &trap);
1066 status &= ~0x00000002;
1067 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000002);
1068 }
597 1069
1070 /* Unknown, never seen: 0x4 */
1071
1072 /* ILLEGAL_MTHD: You used a wrong method for this class. */
1073 if (status & 0x00000010) {
1074 nouveau_graph_trap_info(dev, &trap);
1075 if (nouveau_pgraph_intr_swmthd(dev, &trap))
1076 unhandled = 1;
1077 if (unhandled && nouveau_ratelimit())
1078 nouveau_graph_dump_trap_info(dev,
1079 "PGRAPH_ILLEGAL_MTHD", &trap);
598 status &= ~0x00000010; 1080 status &= ~0x00000010;
599 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010); 1081 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
600 } 1082 }
601 1083
1084 /* ILLEGAL_CLASS: You used a wrong class. */
1085 if (status & 0x00000020) {
1086 nouveau_graph_trap_info(dev, &trap);
1087 if (nouveau_ratelimit())
1088 nouveau_graph_dump_trap_info(dev,
1089 "PGRAPH_ILLEGAL_CLASS", &trap);
1090 status &= ~0x00000020;
1091 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000020);
1092 }
1093
1094 /* DOUBLE_NOTIFY: You tried to set a NOTIFY on another NOTIFY. */
1095 if (status & 0x00000040) {
1096 nouveau_graph_trap_info(dev, &trap);
1097 if (nouveau_ratelimit())
1098 nouveau_graph_dump_trap_info(dev,
1099 "PGRAPH_DOUBLE_NOTIFY", &trap);
1100 status &= ~0x00000040;
1101 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000040);
1102 }
1103
1104 /* CONTEXT_SWITCH: PGRAPH needs us to load a new context */
602 if (status & 0x00001000) { 1105 if (status & 0x00001000) {
603 nv_wr32(dev, 0x400500, 0x00000000); 1106 nv_wr32(dev, 0x400500, 0x00000000);
604 nv_wr32(dev, NV03_PGRAPH_INTR, 1107 nv_wr32(dev, NV03_PGRAPH_INTR,
@@ -613,49 +1116,59 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
613 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; 1116 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
614 } 1117 }
615 1118
616 if (status & 0x00100000) { 1119 /* BUFFER_NOTIFY: Your m2mf transfer finished */
617 nouveau_pgraph_intr_error(dev, nsource | 1120 if (status & 0x00010000) {
618 NV03_PGRAPH_NSOURCE_DATA_ERROR); 1121 nouveau_graph_trap_info(dev, &trap);
1122 if (nouveau_ratelimit())
1123 nouveau_graph_dump_trap_info(dev,
1124 "PGRAPH_BUFFER_NOTIFY", &trap);
1125 status &= ~0x00010000;
1126 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00010000);
1127 }
619 1128
1129 /* DATA_ERROR: Invalid value for this method, or invalid
1130 * state in current PGRAPH context for this operation */
1131 if (status & 0x00100000) {
1132 nouveau_graph_trap_info(dev, &trap);
1133 if (nouveau_ratelimit()) {
1134 nouveau_graph_dump_trap_info(dev,
1135 "PGRAPH_DATA_ERROR", &trap);
1136 NV_INFO (dev, "PGRAPH_DATA_ERROR - ");
1137 nouveau_print_enum_names(nv_rd32(dev, 0x400110),
1138 nv50_data_error_names);
1139 printk("\n");
1140 }
620 status &= ~0x00100000; 1141 status &= ~0x00100000;
621 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000); 1142 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
622 } 1143 }
623 1144
1145 /* TRAP: Something bad happened in the middle of command
1146 * execution. Has a billion types, subtypes, and even
1147 * subsubtypes. */
624 if (status & 0x00200000) { 1148 if (status & 0x00200000) {
625 int r; 1149 nv50_pgraph_trap_handler(dev);
626
627 nouveau_pgraph_intr_error(dev, nsource |
628 NV03_PGRAPH_NSOURCE_PROTECTION_ERROR);
629
630 NV_ERROR(dev, "magic set 1:\n");
631 for (r = 0x408900; r <= 0x408910; r += 4)
632 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
633 nv_rd32(dev, r));
634 nv_wr32(dev, 0x408900,
635 nv_rd32(dev, 0x408904) | 0xc0000000);
636 for (r = 0x408e08; r <= 0x408e24; r += 4)
637 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
638 nv_rd32(dev, r));
639 nv_wr32(dev, 0x408e08,
640 nv_rd32(dev, 0x408e08) | 0xc0000000);
641
642 NV_ERROR(dev, "magic set 2:\n");
643 for (r = 0x409900; r <= 0x409910; r += 4)
644 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
645 nv_rd32(dev, r));
646 nv_wr32(dev, 0x409900,
647 nv_rd32(dev, 0x409904) | 0xc0000000);
648 for (r = 0x409e08; r <= 0x409e24; r += 4)
649 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
650 nv_rd32(dev, r));
651 nv_wr32(dev, 0x409e08,
652 nv_rd32(dev, 0x409e08) | 0xc0000000);
653
654 status &= ~0x00200000; 1150 status &= ~0x00200000;
655 nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource);
656 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000); 1151 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
657 } 1152 }
658 1153
1154 /* Unknown, never seen: 0x00400000 */
1155
1156 /* SINGLE_STEP: Happens on every method if you turned on
1157 * single stepping in 40008c */
1158 if (status & 0x01000000) {
1159 nouveau_graph_trap_info(dev, &trap);
1160 if (nouveau_ratelimit())
1161 nouveau_graph_dump_trap_info(dev,
1162 "PGRAPH_SINGLE_STEP", &trap);
1163 status &= ~0x01000000;
1164 nv_wr32(dev, NV03_PGRAPH_INTR, 0x01000000);
1165 }
1166
1167 /* 0x02000000 happens when you pause a ctxprog...
1168 * but the only way this can happen that I know is by
1169 * poking the relevant MMIO register, and we don't
1170 * do that. */
1171
659 if (status) { 1172 if (status) {
660 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", 1173 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
661 status); 1174 status);
@@ -672,7 +1185,8 @@ nv50_pgraph_irq_handler(struct drm_device *dev)
672 } 1185 }
673 1186
674 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); 1187 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
675 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31)); 1188 if (nv_rd32(dev, 0x400824) & (1 << 31))
1189 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
676} 1190}
677 1191
678static void 1192static void
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 07:32:19 -0400