diff options
author | Francisco Jerez <currojerez@riseup.net> | 2010-07-13 09:50:23 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-07-25 21:42:13 -0400 |
commit | 3c7066bca990a440b512663f89680bd1c1cae6c1 (patch) | |
tree | b996194c7560ef735dda344f6feea20677be2ee5 /drivers/gpu/drm/nouveau/nouveau_calc.c | |
parent | 20b240059297d1748f6120f432d0db0db9115c32 (diff) |
drm/nouveau: Add some PFB register defines.
Also collect all the PFB registers in a single place and remove some
duplicated definitions.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_calc.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_calc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_calc.c b/drivers/gpu/drm/nouveau/nouveau_calc.c index 88f9bc0941e..ca85da78484 100644 --- a/drivers/gpu/drm/nouveau/nouveau_calc.c +++ b/drivers/gpu/drm/nouveau/nouveau_calc.c | |||
@@ -200,7 +200,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp, | |||
200 | struct nv_sim_state sim_data; | 200 | struct nv_sim_state sim_data; |
201 | int MClk = nouveau_hw_get_clock(dev, MPLL); | 201 | int MClk = nouveau_hw_get_clock(dev, MPLL); |
202 | int NVClk = nouveau_hw_get_clock(dev, NVPLL); | 202 | int NVClk = nouveau_hw_get_clock(dev, NVPLL); |
203 | uint32_t cfg1 = nvReadFB(dev, NV_PFB_CFG1); | 203 | uint32_t cfg1 = nvReadFB(dev, NV04_PFB_CFG1); |
204 | 204 | ||
205 | sim_data.pclk_khz = VClk; | 205 | sim_data.pclk_khz = VClk; |
206 | sim_data.mclk_khz = MClk; | 206 | sim_data.mclk_khz = MClk; |
@@ -218,7 +218,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp, | |||
218 | sim_data.mem_latency = 3; | 218 | sim_data.mem_latency = 3; |
219 | sim_data.mem_page_miss = 10; | 219 | sim_data.mem_page_miss = 10; |
220 | } else { | 220 | } else { |
221 | sim_data.memory_type = nvReadFB(dev, NV_PFB_CFG0) & 0x1; | 221 | sim_data.memory_type = nvReadFB(dev, NV04_PFB_CFG0) & 0x1; |
222 | sim_data.memory_width = (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; | 222 | sim_data.memory_width = (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; |
223 | sim_data.mem_latency = cfg1 & 0xf; | 223 | sim_data.mem_latency = cfg1 & 0xf; |
224 | sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); | 224 | sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); |