drm/nouveau: introduce new gart type, and name _SGDMA more appropriately

In preparation for the addition of a new nv40 backend, we'll need to be
able to distinguish between a paged dma object and the on-chip GART.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 4 insertions, 2 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index d38a4d9f9b0..bf260af18b3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -382,7 +382,8 @@ nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
         case NOUVEAU_GART_AGP:
                 return ttm_agp_backend_init(bdev, dev->agp->bridge);
 #endif
-        case NOUVEAU_GART_SGDMA:
+        case NOUVEAU_GART_PDMA:
+        case NOUVEAU_GART_HW:
                 return nouveau_sgdma_init_ttm(dev);
         default:
                 NV_ERROR(dev, "Unknown GART type %d\n",
@@ -436,7 +437,8 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
                                 TTM_PL_FLAG_WC;
                         man->default_caching = TTM_PL_FLAG_WC;
                         break;
-                case NOUVEAU_GART_SGDMA:
+                case NOUVEAU_GART_PDMA:
+                case NOUVEAU_GART_HW:
                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
                                      TTM_MEMTYPE_FLAG_CMA;
                         man->available_caching = TTM_PL_MASK_CACHING;