drm/nouveau/dp: remove last bits of VBIOS parsing from DRM code

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

8 files changed, 96 insertions, 1 deletions

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
index 3fb5920b6be..a6bb931450f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
@@ -26,6 +26,12 @@ struct nv50_disp_priv {
                 int (*power)(struct nv50_disp_priv *, int sor, u32 data);
                 int (*hda_eld)(struct nv50_disp_priv *, int sor, u8 *, u32);
                 int (*hdmi)(struct nv50_disp_priv *, int head, int sor, u32);
+                int (*dp_train_init)(struct nv50_disp_priv *, int sor, int link,
+                                     int head, u16 type, u16 mask, u32 data,
+                                     struct dcb_output *);
+                int (*dp_train_fini)(struct nv50_disp_priv *, int sor, int link,
+                                     int head, u16 type, u16 mask, u32 data,
+                                     struct dcb_output *);
                 int (*dp_train)(struct nv50_disp_priv *, int sor, int link,
                                 u16 type, u16 mask, u32 data,
                                 struct dcb_output *);
@@ -57,6 +63,10 @@ int nvd0_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);
 int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32);
 int nv50_sor_power(struct nv50_disp_priv *, int, u32);
 
+int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16,
+                           u32, struct dcb_output *);
+int nv94_sor_dp_train_fini(struct nv50_disp_priv *, int, int, int, u16, u16,
+                           u32, struct dcb_output *);
 int nv94_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,
                       struct dcb_output *);
 int nv94_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
index b5adcc0bc0d..ba9dfd4669a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
@@ -87,6 +87,8 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         priv->sor.power = nv50_sor_power;
         priv->sor.hdmi = nv84_hdmi_ctrl;
         priv->sor.dp_train = nv94_sor_dp_train;
+        priv->sor.dp_train_init = nv94_sor_dp_train_init;
+        priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
         priv->sor.dp_lnkctl = nv94_sor_dp_lnkctl;
         priv->sor.dp_drvctl = nv94_sor_dp_drvctl;
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
index 83ae695ac1d..e9192ca389f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
@@ -89,6 +89,8 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         priv->sor.hda_eld = nva3_hda_eld;
         priv->sor.hdmi = nva3_hdmi_ctrl;
         priv->sor.dp_train = nv94_sor_dp_train;
+        priv->sor.dp_train_init = nv94_sor_dp_train_init;
+        priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
         priv->sor.dp_lnkctl = nv94_sor_dp_lnkctl;
         priv->sor.dp_drvctl = nv94_sor_dp_drvctl;
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index a618f2213a1..24bcbc6a88b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -951,6 +951,8 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         priv->sor.hda_eld = nvd0_hda_eld;
         priv->sor.hdmi = nvd0_hdmi_ctrl;
         priv->sor.dp_train = nvd0_sor_dp_train;
+        priv->sor.dp_train_init = nv94_sor_dp_train_init;
+        priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
         priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;
         priv->sor.dp_drvctl = nvd0_sor_dp_drvctl;
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
index 9b83a70091f..259537c4587 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
@@ -72,6 +72,8 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         priv->sor.hda_eld = nvd0_hda_eld;
         priv->sor.hdmi = nvd0_hdmi_ctrl;
         priv->sor.dp_train = nvd0_sor_dp_train;
+        priv->sor.dp_train_init = nv94_sor_dp_train_init;
+        priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
         priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;
         priv->sor.dp_drvctl = nvd0_sor_dp_drvctl;
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
index 6fd25730a58..39b6b67732d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
@@ -80,7 +80,19 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
                 ret = 0;
                 break;
         case NV94_DISP_SOR_DP_TRAIN:
-                ret = priv->sor.dp_train(priv, or, link, type, mask, data, &outp);
+                switch (data & NV94_DISP_SOR_DP_TRAIN_OP) {
+                case NV94_DISP_SOR_DP_TRAIN_OP_PATTERN:
+                        ret = priv->sor.dp_train(priv, or, link, type, mask, data, &outp);
+                        break;
+                case NV94_DISP_SOR_DP_TRAIN_OP_INIT:
+                        ret = priv->sor.dp_train_init(priv, or, link, head, type, mask, data, &outp);
+                        break;
+                case NV94_DISP_SOR_DP_TRAIN_OP_FINI:
+                        ret = priv->sor.dp_train_fini(priv, or, link, head, type, mask, data, &outp);
+                        break;
+                default:
+                        break;
+                }
                 break;
         case NV94_DISP_SOR_DP_LNKCTL:
                 ret = priv->sor.dp_lnkctl(priv, or, link, head, type, mask, data, &outp);
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
index 49bcc76261e..f6edd009762 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
@@ -43,6 +43,64 @@ nv94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
 }
 
 int
+nv94_sor_dp_train_init(struct nv50_disp_priv *priv, int or, int link, int head,
+                       u16 type, u16 mask, u32 data, struct dcb_output *dcbo)
+{
+        struct nouveau_bios *bios = nouveau_bios(priv);
+        struct nvbios_dpout info;
+        u8  ver, hdr, cnt, len;
+        u16 outp;
+
+        outp = nvbios_dpout_match(bios, type, mask, &ver, &hdr, &cnt, &len, &info);
+        if (outp) {
+                struct nvbios_init init = {
+                        .subdev = nv_subdev(priv),
+                        .bios = bios,
+                        .outp = dcbo,
+                        .crtc = head,
+                        .execute = 1,
+                };
+
+                if (data & NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON)
+                        init.offset = info.script[2];
+                else
+                        init.offset = info.script[3];
+                nvbios_exec(&init);
+
+                init.offset = info.script[0];
+                nvbios_exec(&init);
+        }
+
+        return 0;
+}
+
+int
+nv94_sor_dp_train_fini(struct nv50_disp_priv *priv, int or, int link, int head,
+                       u16 type, u16 mask, u32 data, struct dcb_output *dcbo)
+{
+        struct nouveau_bios *bios = nouveau_bios(priv);
+        struct nvbios_dpout info;
+        u8  ver, hdr, cnt, len;
+        u16 outp;
+
+        outp = nvbios_dpout_match(bios, type, mask, &ver, &hdr, &cnt, &len, &info);
+        if (outp) {
+                struct nvbios_init init = {
+                        .subdev = nv_subdev(priv),
+                        .bios = bios,
+                        .offset = info.script[1],
+                        .outp = dcbo,
+                        .crtc = head,
+                        .execute = 1,
+                };
+
+                nvbios_exec(&init);
+        }
+
+        return 0;
+}
+
+int
 nv94_sor_dp_train(struct nv50_disp_priv *priv, int or, int link,
                   u16 type, u16 mask, u32 data, struct dcb_output *info)
 {
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
index dd060234b0b..47c4b3a5bd3 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/class.h
@@ -191,6 +191,13 @@ struct nve0_channel_ind_class {
 #define NV50_DISP_SOR_LVDS_SCRIPT                                    0x00013000
 #define NV50_DISP_SOR_LVDS_SCRIPT_ID                                 0x0000ffff
 #define NV94_DISP_SOR_DP_TRAIN                                       0x00016000
+#define NV94_DISP_SOR_DP_TRAIN_OP                                    0xf0000000
+#define NV94_DISP_SOR_DP_TRAIN_OP_PATTERN                            0x00000000
+#define NV94_DISP_SOR_DP_TRAIN_OP_INIT                               0x10000000
+#define NV94_DISP_SOR_DP_TRAIN_OP_FINI                               0x20000000
+#define NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD                           0x00000001
+#define NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_OFF                       0x00000000
+#define NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON                        0x00000001
 #define NV94_DISP_SOR_DP_TRAIN_PATTERN                               0x00000003
 #define NV94_DISP_SOR_DP_TRAIN_PATTERN_DISABLED                      0x00000000
 #define NV94_DISP_SOR_DP_LNKCTL                                      0x00016040