drm/nouveau/instmem: completely new implementation, as a subdev module

v2 (Ben Skeggs):
- some fixes for 64KiB PAGE_SIZE
- fix porting issues in (currently unused) nv41/nv44 pciegart code

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

2 files changed, 8 insertions, 10 deletions

diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
index eb5455fed1b..a0258c76685 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
@@ -74,8 +74,8 @@ nv40_mpeg_context_new(struct nouveau_channel *chan, int engine)
         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
         nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
         if ((nv_rd32(dev, 0x003204) & 0x1f) == chan->id)
-                nv_wr32(dev, 0x00330c, ctx->pinst >> 4);
-        nv_wo32(chan->ramfc, 0x54, ctx->pinst >> 4);
+                nv_wr32(dev, 0x00330c, ctx->addr >> 4);
+        nv_wo32(chan->ramfc, 0x54, ctx->addr >> 4);
         nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
@@ -90,7 +90,7 @@ nv40_mpeg_context_del(struct nouveau_channel *chan, int engine)
         struct nouveau_gpuobj *ctx = chan->engctx[engine];
         struct drm_device *dev = chan->dev;
         unsigned long flags;
-        u32 inst = 0x80000000 | (ctx->pinst >> 4);
+        u32 inst = 0x80000000 | (ctx->addr >> 4);
 
         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
         nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
@@ -224,7 +224,7 @@ nv31_mpeg_isr_chid(struct drm_device *dev, u32 inst)
                         continue;
 
                 ctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_MPEG];
-                if (ctx && ctx->pinst == inst)
+                if (ctx && ctx->addr == inst)
                         break;
         }
         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
index 47d37a2f478..4e3292ed80c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
@@ -47,7 +47,6 @@ static int
 nv50_mpeg_context_new(struct nouveau_channel *chan, int engine)
 {
         struct drm_device *dev = chan->dev;
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_gpuobj *ramin = chan->ramin;
         struct nouveau_gpuobj *ctx = NULL;
         int ret;
@@ -60,15 +59,15 @@ nv50_mpeg_context_new(struct nouveau_channel *chan, int engine)
                 return ret;
 
         nv_wo32(ramin, CTX_PTR(dev, 0x00), 0x80190002);
-        nv_wo32(ramin, CTX_PTR(dev, 0x04), ctx->vinst + ctx->size - 1);
-        nv_wo32(ramin, CTX_PTR(dev, 0x08), ctx->vinst);
+        nv_wo32(ramin, CTX_PTR(dev, 0x04), ctx->addr + ctx->size - 1);
+        nv_wo32(ramin, CTX_PTR(dev, 0x08), ctx->addr);
         nv_wo32(ramin, CTX_PTR(dev, 0x0c), 0);
         nv_wo32(ramin, CTX_PTR(dev, 0x10), 0);
         nv_wo32(ramin, CTX_PTR(dev, 0x14), 0x00010000);
 
         nv_wo32(ctx, 0x70, 0x00801ec1);
         nv_wo32(ctx, 0x7c, 0x0000037c);
-        dev_priv->engine.instmem.flush(dev);
+        nvimem_flush(dev);
 
         chan->engctx[engine] = ctx;
         return 0;
@@ -93,7 +92,6 @@ nv50_mpeg_object_new(struct nouveau_channel *chan, int engine,
                      u32 handle, u16 class)
 {
         struct drm_device *dev = chan->dev;
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_gpuobj *obj = NULL;
         int ret;
 
@@ -107,7 +105,7 @@ nv50_mpeg_object_new(struct nouveau_channel *chan, int engine,
         nv_wo32(obj, 0x04, 0x00000000);
         nv_wo32(obj, 0x08, 0x00000000);
         nv_wo32(obj, 0x0c, 0x00000000);
-        dev_priv->engine.instmem.flush(dev);
+        nvimem_flush(dev);
 
         ret = nouveau_ramht_insert(chan, handle, obj);
         nouveau_gpuobj_ref(NULL, &obj);