diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-12-30 13:00:37 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-12-30 13:00:37 -0500 |
commit | 4a490b78cb7e0e5efa44425df72a9fedc1c36366 (patch) | |
tree | 8a867e39c4e555e4ba10772748b0bde8fe789e20 /drivers/gpu/drm/nouveau/core/engine/graph/fuc | |
parent | 8d91a42e54eebc43f4d8f6064751ccba73528275 (diff) | |
parent | d5757dbe79870d825d0dec30074d48683e1d7e9a (diff) |
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull DRM update from Dave Airlie:
"This is a bit larger due to me not bothering to do anything since
before Xmas, and other people working too hard after I had clearly
given up.
It's got the 3 main x86 driver fixes pulls, and a bunch of tegra
fixes, doesn't fix the Ironlake bug yet, but that does seem to be
getting closer.
- radeon: gpu reset fixes and userspace packet support
- i915: watermark fixes, workarounds, i830/845 fix,
- nouveau: nvd9/kepler microcode fixes, accel is now enabled and
working, gk106 support
- tegra: misc fixes."
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (34 commits)
Revert "drm: tegra: protect DC register access with mutex"
drm: tegra: program only one window during modeset
drm: tegra: clean out old gem prototypes
drm: tegra: remove redundant tegra2_tmds_config entry
drm: tegra: protect DC register access with mutex
drm: tegra: don't leave clients host1x member uninitialized
drm: tegra: fix front_porch <-> back_porch mixup
drm/nve0/graph: fix fuc, and enable acceleration on all known chipsets
drm/nvc0/graph: fix fuc, and enable acceleration on GF119
drm/nouveau/bios: cache ramcfg strap on later chipsets
drm/nouveau/mxm: silence output if no bios data
drm/nouveau/bios: parse/display extra version component
drm/nouveau/bios: implement opcode 0xa9
drm/nouveau/bios: update gpio parsing apis to match current design
drm/nouveau: initial support for GK106
drm/radeon: add WAIT_UNTIL to evergreen VM safe reg list
drm/i915: disable shrinker lock stealing for create_mmap_offset
drm/i915: optionally disable shrinker lock stealing
drm/i915: fix flags in dma buf exporting
drm/radeon: add support for MEM_WRITE packet
...
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/graph/fuc')
6 files changed, 191 insertions, 158 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc index 7b715fda276..62ab231cd6b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc | |||
@@ -57,6 +57,11 @@ chipsets: | |||
57 | .b16 #nve4_gpc_mmio_tail | 57 | .b16 #nve4_gpc_mmio_tail |
58 | .b16 #nve4_tpc_mmio_head | 58 | .b16 #nve4_tpc_mmio_head |
59 | .b16 #nve4_tpc_mmio_tail | 59 | .b16 #nve4_tpc_mmio_tail |
60 | .b8 0xe6 0 0 0 | ||
61 | .b16 #nve4_gpc_mmio_head | ||
62 | .b16 #nve4_gpc_mmio_tail | ||
63 | .b16 #nve4_tpc_mmio_head | ||
64 | .b16 #nve4_tpc_mmio_tail | ||
60 | .b8 0 0 0 0 | 65 | .b8 0 0 0 0 |
61 | 66 | ||
62 | // GPC mmio lists | 67 | // GPC mmio lists |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h index 26c2165bad0..09ee4702c8b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h | |||
@@ -34,13 +34,16 @@ uint32_t nve0_grgpc_data[] = { | |||
34 | 0x00000000, | 34 | 0x00000000, |
35 | /* 0x0064: chipsets */ | 35 | /* 0x0064: chipsets */ |
36 | 0x000000e4, | 36 | 0x000000e4, |
37 | 0x01040080, | 37 | 0x0110008c, |
38 | 0x014c0104, | 38 | 0x01580110, |
39 | 0x000000e7, | 39 | 0x000000e7, |
40 | 0x01040080, | 40 | 0x0110008c, |
41 | 0x014c0104, | 41 | 0x01580110, |
42 | 0x000000e6, | ||
43 | 0x0110008c, | ||
44 | 0x01580110, | ||
42 | 0x00000000, | 45 | 0x00000000, |
43 | /* 0x0080: nve4_gpc_mmio_head */ | 46 | /* 0x008c: nve4_gpc_mmio_head */ |
44 | 0x00000380, | 47 | 0x00000380, |
45 | 0x04000400, | 48 | 0x04000400, |
46 | 0x0800040c, | 49 | 0x0800040c, |
@@ -74,8 +77,8 @@ uint32_t nve0_grgpc_data[] = { | |||
74 | 0x14003100, | 77 | 0x14003100, |
75 | 0x000031d0, | 78 | 0x000031d0, |
76 | 0x040031e0, | 79 | 0x040031e0, |
77 | /* 0x0104: nve4_gpc_mmio_tail */ | 80 | /* 0x0110: nve4_gpc_mmio_tail */ |
78 | /* 0x0104: nve4_tpc_mmio_head */ | 81 | /* 0x0110: nve4_tpc_mmio_head */ |
79 | 0x00000048, | 82 | 0x00000048, |
80 | 0x00000064, | 83 | 0x00000064, |
81 | 0x00000088, | 84 | 0x00000088, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc index acfc457654b..0bcfa4d447e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc | |||
@@ -754,6 +754,16 @@ ctx_mmio_exec: | |||
754 | // on load it means: "a save preceeded this load" | 754 | // on load it means: "a save preceeded this load" |
755 | // | 755 | // |
756 | ctx_xfer: | 756 | ctx_xfer: |
757 | // according to mwk, some kind of wait for idle | ||
758 | mov $r15 0xc00 | ||
759 | shl b32 $r15 6 | ||
760 | mov $r14 4 | ||
761 | iowr I[$r15 + 0x200] $r14 | ||
762 | ctx_xfer_idle: | ||
763 | iord $r14 I[$r15 + 0x000] | ||
764 | and $r14 0x2000 | ||
765 | bra ne #ctx_xfer_idle | ||
766 | |||
757 | bra not $p1 #ctx_xfer_pre | 767 | bra not $p1 #ctx_xfer_pre |
758 | bra $p2 #ctx_xfer_pre_load | 768 | bra $p2 #ctx_xfer_pre_load |
759 | ctx_xfer_pre: | 769 | ctx_xfer_pre: |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h index 85a8d556f48..bb03d2a1d57 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h | |||
@@ -799,79 +799,80 @@ uint32_t nvc0_grhub_code[] = { | |||
799 | 0x01fa0613, | 799 | 0x01fa0613, |
800 | 0xf803f806, | 800 | 0xf803f806, |
801 | /* 0x0829: ctx_xfer */ | 801 | /* 0x0829: ctx_xfer */ |
802 | 0x0611f400, | 802 | 0x00f7f100, |
803 | /* 0x082f: ctx_xfer_pre */ | 803 | 0x06f4b60c, |
804 | 0xf01102f4, | 804 | 0xd004e7f0, |
805 | 0x21f510f7, | 805 | /* 0x0836: ctx_xfer_idle */ |
806 | 0x21f50698, | 806 | 0xfecf80fe, |
807 | 0x11f40631, | 807 | 0x00e4f100, |
808 | /* 0x083d: ctx_xfer_pre_load */ | 808 | 0xf91bf420, |
809 | 0x02f7f01c, | 809 | 0xf40611f4, |
810 | 0x065721f5, | 810 | /* 0x0846: ctx_xfer_pre */ |
811 | 0x066621f5, | 811 | 0xf7f01102, |
812 | 0x067821f5, | 812 | 0x9821f510, |
813 | 0x21f5f4bd, | 813 | 0x3121f506, |
814 | 0x21f50657, | 814 | 0x1c11f406, |
815 | /* 0x0856: ctx_xfer_exec */ | 815 | /* 0x0854: ctx_xfer_pre_load */ |
816 | 0x019806b8, | 816 | 0xf502f7f0, |
817 | 0x1427f116, | 817 | 0xf5065721, |
818 | 0x0624b604, | 818 | 0xf5066621, |
819 | 0xf10020d0, | 819 | 0xbd067821, |
820 | 0xf0a500e7, | 820 | 0x5721f5f4, |
821 | 0x1fb941e3, | 821 | 0xb821f506, |
822 | 0x8d21f402, | 822 | /* 0x086d: ctx_xfer_exec */ |
823 | 0xf004e0b6, | 823 | 0x16019806, |
824 | 0x2cf001fc, | 824 | 0x041427f1, |
825 | 0x0124b602, | 825 | 0xd00624b6, |
826 | 0xf405f2fd, | 826 | 0xe7f10020, |
827 | 0x17f18d21, | 827 | 0xe3f0a500, |
828 | 0x13f04afc, | 828 | 0x021fb941, |
829 | 0x0c27f002, | 829 | 0xb68d21f4, |
830 | 0xf50012d0, | 830 | 0xfcf004e0, |
831 | 0xf1020721, | 831 | 0x022cf001, |
832 | 0xf047fc27, | 832 | 0xfd0124b6, |
833 | 0x20d00223, | 833 | 0x21f405f2, |
834 | 0x012cf000, | 834 | 0xfc17f18d, |
835 | 0xd00320b6, | 835 | 0x0213f04a, |
836 | 0xacf00012, | 836 | 0xd00c27f0, |
837 | 0x06a5f001, | 837 | 0x21f50012, |
838 | 0x9800b7f0, | 838 | 0x27f10207, |
839 | 0x0d98140c, | 839 | 0x23f047fc, |
840 | 0x00e7f015, | 840 | 0x0020d002, |
841 | 0x015c21f5, | 841 | 0xb6012cf0, |
842 | 0xf508a7f0, | 842 | 0x12d00320, |
843 | 0xf5010321, | 843 | 0x01acf000, |
844 | 0xf4020721, | 844 | 0xf006a5f0, |
845 | 0xa7f02201, | 845 | 0x0c9800b7, |
846 | 0xc921f40c, | 846 | 0x150d9814, |
847 | 0x0a1017f1, | 847 | 0xf500e7f0, |
848 | 0xf00614b6, | 848 | 0xf0015c21, |
849 | 0x12d00527, | 849 | 0x21f508a7, |
850 | /* 0x08dd: ctx_xfer_post_save_wait */ | 850 | 0x21f50103, |
851 | 0x0012cf00, | 851 | 0x01f40207, |
852 | 0xf40522fd, | 852 | 0x0ca7f022, |
853 | 0x02f4fa1b, | 853 | 0xf1c921f4, |
854 | /* 0x08e9: ctx_xfer_post */ | 854 | 0xb60a1017, |
855 | 0x02f7f032, | 855 | 0x27f00614, |
856 | 0x065721f5, | 856 | 0x0012d005, |
857 | 0x21f5f4bd, | 857 | /* 0x08f4: ctx_xfer_post_save_wait */ |
858 | 0x21f50698, | 858 | 0xfd0012cf, |
859 | 0x21f50226, | 859 | 0x1bf40522, |
860 | 0xf4bd0666, | 860 | 0x3202f4fa, |
861 | 0x065721f5, | 861 | /* 0x0900: ctx_xfer_post */ |
862 | 0x981011f4, | 862 | 0xf502f7f0, |
863 | 0x11fd8001, | 863 | 0xbd065721, |
864 | 0x070bf405, | 864 | 0x9821f5f4, |
865 | 0x07df21f5, | 865 | 0x2621f506, |
866 | /* 0x0914: ctx_xfer_no_post_mmio */ | 866 | 0x6621f502, |
867 | 0x064921f5, | 867 | 0xf5f4bd06, |
868 | /* 0x0918: ctx_xfer_done */ | 868 | 0xf4065721, |
869 | 0x000000f8, | 869 | 0x01981011, |
870 | 0x00000000, | 870 | 0x0511fd80, |
871 | 0x00000000, | 871 | 0xf5070bf4, |
872 | 0x00000000, | 872 | /* 0x092b: ctx_xfer_no_post_mmio */ |
873 | 0x00000000, | 873 | 0xf507df21, |
874 | 0x00000000, | 874 | /* 0x092f: ctx_xfer_done */ |
875 | 0xf8064921, | ||
875 | 0x00000000, | 876 | 0x00000000, |
876 | 0x00000000, | 877 | 0x00000000, |
877 | 0x00000000, | 878 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc index 138eeaa2866..7fe9d7cf486 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc | |||
@@ -44,6 +44,9 @@ chipsets: | |||
44 | .b8 0xe7 0 0 0 | 44 | .b8 0xe7 0 0 0 |
45 | .b16 #nve4_hub_mmio_head | 45 | .b16 #nve4_hub_mmio_head |
46 | .b16 #nve4_hub_mmio_tail | 46 | .b16 #nve4_hub_mmio_tail |
47 | .b8 0xe6 0 0 0 | ||
48 | .b16 #nve4_hub_mmio_head | ||
49 | .b16 #nve4_hub_mmio_tail | ||
47 | .b8 0 0 0 0 | 50 | .b8 0 0 0 0 |
48 | 51 | ||
49 | nve4_hub_mmio_head: | 52 | nve4_hub_mmio_head: |
@@ -680,6 +683,16 @@ ctx_mmio_exec: | |||
680 | // on load it means: "a save preceeded this load" | 683 | // on load it means: "a save preceeded this load" |
681 | // | 684 | // |
682 | ctx_xfer: | 685 | ctx_xfer: |
686 | // according to mwk, some kind of wait for idle | ||
687 | mov $r15 0xc00 | ||
688 | shl b32 $r15 6 | ||
689 | mov $r14 4 | ||
690 | iowr I[$r15 + 0x200] $r14 | ||
691 | ctx_xfer_idle: | ||
692 | iord $r14 I[$r15 + 0x000] | ||
693 | and $r14 0x2000 | ||
694 | bra ne #ctx_xfer_idle | ||
695 | |||
683 | bra not $p1 #ctx_xfer_pre | 696 | bra not $p1 #ctx_xfer_pre |
684 | bra $p2 #ctx_xfer_pre_load | 697 | bra $p2 #ctx_xfer_pre_load |
685 | ctx_xfer_pre: | 698 | ctx_xfer_pre: |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h index decf0c60ca3..e3421af68ab 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h | |||
@@ -30,11 +30,13 @@ uint32_t nve0_grhub_data[] = { | |||
30 | 0x00000000, | 30 | 0x00000000, |
31 | /* 0x005c: chipsets */ | 31 | /* 0x005c: chipsets */ |
32 | 0x000000e4, | 32 | 0x000000e4, |
33 | 0x013c0070, | 33 | 0x01440078, |
34 | 0x000000e7, | 34 | 0x000000e7, |
35 | 0x013c0070, | 35 | 0x01440078, |
36 | 0x000000e6, | ||
37 | 0x01440078, | ||
36 | 0x00000000, | 38 | 0x00000000, |
37 | /* 0x0070: nve4_hub_mmio_head */ | 39 | /* 0x0078: nve4_hub_mmio_head */ |
38 | 0x0417e91c, | 40 | 0x0417e91c, |
39 | 0x04400204, | 41 | 0x04400204, |
40 | 0x18404010, | 42 | 0x18404010, |
@@ -86,9 +88,7 @@ uint32_t nve0_grhub_data[] = { | |||
86 | 0x00408840, | 88 | 0x00408840, |
87 | 0x08408900, | 89 | 0x08408900, |
88 | 0x00408980, | 90 | 0x00408980, |
89 | /* 0x013c: nve4_hub_mmio_tail */ | 91 | /* 0x0144: nve4_hub_mmio_tail */ |
90 | 0x00000000, | ||
91 | 0x00000000, | ||
92 | 0x00000000, | 92 | 0x00000000, |
93 | 0x00000000, | 93 | 0x00000000, |
94 | 0x00000000, | 94 | 0x00000000, |
@@ -781,77 +781,78 @@ uint32_t nve0_grhub_code[] = { | |||
781 | 0x0613f002, | 781 | 0x0613f002, |
782 | 0xf80601fa, | 782 | 0xf80601fa, |
783 | /* 0x07fb: ctx_xfer */ | 783 | /* 0x07fb: ctx_xfer */ |
784 | 0xf400f803, | 784 | 0xf100f803, |
785 | 0x02f40611, | 785 | 0xb60c00f7, |
786 | /* 0x0801: ctx_xfer_pre */ | 786 | 0xe7f006f4, |
787 | 0x10f7f00d, | 787 | 0x80fed004, |
788 | 0x067221f5, | 788 | /* 0x0808: ctx_xfer_idle */ |
789 | /* 0x080b: ctx_xfer_pre_load */ | 789 | 0xf100fecf, |
790 | 0xf01c11f4, | 790 | 0xf42000e4, |
791 | 0x21f502f7, | 791 | 0x11f4f91b, |
792 | 0x21f50631, | 792 | 0x0d02f406, |
793 | 0x21f50640, | 793 | /* 0x0818: ctx_xfer_pre */ |
794 | 0xf4bd0652, | 794 | 0xf510f7f0, |
795 | 0x063121f5, | 795 | 0xf4067221, |
796 | 0x069221f5, | 796 | /* 0x0822: ctx_xfer_pre_load */ |
797 | /* 0x0824: ctx_xfer_exec */ | 797 | 0xf7f01c11, |
798 | 0xf1160198, | 798 | 0x3121f502, |
799 | 0xb6041427, | 799 | 0x4021f506, |
800 | 0x20d00624, | 800 | 0x5221f506, |
801 | 0x00e7f100, | 801 | 0xf5f4bd06, |
802 | 0x41e3f0a5, | 802 | 0xf5063121, |
803 | 0xf4021fb9, | 803 | /* 0x083b: ctx_xfer_exec */ |
804 | 0xe0b68d21, | 804 | 0x98069221, |
805 | 0x01fcf004, | 805 | 0x27f11601, |
806 | 0xb6022cf0, | 806 | 0x24b60414, |
807 | 0xf2fd0124, | 807 | 0x0020d006, |
808 | 0x8d21f405, | 808 | 0xa500e7f1, |
809 | 0x4afc17f1, | 809 | 0xb941e3f0, |
810 | 0xf00213f0, | 810 | 0x21f4021f, |
811 | 0x12d00c27, | 811 | 0x04e0b68d, |
812 | 0x0721f500, | 812 | 0xf001fcf0, |
813 | 0xfc27f102, | 813 | 0x24b6022c, |
814 | 0x0223f047, | 814 | 0x05f2fd01, |
815 | 0xf00020d0, | 815 | 0xf18d21f4, |
816 | 0x20b6012c, | 816 | 0xf04afc17, |
817 | 0x0012d003, | 817 | 0x27f00213, |
818 | 0xf001acf0, | 818 | 0x0012d00c, |
819 | 0xb7f006a5, | 819 | 0x020721f5, |
820 | 0x140c9800, | 820 | 0x47fc27f1, |
821 | 0xf0150d98, | 821 | 0xd00223f0, |
822 | 0x21f500e7, | 822 | 0x2cf00020, |
823 | 0xa7f0015c, | 823 | 0x0320b601, |
824 | 0x0321f508, | 824 | 0xf00012d0, |
825 | 0x0721f501, | 825 | 0xa5f001ac, |
826 | 0x2201f402, | 826 | 0x00b7f006, |
827 | 0xf40ca7f0, | 827 | 0x98140c98, |
828 | 0x17f1c921, | 828 | 0xe7f0150d, |
829 | 0x14b60a10, | 829 | 0x5c21f500, |
830 | 0x0527f006, | 830 | 0x08a7f001, |
831 | /* 0x08ab: ctx_xfer_post_save_wait */ | 831 | 0x010321f5, |
832 | 0xcf0012d0, | 832 | 0x020721f5, |
833 | 0x22fd0012, | 833 | 0xf02201f4, |
834 | 0xfa1bf405, | 834 | 0x21f40ca7, |
835 | /* 0x08b7: ctx_xfer_post */ | 835 | 0x1017f1c9, |
836 | 0xf02e02f4, | 836 | 0x0614b60a, |
837 | 0x21f502f7, | 837 | 0xd00527f0, |
838 | 0xf4bd0631, | 838 | /* 0x08c2: ctx_xfer_post_save_wait */ |
839 | 0x067221f5, | 839 | 0x12cf0012, |
840 | 0x022621f5, | 840 | 0x0522fd00, |
841 | 0x064021f5, | 841 | 0xf4fa1bf4, |
842 | 0x21f5f4bd, | 842 | /* 0x08ce: ctx_xfer_post */ |
843 | 0x11f40631, | 843 | 0xf7f02e02, |
844 | 0x80019810, | 844 | 0x3121f502, |
845 | 0xf40511fd, | 845 | 0xf5f4bd06, |
846 | 0x21f5070b, | 846 | 0xf5067221, |
847 | /* 0x08e2: ctx_xfer_no_post_mmio */ | 847 | 0xf5022621, |
848 | /* 0x08e2: ctx_xfer_done */ | 848 | 0xbd064021, |
849 | 0x00f807b1, | 849 | 0x3121f5f4, |
850 | 0x00000000, | 850 | 0x1011f406, |
851 | 0x00000000, | 851 | 0xfd800198, |
852 | 0x00000000, | 852 | 0x0bf40511, |
853 | 0x00000000, | 853 | 0xb121f507, |
854 | 0x00000000, | 854 | /* 0x08f9: ctx_xfer_no_post_mmio */ |
855 | 0x00000000, | 855 | /* 0x08f9: ctx_xfer_done */ |
856 | 0x0000f807, | ||
856 | 0x00000000, | 857 | 0x00000000, |
857 | }; | 858 | }; |