drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines.

This path, which shouldn't be *that* complicated, is now so littered
with per-chipset tweaks that it's hard to trace the order of what
happens.  HAS_PCH_SPLIT() is the most radical change across chipsets,
so it seems like a natural split to simplify the code.

This first commit just copies the existing code without changing
anything.

v2: updated to track removal of call to intel_enable_plane from i9xx_crtc_mode_set

Signed-off-by: Eric Anholt <eric@anholt.net>
Hella-acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 674 insertions, 7 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a47e5ee5dca..b62136764a2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4516,11 +4516,659 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
 }
 
-static int intel_crtc_mode_set(struct drm_crtc *crtc,
-                               struct drm_display_mode *mode,
-                               struct drm_display_mode *adjusted_mode,
-                               int x, int y,
-                               struct drm_framebuffer *old_fb)
+static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
+                              struct drm_display_mode *mode,
+                              struct drm_display_mode *adjusted_mode,
+                              int x, int y,
+                              struct drm_framebuffer *old_fb)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        int pipe = intel_crtc->pipe;
+        int plane = intel_crtc->plane;
+        u32 fp_reg, dpll_reg;
+        int refclk, num_connectors = 0;
+        intel_clock_t clock, reduced_clock;
+        u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
+        bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
+        bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
+        struct intel_encoder *has_edp_encoder = NULL;
+        struct drm_mode_config *mode_config = &dev->mode_config;
+        struct intel_encoder *encoder;
+        const intel_limit_t *limit;
+        int ret;
+        struct fdi_m_n m_n = {0};
+        u32 reg, temp;
+        u32 lvds_sync = 0;
+        int target_clock;
+
+        drm_vblank_pre_modeset(dev, pipe);
+
+        list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
+                if (encoder->base.crtc != crtc)
+                        continue;
+
+                switch (encoder->type) {
+                case INTEL_OUTPUT_LVDS:
+                        is_lvds = true;
+                        break;
+                case INTEL_OUTPUT_SDVO:
+                case INTEL_OUTPUT_HDMI:
+                        is_sdvo = true;
+                        if (encoder->needs_tv_clock)
+                                is_tv = true;
+                        break;
+                case INTEL_OUTPUT_DVO:
+                        is_dvo = true;
+                        break;
+                case INTEL_OUTPUT_TVOUT:
+                        is_tv = true;
+                        break;
+                case INTEL_OUTPUT_ANALOG:
+                        is_crt = true;
+                        break;
+                case INTEL_OUTPUT_DISPLAYPORT:
+                        is_dp = true;
+                        break;
+                case INTEL_OUTPUT_EDP:
+                        has_edp_encoder = encoder;
+                        break;
+                }
+
+                num_connectors++;
+        }
+
+        if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
+                refclk = dev_priv->lvds_ssc_freq * 1000;
+                DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
+                              refclk / 1000);
+        } else if (!IS_GEN2(dev)) {
+                refclk = 96000;
+                if (HAS_PCH_SPLIT(dev) &&
+                    (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
+                        refclk = 120000; /* 120Mhz refclk */
+        } else {
+                refclk = 48000;
+        }
+
+        /*
+         * Returns a set of divisors for the desired target clock with the given
+         * refclk, or FALSE.  The returned values represent the clock equation:
+         * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+         */
+        limit = intel_limit(crtc, refclk);
+        ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
+        if (!ok) {
+                DRM_ERROR("Couldn't find PLL settings for mode!\n");
+                drm_vblank_post_modeset(dev, pipe);
+                return -EINVAL;
+        }
+
+        /* Ensure that the cursor is valid for the new mode before changing... */
+        intel_crtc_update_cursor(crtc, true);
+
+        if (is_lvds && dev_priv->lvds_downclock_avail) {
+                has_reduced_clock = limit->find_pll(limit, crtc,
+                                                    dev_priv->lvds_downclock,
+                                                    refclk,
+                                                    &reduced_clock);
+                if (has_reduced_clock && (clock.p != reduced_clock.p)) {
+                        /*
+                         * If the different P is found, it means that we can't
+                         * switch the display clock by using the FP0/FP1.
+                         * In such case we will disable the LVDS downclock
+                         * feature.
+                         */
+                        DRM_DEBUG_KMS("Different P is found for "
+                                      "LVDS clock/downclock\n");
+                        has_reduced_clock = 0;
+                }
+        }
+        /* SDVO TV has fixed PLL values depend on its clock range,
+           this mirrors vbios setting. */
+        if (is_sdvo && is_tv) {
+                if (adjusted_mode->clock >= 100000
+                    && adjusted_mode->clock < 140500) {
+                        clock.p1 = 2;
+                        clock.p2 = 10;
+                        clock.n = 3;
+                        clock.m1 = 16;
+                        clock.m2 = 8;
+                } else if (adjusted_mode->clock >= 140500
+                           && adjusted_mode->clock <= 200000) {
+                        clock.p1 = 1;
+                        clock.p2 = 10;
+                        clock.n = 6;
+                        clock.m1 = 12;
+                        clock.m2 = 8;
+                }
+        }
+
+        /* FDI link */
+        if (HAS_PCH_SPLIT(dev)) {
+                int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
+                int lane = 0, link_bw, bpp;
+                /* CPU eDP doesn't require FDI link, so just set DP M/N
+                   according to current link config */
+                if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+                        target_clock = mode->clock;
+                        intel_edp_link_config(has_edp_encoder,
+                                              &lane, &link_bw);
+                } else {
+                        /* [e]DP over FDI requires target mode clock
+                           instead of link clock */
+                        if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
+                                target_clock = mode->clock;
+                        else
+                                target_clock = adjusted_mode->clock;
+
+                        /* FDI is a binary signal running at ~2.7GHz, encoding
+                         * each output octet as 10 bits. The actual frequency
+                         * is stored as a divider into a 100MHz clock, and the
+                         * mode pixel clock is stored in units of 1KHz.
+                         * Hence the bw of each lane in terms of the mode signal
+                         * is:
+                         */
+                        link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
+                }
+
+                /* determine panel color depth */
+                temp = I915_READ(PIPECONF(pipe));
+                temp &= ~PIPE_BPC_MASK;
+                if (is_lvds) {
+                        /* the BPC will be 6 if it is 18-bit LVDS panel */
+                        if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
+                                temp |= PIPE_8BPC;
+                        else
+                                temp |= PIPE_6BPC;
+                } else if (has_edp_encoder) {
+                        switch (dev_priv->edp.bpp/3) {
+                        case 8:
+                                temp |= PIPE_8BPC;
+                                break;
+                        case 10:
+                                temp |= PIPE_10BPC;
+                                break;
+                        case 6:
+                                temp |= PIPE_6BPC;
+                                break;
+                        case 12:
+                                temp |= PIPE_12BPC;
+                                break;
+                        }
+                } else
+                        temp |= PIPE_8BPC;
+                I915_WRITE(PIPECONF(pipe), temp);
+
+                switch (temp & PIPE_BPC_MASK) {
+                case PIPE_8BPC:
+                        bpp = 24;
+                        break;
+                case PIPE_10BPC:
+                        bpp = 30;
+                        break;
+                case PIPE_6BPC:
+                        bpp = 18;
+                        break;
+                case PIPE_12BPC:
+                        bpp = 36;
+                        break;
+                default:
+                        DRM_ERROR("unknown pipe bpc value\n");
+                        bpp = 24;
+                }
+
+                if (!lane) {
+                        /*
+                         * Account for spread spectrum to avoid
+                         * oversubscribing the link. Max center spread
+                         * is 2.5%; use 5% for safety's sake.
+                         */
+                        u32 bps = target_clock * bpp * 21 / 20;
+                        lane = bps / (link_bw * 8) + 1;
+                }
+
+                intel_crtc->fdi_lanes = lane;
+
+                if (pixel_multiplier > 1)
+                        link_bw *= pixel_multiplier;
+                ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
+        }
+
+        /* Ironlake: try to setup display ref clock before DPLL
+         * enabling. This is only under driver's control after
+         * PCH B stepping, previous chipset stepping should be
+         * ignoring this setting.
+         */
+        if (HAS_PCH_SPLIT(dev)) {
+                temp = I915_READ(PCH_DREF_CONTROL);
+                /* Always enable nonspread source */
+                temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+                temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+                temp &= ~DREF_SSC_SOURCE_MASK;
+                temp |= DREF_SSC_SOURCE_ENABLE;
+                I915_WRITE(PCH_DREF_CONTROL, temp);
+
+                POSTING_READ(PCH_DREF_CONTROL);
+                udelay(200);
+
+                if (has_edp_encoder) {
+                        if (intel_panel_use_ssc(dev_priv)) {
+                                temp |= DREF_SSC1_ENABLE;
+                                I915_WRITE(PCH_DREF_CONTROL, temp);
+
+                                POSTING_READ(PCH_DREF_CONTROL);
+                                udelay(200);
+                        }
+                        temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+
+                        /* Enable CPU source on CPU attached eDP */
+                        if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+                                if (intel_panel_use_ssc(dev_priv))
+                                        temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+                                else
+                                        temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+                        } else {
+                                /* Enable SSC on PCH eDP if needed */
+                                if (intel_panel_use_ssc(dev_priv)) {
+                                        DRM_ERROR("enabling SSC on PCH\n");
+                                        temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
+                                }
+                        }
+                        I915_WRITE(PCH_DREF_CONTROL, temp);
+                        POSTING_READ(PCH_DREF_CONTROL);
+                        udelay(200);
+                }
+        }
+
+        if (IS_PINEVIEW(dev)) {
+                fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
+                if (has_reduced_clock)
+                        fp2 = (1 << reduced_clock.n) << 16 |
+                                reduced_clock.m1 << 8 | reduced_clock.m2;
+        } else {
+                fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
+                if (has_reduced_clock)
+                        fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
+                                reduced_clock.m2;
+        }
+
+        /* Enable autotuning of the PLL clock (if permissible) */
+        if (HAS_PCH_SPLIT(dev)) {
+                int factor = 21;
+
+                if (is_lvds) {
+                        if ((intel_panel_use_ssc(dev_priv) &&
+                             dev_priv->lvds_ssc_freq == 100) ||
+                            (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+                                factor = 25;
+                } else if (is_sdvo && is_tv)
+                        factor = 20;
+
+                if (clock.m1 < factor * clock.n)
+                        fp |= FP_CB_TUNE;
+        }
+
+        dpll = 0;
+        if (!HAS_PCH_SPLIT(dev))
+                dpll = DPLL_VGA_MODE_DIS;
+
+        if (!IS_GEN2(dev)) {
+                if (is_lvds)
+                        dpll |= DPLLB_MODE_LVDS;
+                else
+                        dpll |= DPLLB_MODE_DAC_SERIAL;
+                if (is_sdvo) {
+                        int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
+                        if (pixel_multiplier > 1) {
+                                if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+                                        dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
+                                else if (HAS_PCH_SPLIT(dev))
+                                        dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
+                        }
+                        dpll |= DPLL_DVO_HIGH_SPEED;
+                }
+                if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
+                        dpll |= DPLL_DVO_HIGH_SPEED;
+
+                /* compute bitmask from p1 value */
+                if (IS_PINEVIEW(dev))
+                        dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
+                else {
+                        dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+                        /* also FPA1 */
+                        if (HAS_PCH_SPLIT(dev))
+                                dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+                        if (IS_G4X(dev) && has_reduced_clock)
+                                dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+                }
+                switch (clock.p2) {
+                case 5:
+                        dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
+                        break;
+                case 7:
+                        dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
+                        break;
+                case 10:
+                        dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
+                        break;
+                case 14:
+                        dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
+                        break;
+                }
+                if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
+                        dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
+        } else {
+                if (is_lvds) {
+                        dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+                } else {
+                        if (clock.p1 == 2)
+                                dpll |= PLL_P1_DIVIDE_BY_TWO;
+                        else
+                                dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+                        if (clock.p2 == 4)
+                                dpll |= PLL_P2_DIVIDE_BY_4;
+                }
+        }
+
+        if (is_sdvo && is_tv)
+                dpll |= PLL_REF_INPUT_TVCLKINBC;
+        else if (is_tv)
+                /* XXX: just matching BIOS for now */
+                /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
+                dpll |= 3;
+        else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
+                dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
+        else
+                dpll |= PLL_REF_INPUT_DREFCLK;
+
+        /* setup pipeconf */
+        pipeconf = I915_READ(PIPECONF(pipe));
+
+        /* Set up the display plane register */
+        dspcntr = DISPPLANE_GAMMA_ENABLE;
+
+        /* Ironlake's plane is forced to pipe, bit 24 is to
+           enable color space conversion */
+        if (!HAS_PCH_SPLIT(dev)) {
+                if (pipe == 0)
+                        dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
+                else
+                        dspcntr |= DISPPLANE_SEL_PIPE_B;
+        }
+
+        if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
+                /* Enable pixel doubling when the dot clock is > 90% of the (display)
+                 * core speed.
+                 *
+                 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
+                 * pipe == 0 check?
+                 */
+                if (mode->clock >
+                    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
+                        pipeconf |= PIPECONF_DOUBLE_WIDE;
+                else
+                        pipeconf &= ~PIPECONF_DOUBLE_WIDE;
+        }
+
+        if (!HAS_PCH_SPLIT(dev))
+                dpll |= DPLL_VCO_ENABLE;
+
+        DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
+        drm_mode_debug_printmodeline(mode);
+
+        /* assign to Ironlake registers */
+        if (HAS_PCH_SPLIT(dev)) {
+                fp_reg = PCH_FP0(pipe);
+                dpll_reg = PCH_DPLL(pipe);
+        } else {
+                fp_reg = FP0(pipe);
+                dpll_reg = DPLL(pipe);
+        }
+
+        /* PCH eDP needs FDI, but CPU eDP does not */
+        if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+                I915_WRITE(fp_reg, fp);
+                I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+
+                POSTING_READ(dpll_reg);
+                udelay(150);
+        }
+
+        /* enable transcoder DPLL */
+        if (HAS_PCH_CPT(dev)) {
+                temp = I915_READ(PCH_DPLL_SEL);
+                switch (pipe) {
+                case 0:
+                        temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
+                        break;
+                case 1:
+                        temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
+                        break;
+                case 2:
+                        /* FIXME: manage transcoder PLLs? */
+                        temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
+                        break;
+                default:
+                        BUG();
+                }
+                I915_WRITE(PCH_DPLL_SEL, temp);
+
+                POSTING_READ(PCH_DPLL_SEL);
+                udelay(150);
+        }
+
+        /* The LVDS pin pair needs to be on before the DPLLs are enabled.
+         * This is an exception to the general rule that mode_set doesn't turn
+         * things on.
+         */
+        if (is_lvds) {
+                reg = LVDS;
+                if (HAS_PCH_SPLIT(dev))
+                        reg = PCH_LVDS;
+
+                temp = I915_READ(reg);
+                temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
+                if (pipe == 1) {
+                        if (HAS_PCH_CPT(dev))
+                                temp |= PORT_TRANS_B_SEL_CPT;
+                        else
+                                temp |= LVDS_PIPEB_SELECT;
+                } else {
+                        if (HAS_PCH_CPT(dev))
+                                temp &= ~PORT_TRANS_SEL_MASK;
+                        else
+                                temp &= ~LVDS_PIPEB_SELECT;
+                }
+                /* set the corresponsding LVDS_BORDER bit */
+                temp |= dev_priv->lvds_border_bits;
+                /* Set the B0-B3 data pairs corresponding to whether we're going to
+                 * set the DPLLs for dual-channel mode or not.
+                 */
+                if (clock.p2 == 7)
+                        temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
+                else
+                        temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
+
+                /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
+                 * appropriately here, but we need to look more thoroughly into how
+                 * panels behave in the two modes.
+                 */
+                /* set the dithering flag on non-PCH LVDS as needed */
+                if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
+                        if (dev_priv->lvds_dither)
+                                temp |= LVDS_ENABLE_DITHER;
+                        else
+                                temp &= ~LVDS_ENABLE_DITHER;
+                }
+                if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+                        lvds_sync |= LVDS_HSYNC_POLARITY;
+                if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+                        lvds_sync |= LVDS_VSYNC_POLARITY;
+                if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
+                    != lvds_sync) {
+                        char flags[2] = "-+";
+                        DRM_INFO("Changing LVDS panel from "
+                                 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
+                                 flags[!(temp & LVDS_HSYNC_POLARITY)],
+                                 flags[!(temp & LVDS_VSYNC_POLARITY)],
+                                 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
+                                 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
+                        temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
+                        temp |= lvds_sync;
+                }
+                I915_WRITE(reg, temp);
+        }
+
+        /* set the dithering flag and clear for anything other than a panel. */
+        if (HAS_PCH_SPLIT(dev)) {
+                pipeconf &= ~PIPECONF_DITHER_EN;
+                pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
+                if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
+                        pipeconf |= PIPECONF_DITHER_EN;
+                        pipeconf |= PIPECONF_DITHER_TYPE_ST1;
+                }
+        }
+
+        if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+                intel_dp_set_m_n(crtc, mode, adjusted_mode);
+        } else if (HAS_PCH_SPLIT(dev)) {
+                /* For non-DP output, clear any trans DP clock recovery setting.*/
+                I915_WRITE(TRANSDATA_M1(pipe), 0);
+                I915_WRITE(TRANSDATA_N1(pipe), 0);
+                I915_WRITE(TRANSDPLINK_M1(pipe), 0);
+                I915_WRITE(TRANSDPLINK_N1(pipe), 0);
+        }
+
+        if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+                I915_WRITE(dpll_reg, dpll);
+
+                /* Wait for the clocks to stabilize. */
+                POSTING_READ(dpll_reg);
+                udelay(150);
+
+                if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
+                        temp = 0;
+                        if (is_sdvo) {
+                                temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+                                if (temp > 1)
+                                        temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+                                else
+                                        temp = 0;
+                        }
+                        I915_WRITE(DPLL_MD(pipe), temp);
+                } else {
+                        /* The pixel multiplier can only be updated once the
+                         * DPLL is enabled and the clocks are stable.
+                         *
+                         * So write it again.
+                         */
+                        I915_WRITE(dpll_reg, dpll);
+                }
+        }
+
+        intel_crtc->lowfreq_avail = false;
+        if (is_lvds && has_reduced_clock && i915_powersave) {
+                I915_WRITE(fp_reg + 4, fp2);
+                intel_crtc->lowfreq_avail = true;
+                if (HAS_PIPE_CXSR(dev)) {
+                        DRM_DEBUG_KMS("enabling CxSR downclocking\n");
+                        pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
+                }
+        } else {
+                I915_WRITE(fp_reg + 4, fp);
+                if (HAS_PIPE_CXSR(dev)) {
+                        DRM_DEBUG_KMS("disabling CxSR downclocking\n");
+                        pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
+                }
+        }
+
+        if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+                pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+                /* the chip adds 2 halflines automatically */
+                adjusted_mode->crtc_vdisplay -= 1;
+                adjusted_mode->crtc_vtotal -= 1;
+                adjusted_mode->crtc_vblank_start -= 1;
+                adjusted_mode->crtc_vblank_end -= 1;
+                adjusted_mode->crtc_vsync_end -= 1;
+                adjusted_mode->crtc_vsync_start -= 1;
+        } else
+                pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
+
+        I915_WRITE(HTOTAL(pipe),
+                   (adjusted_mode->crtc_hdisplay - 1) |
+                   ((adjusted_mode->crtc_htotal - 1) << 16));
+        I915_WRITE(HBLANK(pipe),
+                   (adjusted_mode->crtc_hblank_start - 1) |
+                   ((adjusted_mode->crtc_hblank_end - 1) << 16));
+        I915_WRITE(HSYNC(pipe),
+                   (adjusted_mode->crtc_hsync_start - 1) |
+                   ((adjusted_mode->crtc_hsync_end - 1) << 16));
+
+        I915_WRITE(VTOTAL(pipe),
+                   (adjusted_mode->crtc_vdisplay - 1) |
+                   ((adjusted_mode->crtc_vtotal - 1) << 16));
+        I915_WRITE(VBLANK(pipe),
+                   (adjusted_mode->crtc_vblank_start - 1) |
+                   ((adjusted_mode->crtc_vblank_end - 1) << 16));
+        I915_WRITE(VSYNC(pipe),
+                   (adjusted_mode->crtc_vsync_start - 1) |
+                   ((adjusted_mode->crtc_vsync_end - 1) << 16));
+
+        /* pipesrc and dspsize control the size that is scaled from,
+         * which should always be the user's requested size.
+         */
+        if (!HAS_PCH_SPLIT(dev)) {
+                I915_WRITE(DSPSIZE(plane),
+                           ((mode->vdisplay - 1) << 16) |
+                           (mode->hdisplay - 1));
+                I915_WRITE(DSPPOS(plane), 0);
+        }
+        I915_WRITE(PIPESRC(pipe),
+                   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
+
+        if (HAS_PCH_SPLIT(dev)) {
+                I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+                I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+                I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+                I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+
+                if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+                        ironlake_set_pll_edp(crtc, adjusted_mode->clock);
+                }
+        }
+
+        I915_WRITE(PIPECONF(pipe), pipeconf);
+        POSTING_READ(PIPECONF(pipe));
+        if (!HAS_PCH_SPLIT(dev))
+                intel_enable_pipe(dev_priv, pipe, false);
+
+        intel_wait_for_vblank(dev, pipe);
+
+        if (IS_GEN5(dev)) {
+                /* enable address swizzle for tiling buffer */
+                temp = I915_READ(DISP_ARB_CTL);
+                I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
+        }
+
+        I915_WRITE(DSPCNTR(plane), dspcntr);
+        POSTING_READ(DSPCNTR(plane));
+
+        ret = intel_pipe_set_base(crtc, x, y, old_fb);
+
+        intel_update_watermarks(dev);
+
+        drm_vblank_post_modeset(dev, pipe);
+
+        return ret;
+}
+
+static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
+                                  struct drm_display_mode *mode,
+                                  struct drm_display_mode *adjusted_mode,
+                                  int x, int y,
+                                  struct drm_framebuffer *old_fb)
 {
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5164,6 +5812,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
         return ret;
 }
 
+static int intel_crtc_mode_set(struct drm_crtc *crtc,
+                               struct drm_display_mode *mode,
+                               struct drm_display_mode *adjusted_mode,
+                               int x, int y,
+                               struct drm_framebuffer *old_fb)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        int ret;
+
+        ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
+                                              x, y, old_fb);
+
+        return ret;
+}
+
 /** Loads the palette/gamma unit for the CRTC with the prepared values */
 void intel_crtc_load_lut(struct drm_crtc *crtc)
 {
@@ -7329,10 +7993,13 @@ static void intel_init_display(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         /* We always want a DPMS function */
-        if (HAS_PCH_SPLIT(dev))
+        if (HAS_PCH_SPLIT(dev)) {
                 dev_priv->display.dpms = ironlake_crtc_dpms;
-        else
+                dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
+        } else {
                 dev_priv->display.dpms = i9xx_crtc_dpms;
+                dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
+        }
 
         if (I915_HAS_FBC(dev)) {
                 if (HAS_PCH_SPLIT(dev)) {