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authorJesse Barnes <jbarnes@virtuousgeek.org>2009-10-08 13:16:48 -0400
committerEric Anholt <eric@anholt.net>2009-11-05 17:47:06 -0500
commit97f5ab6651a996ecefed73e41684422f3b29d9a8 (patch)
tree3a78cd25b38419df94fa5b2f91793f47b5d99b68 /drivers/gpu/drm/i915/intel_display.c
parentd8a2d0e00c0d5a0d55e14b884bff034205015e51 (diff)
drm/i915: add render standby support
Render standy allows the GPU to power down the render unit when idle. In order for this to work, it needs a page of graphics memory to save state. This patch allocates that page and enables the feature on supported chipsets. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c41
1 files changed, 41 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 099f420de57..8945656dc1d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4296,6 +4296,42 @@ void intel_init_clock_gating(struct drm_device *dev)
4296 } else if (IS_I830(dev)) { 4296 } else if (IS_I830(dev)) {
4297 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 4297 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4298 } 4298 }
4299
4300 /*
4301 * GPU can automatically power down the render unit if given a page
4302 * to save state.
4303 */
4304 if (I915_HAS_RC6(dev)) {
4305 struct drm_gem_object *pwrctx;
4306 struct drm_i915_gem_object *obj_priv;
4307 int ret;
4308
4309 pwrctx = drm_gem_object_alloc(dev, 4096);
4310 if (!pwrctx) {
4311 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4312 goto out;
4313 }
4314
4315 ret = i915_gem_object_pin(pwrctx, 4096);
4316 if (ret) {
4317 DRM_ERROR("failed to pin power context: %d\n", ret);
4318 drm_gem_object_unreference(pwrctx);
4319 goto out;
4320 }
4321
4322 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4323
4324 obj_priv = pwrctx->driver_private;
4325
4326 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4327 I915_WRITE(MCHBAR_RENDER_STANDBY,
4328 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4329
4330 dev_priv->pwrctx = pwrctx;
4331 }
4332
4333out:
4334 return;
4299} 4335}
4300 4336
4301/* Set up chip specific display functions */ 4337/* Set up chip specific display functions */
@@ -4450,6 +4486,11 @@ void intel_modeset_cleanup(struct drm_device *dev)
4450 if (dev_priv->display.disable_fbc) 4486 if (dev_priv->display.disable_fbc)
4451 dev_priv->display.disable_fbc(dev); 4487 dev_priv->display.disable_fbc(dev);
4452 4488
4489 if (dev_priv->pwrctx) {
4490 i915_gem_object_unpin(dev_priv->pwrctx);
4491 drm_gem_object_unreference(dev_priv->pwrctx);
4492 }
4493
4453 drm_mode_config_cleanup(dev); 4494 drm_mode_config_cleanup(dev);
4454} 4495}
4455 4496