drm/i915: add Ironlake clock gating workaround for FDI link training

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 349710a8014..5812fc7c5a0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1714,6 +1714,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
         POSTING_READ(reg);
         udelay(150);
 
+        /* Ironlake workaround, enable clock pointer after FDI enable*/
+        I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
+
         reg = FDI_RX_IIR(pipe);
         for (tries = 0; tries < 5; tries++) {
                 temp = I915_READ(reg);
@@ -2192,6 +2195,11 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
         POSTING_READ(reg);
         udelay(100);
 
+        /* Ironlake workaround, disable clock pointer after downing FDI */
+        I915_WRITE(FDI_RX_CHICKEN(pipe),
+                   I915_READ(FDI_RX_CHICKEN(pipe) &
+                             ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
+
         /* still set train pattern 1 */
         reg = FDI_TX_CTL(pipe);
         temp = I915_READ(reg);