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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-20 13:15:30 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-20 13:15:30 -0400
commit43813f399c72aa22e01a680559c1cb5274bf2140 (patch)
tree933c0e7c445b9c3478b5a0db06a162d0d39f00f2 /drivers/gpu/drm/i915/intel_display.c
parenta552f0af753eb4b5bbbe9eff205fe874b04c4583 (diff)
parent0b7af262aba912f52bc6ef76f1bc0960b01b8502 (diff)
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (24 commits) agp/intel: Make intel_i965_mask_memory use dma_addr_t for physical addresses agp: add user mapping support to ATI AGP bridge. drm/i915: enable GEM on PAE. drm/radeon: fix unused variables warning agp: switch AGP to use page array instead of unsigned long array agpgart: detected ALi M???? chipset with M1621 drm/radeon: command stream checker for r3xx-r5xx hardware drm/radeon: Fully initialize LVDS info also when we can't get it from the ROM. radeon: Fix CP byte order on big endian architectures with KMS. agp/uninorth: Handle user memory types. drm/ttm: Add some powerpc cache flush code. radeon: Enable modesetting on non-x86. drm/radeon: Respect AGP cant_use_aperture flag. drm: EDID endianness fixes. drm/radeon: this VRAM vs aperture test is wrong, just remove it. drm/ttm: fix an error path to exit function correctly drm: Apply "Memory fragmentation from lost alignment blocks" ttm: Return -ERESTART when a signal interrupts bo eviction. drm: Remove memory debugging infrastructure. drm/i915: Clear fence register on tiling stride change. ...
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c20
1 files changed, 16 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 028f5b66e3d..3e1c7816211 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -828,19 +828,31 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
828 } 828 }
829 829
830 mutex_lock(&dev->struct_mutex); 830 mutex_lock(&dev->struct_mutex);
831 ret = i915_gem_object_pin(intel_fb->obj, alignment); 831 ret = i915_gem_object_pin(obj, alignment);
832 if (ret != 0) { 832 if (ret != 0) {
833 mutex_unlock(&dev->struct_mutex); 833 mutex_unlock(&dev->struct_mutex);
834 return ret; 834 return ret;
835 } 835 }
836 836
837 ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1); 837 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
838 if (ret != 0) { 838 if (ret != 0) {
839 i915_gem_object_unpin(intel_fb->obj); 839 i915_gem_object_unpin(obj);
840 mutex_unlock(&dev->struct_mutex); 840 mutex_unlock(&dev->struct_mutex);
841 return ret; 841 return ret;
842 } 842 }
843 843
844 /* Pre-i965 needs to install a fence for tiled scan-out */
845 if (!IS_I965G(dev) &&
846 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
847 obj_priv->tiling_mode != I915_TILING_NONE) {
848 ret = i915_gem_object_get_fence_reg(obj);
849 if (ret != 0) {
850 i915_gem_object_unpin(obj);
851 mutex_unlock(&dev->struct_mutex);
852 return ret;
853 }
854 }
855
844 dspcntr = I915_READ(dspcntr_reg); 856 dspcntr = I915_READ(dspcntr_reg);
845 /* Mask out pixel format bits in case we change it */ 857 /* Mask out pixel format bits in case we change it */
846 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 858 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
@@ -860,7 +872,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
860 break; 872 break;
861 default: 873 default:
862 DRM_ERROR("Unknown color depth\n"); 874 DRM_ERROR("Unknown color depth\n");
863 i915_gem_object_unpin(intel_fb->obj); 875 i915_gem_object_unpin(obj);
864 mutex_unlock(&dev->struct_mutex); 876 mutex_unlock(&dev->struct_mutex);
865 return -EINVAL; 877 return -EINVAL;
866 } 878 }