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authorChris Wilson <chris@chris-wilson.co.uk>2010-09-21 06:19:32 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-21 06:19:32 -0400
commite9e5f8e8d373e72f5c39dafde1ce110fc7082118 (patch)
tree2991e33571a59cc2488daef36dcfeab7bddb9d7f /drivers/gpu/drm/i915/i915_suspend.c
parentf899fc64cda8569d0529452aafc0da31c042df2e (diff)
parentdb8c076b9206ea35b1f7299708d5510b17674db2 (diff)
Merge branch 'drm-intel-fixes' into HEAD
Conflicts: drivers/char/agp/intel-agp.c drivers/gpu/drm/i915/intel_crt.c
Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c36
1 files changed, 27 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 5c0de650182..967dcde312b 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -789,16 +789,25 @@ int i915_save_state(struct drm_device *dev)
789 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 789 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
790 790
791 /* Fences */ 791 /* Fences */
792 if (IS_I965G(dev)) { 792 switch (INTEL_INFO(dev)->gen) {
793 case 6:
794 for (i = 0; i < 16; i++)
795 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
796 break;
797 case 5:
798 case 4:
793 for (i = 0; i < 16; i++) 799 for (i = 0; i < 16; i++)
794 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 800 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
795 } else { 801 break;
796 for (i = 0; i < 8; i++) 802 case 3:
797 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
798
799 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 803 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
800 for (i = 0; i < 8; i++) 804 for (i = 0; i < 8; i++)
801 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 805 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
806 case 2:
807 for (i = 0; i < 8; i++)
808 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
809 break;
810
802 } 811 }
803 812
804 return 0; 813 return 0;
@@ -815,15 +824,24 @@ int i915_restore_state(struct drm_device *dev)
815 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 824 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
816 825
817 /* Fences */ 826 /* Fences */
818 if (IS_I965G(dev)) { 827 switch (INTEL_INFO(dev)->gen) {
828 case 6:
829 for (i = 0; i < 16; i++)
830 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
831 break;
832 case 5:
833 case 4:
819 for (i = 0; i < 16; i++) 834 for (i = 0; i < 16; i++)
820 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]); 835 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
821 } else { 836 break;
822 for (i = 0; i < 8; i++) 837 case 3:
823 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]); 838 case 2:
824 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 839 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
825 for (i = 0; i < 8; i++) 840 for (i = 0; i < 8; i++)
826 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]); 841 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
842 for (i = 0; i < 8; i++)
843 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
844 break;
827 } 845 }
828 846
829 i915_restore_display(dev); 847 i915_restore_display(dev);